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hcs12x microcontrollers freescale.com MC9S12XHZ512 data sheet MC9S12XHZ512 rev. 1.02 7/2006 4 .com u datasheet
4 .com u datasheet
MC9S12XHZ512 data sheet MC9S12XHZ512v1 rev. 1.02 7/2006 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 4 freescale semiconductor to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. revision history date revision level description january 5, 2006 01.00 new book april 20, 2006 01.01 updated block guide versions julyl 28, 2006 01.02 made minor corrections freescale and the freescale logo are trademarks of freescale semiconductor, inc. this product incorporates superflash?technology licensed from sst. freescale semiconductor, inc., 2006. all rights reserved. 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 5 list of chapters chapter 1 device overview (MC9S12XHZ512v1) . . . . . . . . . . . . . . . . . . . 25 chapter 2 port integration module (s12xhzpimv1) . . . . . . . . . . . . . . . . . 61 chapter 3 512 kbyte flash module (s12xftx512k4v3). . . . . . . . . . . . . 135 chapter 4 4 kbyte eeprom module (s12xeetx4kv2) . . . . . . . . . . . . . 177 chapter 5 xgate (s12xgatev2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 chapter 6 security (s12x9secv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 chapter 7 clocks and reset generator (crgv6) . . . . . . . . . . . . . . . . . . 345 chapter 8 pierce oscillator (s12xosclcpv1) . . . . . . . . . . . . . . . . . . . . 385 chapter 9 analog-to-digital converter (atd10b16cv4) . . . . . . . . . . . . 391 chapter 10 liquid crystal display (lcd32f4bv1) . . . . . . . . . . . . . . . . . . 425 chapter 11 motor controller (mc10b12cv2). . . . . . . . . . . . . . . . . . . . . . . 443 chapter 12 stepper stall detector (ssdv1). . . . . . . . . . . . . . . . . . . . . . . . 475 chapter 13 inter-integrated circuit (iicv3) . . . . . . . . . . . . . . . . . . . . . . . . 493 chapter 14 freescale? scalable controller area network (mscanv3) . 519 chapter 15 serial communication interface (sciv5) . . . . . . . . . . . . . . . . 577 chapter 16 serial peripheral interface (spiv4) . . . . . . . . . . . . . . . . . . . . . 615 chapter 17 periodic interrupt timer (pit24b4cv1) . . . . . . . . . . . . . . . . . 641 chapter 18 pulse-width modulator (pwm8b8cv1). . . . . . . . . . . . . . . . . . 655 chapter 19 enhanced capture timer (ect16b8cv3). . . . . . . . . . . . . . . . 687 chapter 20 voltage regulator (vreg3v3v5) . . . . . . . . . . . . . . . . . . . . . . 741 chapter 21 background debug module (s12xbdmv2) . . . . . . . . . . . . . . 755 chapter 22 s12x debug (s12xdbgv3) module . . . . . . . . . . . . . . . . . . . . 781 chapter 23 external bus interface (s12xebiv3) . . . . . . . . . . . . . . . . . . . . 823 chapter 24 interrupt (s12xintv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 chapter 25 memory mapping control (s12xmmcv3) . . . . . . . . . . . . . . . . 865 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 6 freescale semiconductor appendix a electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 appendix b package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 appendix c pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 appendix d ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 appendix e detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 7 table of contents chapter 1 device overview (MC9S12XHZ512v1) 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.1.4 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.1.5 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.2.2 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.2.3 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 1.3 system clock description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.4 chip con?uration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.5.1 user modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.5.2 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1.5.3 freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.6 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.6.1 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.6.2 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.7 cop con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.8 atd external trigger input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 chapter 2 port integration module (s12xhzpimv1) 2.1 lntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 2.3.1 port a and port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.2 port c and port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.3 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3.4 port k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.3.5 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.3.6 port ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 8 freescale semiconductor 2.3.7 port l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.3.8 port m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.3.9 port p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.3.10 port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.3.11 port t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.3.12 port u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.13 port v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.3.14 port w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 2.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.4.1 i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.4.2 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.4.3 data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 29 2.4.4 reduced drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.4.5 pull device enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.4.6 polarity select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.4.7 pin con?uration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 2.5.1 reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.6.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 2.6.3 operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 chapter 3 512 kbyte flash module (s12xftx512k4v3) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 36 3.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 38 3.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4.1 flash command operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4.2 flash commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.4.3 illegal flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 72 3.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.3 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 9 3.6 flash module security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.6.1 unsecuring the mcu using backdoor key access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 3.6.2 unsecuring the mcu in special single chip mode using bdm . . . . . . . . . . . . . . . . . 175 3.7 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.7.1 flash reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 75 3.7.2 reset while flash command active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.8.1 description of flash interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 chapter 4 4 kbyte eeprom module (s12xeetx4kv2) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 4.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 78 4.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.4.1 eeprom command operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.4.2 eeprom commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.4.3 illegal eeprom operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 4.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.5.3 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.6 eeprom module security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.6.1 unsecuring the mcu in special single chip mode using bdm . . . . . . . . . . . . . . . . . 208 4.7 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.7.1 eeprom reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.7.2 reset while eeprom command active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.8.1 description of eeprom interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 10 freescale semiconductor chapter 5 xgate (s12xgatev2) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.1.1 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 5.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 5.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14 5.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.4.1 xgate risc core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.4.2 programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.4.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 5.4.4 semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.4.5 software error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.5.1 incoming interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.5.2 outgoing interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.6 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.6.1 debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.6.2 entering debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.6.3 leaving debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.7 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 36 5.8.2 instruction summary and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 5.8.3 cycle notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.8.4 thread execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.8.5 instruction glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.8.6 instruction coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 5.9 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 5.9.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 5.9.2 code example (transmit "hello world!" on sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 chapter 6 security (s12x9secv2) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 6.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 6.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 38 6.1.3 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 6.1.4 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 11 6.1.5 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 6.1.6 reprogramming the security bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.1.7 complete memory erase (special modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 chapter 7 clocks and reset generator (crgv6) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 7.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 7.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 46 7.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 7.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 7.2.1 v ddpll and v sspll ?operating and ground voltage pins . . . . . . . . . . . . . . . . . . . . 348 7.2.2 xfc ?external loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 7.2.3 reset ?reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 7.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 48 7.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 7.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 7.4.1 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 7.4.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 7.4.3 low power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 0 7.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 7.5.1 description of reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 7.5.2 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 81 7.5.3 computer operating properly watchdog (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . 381 7.5.4 power on reset, low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 7.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 7.6.1 real time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 7.6.2 pll lock interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 7.6.3 self clock mode interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 chapter 8 pierce oscillator (s12xosclcpv1) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 8.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 8.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 85 8.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 8.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 8.2.1 v ddpll and v sspll ?operating and ground voltage pins . . . . . . . . . . . . . . . . . . . . 386 8.2.2 extal and xtal ?input and output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 8.2.3 xclks ?input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 88 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 12 freescale semiconductor 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.4.1 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.4.2 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.4.3 wait mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 8.4.4 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 chapter 9 analog-to-digital converter (atd10b16cv4) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 9.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 9.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 91 9.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 9.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 9.2.1 anx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) analog input channel x pins 393 9.2.2 etrig3, etrig2, etrig1, etrig0 ?external trigger pins . . . . . . . . . . . . . . . . . 393 9.2.3 v rh , v rl ?high reference voltage pin, low reference voltage pin . . . . . . . . . . . . 393 9.2.4 v dda , v ssa ?analog circuitry power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . 393 9.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 93 9.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 9.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 9.4.1 analog sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 9.4.2 digital sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 9.4.3 operation in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 9.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 9.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 chapter 10 liquid crystal display (lcd32f4bv1) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 10.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 10.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 10.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 10.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.2.1 bp[3:0] ?analog backplane pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.2.2 fp[31:0] ?analog frontplane pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.2.3 vlcd ?lcd supply voltage pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 13 10.4.1 lcd driver description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 10.4.2 operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 10.4.3 operation in pseudo stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.4.4 operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 10.4.5 lcd waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 chapter 11 motor controller (mc10b12cv2) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 11.2.1 m0c0m/m0c0p/m0c1m/m0c1p ?pwm output pins for motor 0 . . . . . . . . . . . . 446 11.2.2 m1c0m/m1c0p/m1c1m/m1c1p ?pwm output pins for motor 1 . . . . . . . . . . . . 447 11.2.3 m2c0m/m2c0p/m2c1m/m2c1p ?pwm output pins for motor 2 . . . . . . . . . . . . 447 11.2.4 m3c0m/m3c0p/m3c1m/m3c1p ?pwm output pins for motor 3 . . . . . . . . . . . . 447 11.2.5 m4c0m/m4c0p/m4c1m/m4c1p ?pwm output pins for motor 4 . . . . . . . . . . . . 447 11.2.6 m5c0m/m5c0p/m5c1m/m5c1p ?pwm output pins for motor 5 . . . . . . . . . . . . 447 11.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 11.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 11.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 11.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 11.4.2 pwm duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 11.4.3 motor controller counter clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 11.4.4 output switching delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 11.4.5 operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 0 11.4.6 operation in stop and pseudo-stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.6.1 timer counter over?w interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.7 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.7.1 code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 14 freescale semiconductor chapter 12 stepper stall detector (ssdv1) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.1.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 12.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 12.2.1 cosxm/cosxp ?cosine coil pins for motor x . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 12.2.2 sinxm/sinxp ?sine coil pins for motor x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 12.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 12.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 12.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 12.4.1 return to zero modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 85 12.4.2 full step states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 12.4.3 operation in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 12.4.4 stall detection flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 chapter 13 inter-integrated circuit (iicv3) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 13.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 13.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 13.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 13.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.2.1 iic_scl ?serial clock line pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.2.2 iic_sda ?serial data line pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.4.1 i-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.4.2 operation in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.4.3 operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2 13.4.4 operation in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2 13.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 13.7.1 iic programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 15 chapter 14 freescale? scalable controller area network (mscanv3) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 14.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 14.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 14.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 14.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2.1 rxcan ?can receiver input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2.2 txcan ?can transmitter output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2.3 can system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 14.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 14.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 14.3.3 programmers model of message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 14.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 14.4.2 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.4.3 identi?r acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 0 14.4.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.4.5 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 67 14.4.6 reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 14.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 14.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 14.5.1 mscan initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 74 14.5.2 bus-off recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 chapter 15 serial communication interface (sciv5) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.2.1 txd ?transmit pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 0 15.2.2 rxd ?receive pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 0 15.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.3.1 module memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 15.4.1 infrared interface submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 16 freescale semiconductor 15.4.2 lin support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 15.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 15.4.4 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 96 15.4.5 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 15.4.6 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 15.4.7 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 15.4.8 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5.1 reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5.3 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 15.5.4 recovery from wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 15.5.5 recovery from stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 chapter 16 serial peripheral interface (spiv4) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.1 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 16.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.1 mosi ?master out/slave in pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.2 miso ?master in/slave out pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.3 ss ?slave select pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.2.4 sck ?serial clock pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 16.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 16.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 16.4.3 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 31 16.4.4 spi baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 16.4.5 special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 16.4.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 16.4.7 low power mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 17 chapter 17 periodic interrupt timer (pit24b4cv1) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 17.4.1 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 17.4.2 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 17.4.3 hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5.2 shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5.3 flag clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 chapter 18 pulse-width modulator (pwm8b8cv1) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2.1 pwm7 ?pwm channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2.2 pwm6 ?pwm channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2.3 pwm5 ?pwm channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.4 pwm4 ?pwm channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.5 pwm3 ?pwm channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.6 pwm3 ?pwm channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.7 pwm3 ?pwm channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.8 pwm3 ?pwm channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.4.1 pwm clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.4.2 pwm channel timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 18.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 18.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 18 freescale semiconductor chapter 19 enhanced capture timer (ect16b8cv3) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 19.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.1 ioc7 ?input capture and output compare channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.2 ioc6 ?input capture and output compare channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.3 ioc5 ?input capture and output compare channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.4 ioc4 ?input capture and output compare channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.5 ioc3 ?input capture and output compare channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.6 ioc2 ?input capture and output compare channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.7 ioc1 ?input capture and output compare channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.8 ioc0 ?input capture and output compare channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 19.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 19.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 19.4.1 enhanced capture timer modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 19.4.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 19.4.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 chapter 20 voltage regulator (vreg3v3v5) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 20.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.1 vddr ?regulator power input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.2 vdda, vssa ?regulator reference supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.3 vdd, vss ?regulator output1 (core logic) pins . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.4 vddpll, vsspll ?regulator output2 (pll) pins . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.2.5 v regen optional regulator enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 20.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 20.4.2 regulator core (reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0 20.4.3 low-voltage detect (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 19 20.4.4 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.5 low-voltage reset (lvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.6 regulator control (ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.7 autonomous periodical interrupt (api) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.8 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 20.4.9 description of reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 20.4.10interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 chapter 21 background debug module (s12xbdmv2) 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 21.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 21.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 21.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 21.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 21.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 21.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 21.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 21.3.3 family id assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.4.1 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.4.2 enabling and activating bdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.4.3 bdm hardware commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 21.4.4 standard bdm firmware commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 21.4.5 bdm command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 21.4.6 bdm serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 21.4.7 serial interface hardware handshake protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 21.4.8 hardware handshake abort procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 21.4.9 sync ?request timed reference pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 21.4.10instruction tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 21.4.11serial communication time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 chapter 22 s12x debug (s12xdbgv3) module 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 22.1.1 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 22.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 22.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 22.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 22.1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 22.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 22.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 20 freescale semiconductor 22.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 22.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 22.4.1 s12xdbg operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 22.4.2 comparator modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 22.4.3 trigger modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 22.4.4 state sequence control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 22.4.5 trace buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11 22.4.6 tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 22.4.7 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 chapter 23 external bus interface (s12xebiv3) 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 23.1.1 glossary or terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 23.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 23.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 23.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 23.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 23.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 23.4.1 operating modes and external bus properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 23.4.2 internal visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 23.4.3 accesses to port replacement registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 23.4.4 stretched external bus accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 23.4.5 data select and data direction signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 23.4.6 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 40 23.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 23.5.1 normal expanded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 23.5.2 emulation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 chapter 24 interrupt (s12xintv1) 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 24.1.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 24.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 24.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 21 24.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 24.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 24.4.1 s12x exception requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 24.4.2 interrupt prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 24.4.3 xgate requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 24.4.4 priority decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 24.4.5 reset exception requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 24.4.6 exception priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 24.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 24.5.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 24.5.2 interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 24.5.3 wake up from stop or wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 chapter 25 memory mapping control (s12xmmcv3) 25.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 25.1.1 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 25.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 25.1.3 s12x memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 25.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 25.1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 25.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 25.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 25.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 25.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 25.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 25.4.1 mcu operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 25.4.2 memory map scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 25.4.3 chip access restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9 25.4.4 chip bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 25.4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 25.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 25.5.1 call and rtc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 25.5.2 port replacement registers (prrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 25.5.3 on-chip rom control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 25.6 internal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 25.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 25.6.2 s12x system behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 0 25.6.3 s12x_cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 25.6.4 s12x_bdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 25.6.5 xgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 25.6.6 s12x_flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 22 freescale semiconductor 25.6.7 priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 25.6.8 xbus0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.9 xbus1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.10xbus2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.11xbus3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.12xram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 25.7 generic labeling scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 23 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 29 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 a.1.6 esd protection and latch-up immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 a.2 atd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 a.2.1 atd operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 a.2.3 atd accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 a.3 nvm, flash, and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 a.3.1 nvm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 a.3.2 nvm reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948 a.4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 a.5 reset, oscillator, and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 a.5.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 a.5.2 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 a.5.3 phase locked loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 a.6 lcd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 a.7 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 a.8 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 a.8.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 a.8.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 a.9 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 a.9.1 normal expanded mode (external wait feature disabled). . . . . . . . . . . . . . . . . . . . . . 962 a.9.2 normal expanded mode (external wait feature enabled) . . . . . . . . . . . . . . . . . . . . . . 964 a.9.3 emulation single-chip mode (without wait states) . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 a.9.4 emulation expanded mode (with optional access stretching) . . . . . . . . . . . . . . . . . . 969 a.9.5 external tag trigger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 24 freescale semiconductor appendix b package information b.1 144-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 b.2 112-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 appendix c pcb layout guidelines appendix d ordering information appendix e detailed register map 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 25 chapter 1 device overview (MC9S12XHZ512v1) 1.1 introduction targeted at automotive instrumentation applications, the MC9S12XHZ512 microcontroller unit (mcu) is a fully pin-compatible extension to the existing mc9s12hz-family of microcontrollers. it offers not only a larger memory than the existing s12-based family but also incorporates all the architectural bene?s of the new s12x-based family to deliver signi?antly higher performance. the MC9S12XHZ512 retains the low cost, power consumption, emc and code-size ef?iency advantages currently associated with the mc9s12hz-family products. based around s12x core, the MC9S12XHZ512 runs 16-bit wide accesses without wait states for all peripherals and memories. the MC9S12XHZ512 also features a new ?xible interrupt handler, which allows multilevel nested interrupts. the MC9S12XHZ512 features the performance boosting xgate co-processor. the xgate is programmable in ??language and runs at twice the bus frequency of the s12. its instruction set is optimized for data movement, logic and bit manipulation instructions. any peripheral module can be serviced by the xgate. the MC9S12XHZ512 contains 512k bytes of freescale semiconductors industry leading, full automotive quali?d split-gate flash memory, with 4k bytes of additional integrated data eeprom and 32k bytes of static ram. the MC9S12XHZ512 features a 32x4 liquid crystal display (lcd) controller/driver and a motor pulse width modulator (mc) consisting of up to 24 high current outputs suited to drive six stepper motors with stall detectors (ssd) to simultaneously calibrate the pointer reset position of each motor. it also features two mscan modules, each with a fifo receiver buffer arrangement, and input ?ters optimized for gateway applications handling numerous message identi?rs. in addition, the MC9S12XHZ512 is composed of standard on-chip peripherals including two asynchronous serial communications interfaces (sci0 and sci1), one serial peripheral interface (spi), two iic-bus interface (iic0 and iic1), an 8-channel 16-bit enhanced capture timer (ect), a 16-channel, 10-bit analog-to-digital converter (adc), and one 8-channel pulse width modulator (pwm). the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. the new fast-exit from stop mode feature can further improve system power consumption. in addition to the i/o ports available in each module, 8 general-purpose i/o pins are available with interrupt and wake-up capability from stop or wait mode. the MC9S12XHZ512 is available in 112-pin lqfp and 144-pin lqfp packages. the 144-pin lqfp package option provides a full 16-bit wide non-multiplexed external bus interface. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 26 freescale semiconductor 1.1.1 features hcs12x core 16-bit hcs12x cpu upward compatible with mc9s12 instruction set interrupt stacking and programmers model identical to mc9s12 instruction queue enhanced indexed addressing enhanced instruction set ebi (external bus interface) mmc (module mapping control) int (interrupt controller) dbg (debug module to monitor hcs12x cpu and xgate bus activity) bdm (background debug mode) xgate (peripheral coprocessor) parallel processing module off loads the cpu by providing high-speed data processing and transfer data transfer between flash eeprom, ram, peripheral modules, and i/o ports memory 512-kbyte flash eeprom 4-kbyte eeprom 32-kbyte ram crg (clock and reset generator) low noise/low power pierce oscillator pll cop watchdog real time interrupt clock monitor fast wake-up from stop mode analog-to-digital converter 16 channels, 10-bit resolution external conversion trigger capability ect (enhanced capture timer) 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels four 8-bit or two 16-bit pulse accumulators pit (periodic interrupt timer) four timers with independent time-out periods time-out periods selectable between 1 and 2 24 bus clock cycles 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 27 8 pwm (pulse-width modulator) channels programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel separate control for each pulse width and duty cycle center-aligned or left-aligned outputs programmable clock select logic with a wide range of frequencies fast emergency shutdown input two 1-mbps, can 2.0 a, b software compatible modules five receive and three transmit buffers flexible identi?r ?ter programmable as 2 x 32 bit, 4 x 16 bit, or 8x8bit four separate interrupt channels for rx, tx, error, and wake-up low-pass ?ter wake-up function loop-back for self-test operation two iic (inter-ic bus) modules compatible with iic bus standard multi-master operation broadcast mode serial interfaces two asynchronous serial communication interfaces (sci) with additional lin support and selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse width synchronous serial peripheral interface (spi) liquid crystal display (lcd) driver with variable input voltage configurable for up to 32 frontplanes and 4 backplanes or general-purpose input or output 5 modes of operation allow for different display sizes to meet application requirements unused frontplane and backplane pins can be used as general-purpose i/o pwm motor controller (mc) with 24 high current drivers each pwm channel switchable between two drivers in an h-bridge configuration left, right and center aligned outputs support for sine and cosine drive dithering output slew rate control six stepper stall detectors (ssd) full step control during return to zero voltage detector and integrator / sigma delta converter circuit 16-bit accumulator register 16-bit modulus down counter 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 28 freescale semiconductor on-chip voltage regulator two parallel, linear voltage regulators with bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) circuit 3.3-v?.5-v operation low-voltage reset (lvr) ultra low-power wake-up timer 144-pin lqfp and 112-pin lqfp packages i/o lines with 5-v input and drive capability input threshold on external bus interface inputs switchable for 3.3-v or 5-v operation 5-v a/d converter inputs 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger operation at 80 mhz equivalent to 40-mhz bus speed development support single-wire background debug mode (bdm) four on-chip hardware breakpoints 1.1.2 modes of operation user modes: normal and emulation operating modes normal single-chip mode normal expanded mode emulation of single-chip mode emulation of expanded mode special operating modes special single-chip mode with active background debug mode special test mode ( freescale use only ) low-power modes: system stop modes pseudo stop mode full stop mode system wait mode 1.1.3 block diagram figure 1-1 shows a block diagram of the MC9S12XHZ512 device. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 29 figure 1-1. MC9S12XHZ512 block diagram extal xtal bkgd xirq pll xfc irq eclk pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 miso mosi ps4 ps5 ps0 ps1 pk3 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 ddra ddrb pta ptb ddre pte ptk ddrk pts ddrs ptm ddrm pk2 fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 fp22 fp21 fp20 vlcd vlcd lcd driver can0 modb/ taghi moda/ taglo/ re reset vddpll vsspll clock and reset generation module fp13 pb5 pb3 pb2 pb1 fp5 addr16/iqstat0 addr17/iqstat1 addr18/iqstat2 addr19/iqstat3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 fp24 fp25 fp26 fp27 an2 an6 an0 an7 an1 an3 an4 an5 pad3 pad4 pad5 pad6 pad7 pad0 pad1 pad2 vrh vrl vdda vssa analog to digital converter ddrad vrh vrl vdda vssa 512k bytes flash eeprom 4k bytes eeprom 32k bytes ram ew ait/romctl vddr vdd1 vss1,2 voltage regulator enahanced capture timer pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 single-wire background debug module rxcan1 txcan1 pm4 pm5 can1 m0c0m m0c0p pu0 pu1 ptu ddru pwm0 ssd0 m0c1m m0c1p pu2 pu3 pwm1 m1c0m m1c0p pu4 pu5 pwm2 ssd1 m1c1m m1c1p pu6 pu7 pwm3 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 ptp ddrp rxd0 txd0 sci0 an10 an14 an8 an15 an9 an11 an12 an13 an10 an14 an8 an15 an9 an11 an12 an13 kwad2 kwad6 kwad0 kwad7 kwad1 kwad3 kwad4 kwad5 m0cosm m0cosp m0sinm m0sinp m1cosm m1cosp m1sinm m1sinp ptad m2c0m m2c0p pv0 pv1 ptv ddrv pwm4 ssd2 m2c1m m2c1p pv2 pv3 pwm5 m3c0m m3c0p pv4 pv5 pwm6 ssd3 m3c1m m3c1p pv6 pv7 pwm7 m2cosm m2cosp m2sinm m2sinp m3cosm m3cosp m3sinm m3sinp rxd1 txd1 sci1 ps2 ps3 sda0 scl0 pm1 iic0 pp6 pp7 a/d converter & vdda vssa pll supply 2.5v vddpll vsspll i/o supply 5v vddx1,2 vssx1,2 internal 2.5v vdd1 vss1,2 voltage regulator 5v vddr voltage regulator 5v pk7 fp23 pc4 pc0 pc7 pc6 ddrc ptc pc5 pc3 pc2 pc1 data8 data9 data10 data11 data12 data13 data14 data15 pd4 pd0 pd7 pd6 ddrd ptd pd5 pd3 pd2 pd1 data0 data1 data2 data3 data4 data5 data6 data7 pe7 pe2 pe3 xclks/ eclkx2 lstrb/ lds/eromctl r w/ we pt4 pt3 pt2 pt1 pt0 pt7 pt6 pt5 ddrt ptt ioc0 ioc1 ioc2 ioc3 ioc4 ioc5 ioc6 ioc7 non-multiplexed external bus interface sda1 scl1 iic1 sda0 scl0 sda1 scl1 cpu12x periodic interrupt cop watchdog clock monitor breakpoints xgate peripheral 4-channel motor supplies vddm1,2,3 vssm1,2,3 m4c0m m4c0p pw0 pw1 ptw ddrw pwm8 ssd4 m4c1m m4c1p pw2 pw3 pwm9 m5c0m m5c0p pw4 pw5 pwm10 ssd5 m5c1m m5c1p pw6 pw7 pwm11 m4cosm m4cosp m4sinm m4sinp m5cosm m5cosp m5sinm m5sinp pins and signals shown in bold are not available in the 112 qfp package co-processor programmable interrupt timer (pit) for internal timebases enhanced multilevel interrupt module pk4 addr20/acc0 pk5 addr21/acc1 pk6 addr22/acc2 cs1 cs3 cs0 cs2 pw6 pw7 module-to-port-routing 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 30 freescale semiconductor 1.1.4 device memory map table 1-1 shows the device memory map for the MC9S12XHZ512. unimplemented register space shown in table 1-1 is not allocated to any module. writing to these locations have no effect. read access to these locations returns zero. table 1-1. device register memory map address offset module size (bytes) 0x0000?x0009 pim (port integration module ) 10 0x000a?x000b mmc (memory map control) 2 0x000c?x000d pim (port integration module) 2 0x000e?x000f ebi (external bus interface) 2 0x0010?x0017 mmc (memory map control) 8 0x0018?x0019 unimplemented 2 0x001a?x001b device id register 2 0x001c?x001f pim (port integration module) 4 0x0020?x002f dbg (debug module) 16 0x0030?x0031 mmc (memory map control) 2 0x0032?x0033 pim (port integration module) 2 0x0034?x003f crg (clock and reset generator) 12 0x0040?x007f ect (enhanced capture timer 16-bit 8-channel) 64 0x0080?x00af atd (analog-to-digital converter 10-bit 16-channel) 48 0x00b0?x00bf int (interrupt module) 16 0x00c0?x00c7 iic0 (inter ic bus) 8 0x00c8?x00cf sci0 (serial communications interface) 8 0x00d0?x00d7 sci1 (serial communications interface) 8 0x00d8?x00df spi (serial peripheral interface) 8 0x00e0?x00ff unimplemented 32 0x0100?x010f flash control registers 16 0x0110?x011b eeprom control registers 12 0x011c?x011f mmc (memory map control) 4 0x0120?x0137 liquid crystal display driver 32x4 (lcd) 24 0x0138?x013f iic1 (inter ic bus) 8 0x0140?x017f can0 (scalable can) 64 0x0180?x01bf can1 (scalable can) 64 0x01c0?x01ff mc (motor controller) 64 0x0200?x027f pim (port integration module) 128 0x0280?x0287 ssd4 (stepper stall detector) 8 0x0288?x028f ssd0 (stepper stall detector) 8 0x0290?x0297 ssd1 (stepper stall detector) 8 0x0298?x029f ssd2 (stepper stall detector) 8 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 31 figure 1-2 shows the cpu & bdm local address translation to the global memory map. it indicates also the location of the internal resources in the memory map. table 1-2. device internal resources figure 1-3 shows xgate local address translation to the global memory map. it indicates also the location of used internal resources in the memory map. 0x02a0?x02a7 ssd3 (stepper stall detector) 8 0x02a8?x02af ssd5 (stepper stall detector) 8 0x02b0?x02ef unimplemented 64 0x02f0?x02f7 voltage regulator 8 0x02f8?x02ff unimplemented 8 0x0300?x0327 pwm (pulse-width modulator 8 channels) 40 0x0328?x033f unimplemented 24 0x0340?x0367 pit (periodic interrupt timer) 40 0x0368?x037f unimplemented 24 0x0380?x03bf xgate 64 0x03c0?x03ff unimplemented 64 0x0400?x07ff unimplemented 1024 internal resource size /kbyte $address system ram ramsize=32k ram_low = 0x0f_8000 eeprom eepromsize=4k eeprom_low = 0x13_f000 flash flashsize=512k flash_low = 0x78_0000 table 1-3. xgate resources internal resource size /kbyte $address xgate ram xgramsize=32k xgram_low = 0x0f_8000 flash xgflashsize=30k 1 1 this value is calculated by the following formula: (64k -2k- xgramsize) xgflash_high = 0x78_8000 table 1-1. device register memory map address offset module size (bytes) 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 32 freescale semiconductor figure 1-2. MC9S12XHZ512 global memory map 0x7f_ffff 0x00_0000 0x13_ffff 0x0f_ffff eeprom ram 0x00_07ff epage rpage ppage 0x3f_ffff cpu and bdm local memory map global memory map flashsize ramsize cs3 cs1 cs0 0x1f_ffff cs2 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x0c00 0x2000 0x0800 8k ram 4k ram window 1k eeprom 2k registers 1k eeprom window 16k flash unpaged 16k flash 2k registers unimplemented ram external space ram_low flash flash_low unimplemented flash eeprom_low unimplemented eeprom cs2 eepromsize 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 33 figure 1-3. xgate global address mapping 0x7f_ffff 0x00_0000 0x0f_ffff 0xffff 0x0000 registers flash ram 0x0800 registers 0x00_07ff xgate local memory map global memory map flashsize xgramsize ramsize 0x78_0800 flash ram xgram_low xgflash_high 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 34 freescale semiconductor 1.1.5 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses 0x001a and 0x001b). the read-only value is a unique part id for each revision of the chip. table 1-4 shows the assigned part id number and mask set number. 1.2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 1.2.1 device pinout the MC9S12XHZ512 is offered in the following package options: 144-pin lqfp with an external bus interface (address/data bus) 112-pin lqfp without an external bus interface figure 1-4 and figure 1-5 show the pin assignments. table 1-4. assigned part id numbers device mask set number part id 1 1 the coding is as follows: bit 15-12: major family identi?r bit 11-8: minor family identi?r bit 7-4: major mask set revision including fab transfers bit 3-0: minor non-full mask set revision MC9S12XHZ512 0m80f 0xe400 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 35 figure 1-4. MC9S12XHZ512 pin assignment for 144-pin lqfp fp28/an12/pl4 fp29an13//pl5 fp30/an14//pl6 fp31/an15/pl7 m4c0m/m4cosm/pw0 m4c0p/m4cosp/pw1 m4c1m/m4sinm/pw2 m4c1p/m4sinp/pw3 vddm1 vssm1 m0c0m/m0cosm/pu0 m0c0p/m0cosp/pu1 m0c1m/m0sinm/pu2 m0c1p/m0sinp/pu3 m1c0m/m1cosm/pu4 m1c0p/m1cosp/pu5 m1c1m/m1sinm/pu6 m1c1p/m1sinp/pu7 vddm2 vssm2 m2c0m/m2cosm/pv0 m2c0p/m2cosp/pv1 m2c1m/m2sinm/pv2 m2c1p/m2sinp/pv3 m3c0m/m3cosm/pv4 m3c0p/m3cosp/pv5 m3c1m/m3sinm/pv6 m3c1p/m3sinp/pv7 vddm3 vssm3 m5c0m/m5cosm/pw4 m5c0p/m5cosp/pw5 m5c1m/m5sinm/pw6 m5c1p/m5sinp/pw7 scl0/pwm5/pp5 sda0/pwm4/pp4 pwm3/pp3 rxd1/pwm2/pp2 txd1/pwm0/pp0 pwm1/pp1 cs0/sda1/pwm6/pp6 cs2/scl1/pwm7/pp7 acc0/addr20/pk4 acc1/addr21/pk5 rxd0/ps0 txd0/ps1 cs3/rxd1/ps2 txd1/ps3 vss2 vddr vddx2 vssx2 modc/bkgd reset vddpll xfc vsspll extal xtal test acc2/addr22/pk6 cs1/pm1 rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 taglo/ re/moda /pe5 miso/ps4 mosi/ps5 sck/ps6 ss/ps7 irq/pe1 pb5/ addr5 /fp5 pb4/ addr4 /fp4 pb3/ addr3 /fp3 pb2/ addr2 /fp2 pb1/ addr1 /fp1 pb0/ addr0 /fp0 pk0/ addr16 /bp0 pk1/ addr17 /bp1 pk2/ addr18 /bp2 pk3/ addr19 /bp3 vlcd vss1 vdd1 pd7/data7 pd6/data6 pd5/data5 pd4/data4 pd3/data3 pd2/data2 pd1/data1 pd0/data0 pad7/kwad7/an7 pad6/kwad6/an6 pad5/kwad5/an5 pad4/kwad4/an4 pad3/kwad3/an3 pad2/kwad2/an2 pad1/kwad1/an1 pad0/kwad0/an0 vdda vrh vrl vssa pe0/ xirq pe4/eclk pe6/ modb / taghi pt7/ioc7/scl1 pt6/ioc6/sda1 pt5/ioc5/scl0 pt4/ioc4/sda0 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 pc7/dat15 pc6/dat14 pc5/dat13 pc4/dat12 vssx1 vddx1 pk7/ ewait/romctl /fp23 pe7/ eclkx2 /xclks/fp22 pe3/ lstrb / lds / eromctl /fp21 pe2/ r w/ we /fp20 pc3/dat11 pc2/dat10 pc1/dat9 pc0/dat8 pl3/an11/fp19 pl2/an10/fp18 pl1/an9/fp17 pl0/an8/fp16 pa7/ addr15 /fp15 pa6/ addr14 /fp14 pa5/ addr13 /fp13 pa4/ addr12 /fp12 pa3/ addr11 /fp11 pa2/ addr10 /fp10 pa1/ addr9 /fp9 pa0/ addr8 /fp8 pb7/ addr7 /fp7 pb6/ addr6 /fp6 MC9S12XHZ512 144 lqfp pins shown in bold are not available in the 112 qfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 36 freescale semiconductor figure 1-5. MC9S12XHZ512 pin assignment for 112-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 MC9S12XHZ512 112 lqfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 fp28/an12/pl4 fp29an13//pl5 fp30/an14//pl6 fp31/an15/pl7 vddm1 vssm1 m0c0m/m0cosm/pu0 m0c0p/m0cosp/pu1 m0c1m/m0sinm/pu2 m0c1p/m0sinp/pu3 m1c0m/m1cosm/pu4 m1c0p/m1cosp/pu5 m1c1m/m1sinm/pu6 m1c1p/m1sinp/pu7 vddm2 vssm2 m2c0m/m2cosm/pv0 m2c0p/m2cosp/pv1 m2c1m/m2sinm/pv2 m2c1p/m2sinp/pv3 m3c0m/m3cosm/pv4 m3c0p/m3cosp/pv5 m3c1m/m3sinm/pv6 m3c1p/m3sinp/pv7 vddm3 vssm3 scl0/pwm5/pp5 sda0/pwm4/pp4 pt7/ioc7/scl1 pt6/ioc6/sda1 pt5/ioc5/scl0 pt4/ioc4/sda0 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/fp23 pe7/xclks/fp22 pe3/fp21 pe2/fp20 pl3/an11/fp19 pl2/an10/fp18 pl1/an9/fp17 pl0/an8/fp16 pa7/fp15 pa6/fp14 pa5/fp13 pa4/fp12 pa3/fp11 pa2/fp10 pa1/fp9 pa0/fp8 pb7/fp7 pb6/fp6 pb5/fp5 pb4/fp4 pb3/fp3 pb2/fp2 pb1/fp1 pb0/fp0 pk0/bp0 pk1/bp1 pk2/bp2 pk3/bp3 vlcd vss1 vdd1 pad7/kwad7/an7 pad6/kwad6/an6 pad5/kwad5/an5 pad4/kwad4/an4 pad3/kwad3/an3 pad2/kwad2/an2 pad1/kwad1/an1 pad0/kwad0/an0 vdda vrh vrl vssa pe0/ xirq pe4/eclk pe6 pwm3/pp3 rxd1/pwm2/pp2 txd1/pwm0/pp0 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddr vddx2 vssx2 modc/bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 pe5 miso/ps4 mosi/ps5 sck/ps6 ss/ps7 irq/pe1 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 37 1.2.2 signal properties summary table 1-5 summarizes all pin functions. table 1-5. signal properties pin name function 1 pin name function 2 pin name function 3 pin name function 4 pin name function 5 powered by internal pull up resistor description ctrl reset state extal v ddpll na na oscillator pins xtal v ddpll na na reset v ddx2 pull up external reset test na na na test input - must be tied to vss in all applications xfc v ddpll na na pll loop filter bkgd modc v ddx2 always on up background debug, mode input pad[7:0] an[7:0] kwad[7:0] v dda perad/ ppsad disabled port ad i/o, analog inputs (atd), interrupts pa[7:0] fp[15:8] addr[15:8] ivd[15:8] v ddx1 pucr down port a i/o, address bus, internal visibility data pb[7:1] fp[7:1] addr[7:1] ivd[7:1] v ddx1 pucr down port b i/o, address bus, internal visibility data pb0 fp0 addr0 ivd0 uds v ddx1 pucr down port b i/o, address bus, internal visibility data, upper data strobe pc[7:0] data[15:8] v ddx1 pucr disabled port c i/o, data bus pd[7:0] data[7:0] v ddx1 pucr disabled port d i/o, data bus pe7 fp22 eclkx2 xclks v ddx1 pucr down port e i/o, lcd driver, system clock output, clock select pe6 t a ghi modb v ddx2 while reset pin is low: down port e i/o, tag high, mode input pe5 t a glo moda re v ddx2 while reset pin is low: down port e i/o, tag low, mode input, read enable pe4 eclk v ddx2 pucr down port e i/o, bus clock output pe3 fp21 lstrb lds eromctl v ddx1 pucr down port e i/o, lcd driver, low byte strobe, eromon control pe2 fp20 r/ w we v ddx1 pucr down port e i/o, read/write, write enable pe1 irq v ddx2 pucr up port e input, maskable interrupt pe0 xirq v ddx2 pucr up port e input, non-maskable interrupt 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 38 freescale semiconductor pk7 fp23 ecs romctl romctl v ddx1 pucr down port k i/o, emulation chip select, rom on enable pk[6:4] addr[22:20] acc[2:0] v ddx2 port k i/o, extended address, access source pk[3:0] bp[3:0] addr[19:16] iqstat[3:0] v ddx1 port k i/o, lcd driver, extended address, pipe status pl[7:4] fp[31:28] an[15:12] v dda perl/ ppsl down port l i/o, lcd drivers, analog inputs (atd) pl[3:0] fp[19:16] an[11:8] v ddx1 port l i/o, lcd drivers, analog inputs (atd) pm5 txcan1 v ddx2 perm/ ppsm disabled port m i/o, tx of can1 pm4 rxcan1 v ddx2 port m i/o, rx of can1 pm3 txcan0 v ddx2 port m i/o, tx of can0 pm2 rxcan0 v ddx2 port m i/o, rx of can0 pm1 cs1 v ddx2 port m i/o, chip select 1 pp7 pwm7 scl1 cs2 v ddx2 perp/ ppsp disabled port p i/o, pwm channel, scl of iic1, chip select 2 pp6 pwm6 sda1 cs0 v ddx2 port p i/o, pwm channel, sda of iic1, chip select 0 pp5 pwm5 scl0 v ddx2 port p i/o, pwm channel, scl of iic0 pp4 pwm4 sda0 v ddx2 port p i/o, pwm channel, sda of iic0 pp3 pwm3 v ddx2 port p i/o, pwm channel pp2 pwm2 rxd1 v ddx2 port p i/o, pwm channel, rxd of sci1 pp1 pwm1 v ddx2 port p i/o, pwm channel pp0 pwm0 txd1 v ddx2 port p i/o, pwm channel, txd of sci1 ps7 ss v ddx2 pers/ ppss disabled port s i/o, ss of spi ps6 sck v ddx2 port s i/o, sck of spi ps5 mosi v ddx2 port s i/o, mosi of spi ps4 miso v ddx2 port s i/o, miso of spi ps3 txd1 v ddx2 port s i/o, txd of sci1 ps2 rxd1 cs3 v ddx2 port s i/o, rxd of sci1, chip select 3 ps1 txd0 v ddx2 port s i/o, txd of sci0 ps0 rxd0 v ddx2 port s i/o, rxd of sci0 table 1-5. signal properties (continued) pin name function 1 pin name function 2 pin name function 3 pin name function 4 pin name function 5 powered by internal pull up resistor description ctrl reset state 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 39 pt7 ioc7 scl1 v ddx1 pert/ ppst disabled port t i/o, timer channels, scl of iic1 pt6 ioc6 sda1 v ddx1 port t i/o, timer channels, sda of iic1 pt5 ioc5 scl0 v ddx1 port t i/o, timer channels, scl of iic0 pt4 ioc4 sda0 v ddx1 port t i/o, timer channels, sda of iic0 pt[3:0] ioc[3:0] fp[27:24] v ddx1 pert/ ppst down port t i/o, timer channels, lcd driver pu7 m1c1p m1sinp v ddm1,2,3 peru/ ppsu disabled port u i/o, motor1 coil nodes of mc or ssd1 pu6 m1c1m m1sinm v ddm1,2,3 pu5 m1c0p m1cosp v ddm1,2,3 pu4 m1c0m m1cosm v ddm1,2,3 pu3 m0c1p m0sinp v ddm1,2,3 port u i/o, motor 0 coil nodes of mc or ssd0 pu2 m0c1m m0sinm v ddm1,2,3 pu1 m0c0p m0cosp v ddm1,2,3 pu0 m0c0m m0cosm v ddm1,2,3 pv7 m3c1p m3sinp v ddm1,2,3 perv/ ppsv disabled port v i/o, motor 3 coil nodes of mc or ssd3 pv6 m3c1m m3sinm v ddm1,2,3 pv5 m3c0p m3cosp v ddm1,2,3 pv4 m3c0m m3cosm v ddm1,2,3 pv3 m2c1p m2sinp v ddm1,2,3 port v i/o, motor 2 coil nodes of mc or ssd2 pv2 m2c1m m2sinm v ddm1,2,3 pv1 m2c0p m2cosp v ddm1,2,3 pv0 m2c0m m2cosm v ddm1,2,3 pw7 m5c1p m5sinp v ddm1,2,3 perw/ ppsw disabled port w i/o, motor 5 coil nodes of mc or ssd5 pw6 m5c1m m5sinm v ddm1,2,3 pw5 m5c0p m5cosp v ddm1,2,3 pw4 m5c0m m5cosm v ddm1,2,3 pw3 m4c1p m4sinp v ddm1,2,3 port w i/o, motor 4 coil nodes of mc or ssd4 pw2 m4c1m m4sinm v ddm1,2,3 pw1 m4c0p m4cosp v ddm1,2,3 pw0 m4c0m m4cosm v ddm1,2,3 table 1-5. signal properties (continued) pin name function 1 pin name function 2 pin name function 3 pin name function 4 pin name function 5 powered by internal pull up resistor description ctrl reset state 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 40 freescale semiconductor note all v ss pins must be connected together in the application. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on mcu pin load. 1.2.3 detailed signal descriptions 1.2.3.1 extal, xtal ?oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 1.2.3.2 reset ?external reset pin the reset pin is an active low bidirectional control signal. it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset.the reset pin has an internal pullup device. table 1-6. power and ground mnemonic nominal voltage description v lcd 5.0 v voltage reference pin for the lcd driver. v dd1 2.5 v internal power and ground generated by internal regulator. these also allow an external source to supply the core v dd /v ss voltages and bypass the internal voltage regulator. v ss1 v ss2 0v v ddr 5.0 v external power and ground, supply to pin drivers and internal voltage regulator. v ssr 0 v v ddx1 v ddx2 5.0 v external power and ground, supply to pin drivers. v ssx1 v ssx2 0 v v dda 5.0 v operating voltage and ground for the analog-to-digital converter and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. v ssa 0 v v rh 5.0 v reference voltage high for the atd converter. v rl 0 v reference voltage low for the atd converter. v ddpll 2.5 v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. v sspll 0 v v ddm1,2,3 5.0 v provides operating voltage and ground for motor 0, 1, 2 and 3. v ssm1,2,3 0 v 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 41 1.2.3.3 test ?test pin this input only pin is reserved for test. this pin has a pulldown device. note the test pin must be tied to v ss in all applications. 1.2.3.4 xfc ?pll loop filter pin please ask your freescale representative for the interactive application note to compute pll loop ?ter elements. any current leakage on this pin must be avoided. figure 1-6. pll loop filter connections 1.2.3.5 bkgd / modc ?background debug and mode pin the bkgd/modc pin is used as a pseudo-open-drain pin for the background debug communication. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. the bkgd pin has a pullup device. 1.2.3.6 pad[7:0] / an[7:0] / kwad[7:0] ?port ad i/o pins [7:0] pad7?ad0 are general-purpose input or output pins and analog inputs for the analog-to-digital converter. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 1.2.3.7 pa[7:0] / addr[15:8] / ivd[15:8] ?port a i/o pins pa[7:0] are general-purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external address bus. in mcu emulation modes of operation, these pins are used for external address bus and internal visibility read data. 1.2.3.8 pb[7:1] / addr[7:1] / ivd[7:1] ?port b i/o pins pb[7:1] are general-purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external address bus. in mcu emulation modes of operation, these pins are used for external address bus and internal visibility read data. mcu xfc r 0 c s c p v ddpll v ddpll 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 42 freescale semiconductor 1.2.3.9 pb0 / addr0 / uds / ivd[0] ?port b i/o pin 0 pb0 is a general-purpose input or output pin. in mcu expanded modes of operation, this pin is used for the external address bus addr0 or as upper data strobe signal. in mcu emulation modes of operation, this pin is used for external address bus addr0 and internal visibility read data ivd0. 1.2.3.10 pc[7:0] / data [15:8] ?port c i/o pins pc[7:0] are general-purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external data bus. the input voltage thresholds for pc[7:0] can be con?ured to reduced levels, to allow data from an external 3.3-v peripheral to be read by the mcu operating at 5.0 v. the input voltage thresholds for pc[7:0] are con?ured to reduced levels out of reset in expanded and emulation modes. the input voltage thresholds for pc[7:0] are con?ured to 5-v levels out of reset in normal modes. 1.2.3.11 pd[7:0] / data [7:0] ?port d i/o pins pd[7:0] are general-purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external data bus. the input voltage thresholds for pd[7:0] can be con?ured to reduced levels, to allow data from an external 3.3-v peripheral to be read by the mcu operating at 5.0 v. the input voltage thresholds for pd[7:0] are con?ured to reduced levels out of reset in expanded and emulation modes. the input voltage thresholds for pc[7:0] are con?ured to 5-v levels out of reset in normal modes. 1.2.3.12 pe7 / fp22 / eclkx2 / xclks ?port e i/o pin 7 pe7 is a general-purpose input or output pin. the pin can be con?ured as frontplane segment driver output fp22 of the lcd module or as the internal system clock eclkx2. the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used. the xclks signal selects the oscillator con?uration during reset low phase while a clock quality check is ongoing. this is the case for: power on reset or low-voltage reset clock monitor reset any reset while in self-clock mode or full stop mode the selected oscillator con?uration is frozen with the rising edge of reset. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 43 figure 1-7. loop controlled pierce oscillator connections (pe7 = 0) figure 1-8. full swing pierce oscillator connections (pe7 = 1) figure 1-9. external clock connections (pe7 = 1) 1.2.3.13 pe6 / modb / t a ghi ?port e i/o pin 6 pe6 is a general-purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is an input with a pull-down device which is only active when reset is low. t a ghi is used to tag the high half of the instruction word being read into the instruction queue. the input voltage threshold for pe6 can be con?ured to reduced levels, to allow data from an external 3.3-v peripheral to be read by the mcu operating at 5.0 v. the input voltage threshold for pe6 is con?ured to reduced levels out of reset in expanded and emulation modes. mcu extal xtal v sspll crystal or ceramic resonator c 2 c 1 mcu extal xtal r s r b v sspll crystal or ceramic resonator c 2 c 1 mcu extal xtal cmos-compatible external oscillator not connected 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 44 freescale semiconductor 1.2.3.14 pe5 / moda / t a glo / re ?port e i/o pin 5 pe5 is a general-purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the read enable re output. this pin is an input with a pull-down device which is only active when reset is low. t a glo is used to tag the low half of the instruction word being read into the instruction queue. the input voltage threshold for pe5 can be con?ured to reduced levels, to allow data from an external 3.3-v peripheral to be read by the mcu operating at 5.0 v. the input voltage threshold for pe5 is con?ured to reduced levels out of reset in expanded and emulation modes. 1.2.3.15 pe4 / eclk ?port e i/o pin 4 pe4 is a general-purpose input or output pin. it can be con?ured to drive the internal bus clock eclk. eclk can be used as a timing reference. 1.2.3.16 pe3 / fp21 / lstrb / lds / eromctl?port e i/o pin 3 pe3 is a general-purpose input or output pin. it can be configured as frontplane segment driver output fp21 of the lcd module. in mcu expanded modes of operation, lstrb or lds can be used for the low byte strobe function to indicate the type of bus access. at the rising edge of reset the state of this pin is latched to the eromon bit. 1.2.3.17 pe2 / fp20 / r/ w / we port e i/o pin 2 pe2 is a general-purpose input or output pin. it can be configured as frontplane segment driver output fp20 of the lcd module. in mcu expanded modes of operations, this pin drives the read/write output signal or write enable output signal for the external bus. it indicates the direction of data on the external bus. 1.2.3.18 pe1 / irq ?port e input pin 1 pe1 is a general-purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 1.2.3.19 pe0 / xirq ?port e input pin 0 pe0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 1.2.3.20 pk7 / fp23 / ew ait / romctl ?port k i/o pin 7 pk7 is a general-purpose input or output pin. it can be configured as frontplane segment driver output fp23 of the lcd module. during mcu emulation modes and normal expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map (romctl). at the rising edge of reset, the state of this pin is latched to the romon bit. the ew ait input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read). 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 45 the input voltage threshold for pk7 can be con?ured to reduced levels, to allow data from an external 3.3-v peripheral to be read by the mcu operating at 5.0 v. the input voltage threshold for pk7 is con?ured to reduced levels out of reset in expanded and emulation modes. 1.2.3.21 pk[6:4] / addr[22:20] / acc[2:0] ?port k i/o pin [6:4] pk[6:4] are general-purpose input or output pins. during mcu expanded modes of operation, the acc[2:0] signals are used to indicate the access source of the bus cycle. this pins also provide the expanded addresses addr[22:20] for the external bus. in emulation modes acc[2:0] is available and is time multiplexed with the high addresses 1.2.3.22 pk[3:0] / bp[3:0] / addr[19:16] / iqstat[3:0] ?port k i/o pins [3:0] pk3-pk0 are general-purpose input or output pins. the pins can be configured as backplane segment driver outputs bp3?p0 of the lcd module. in mcu expanded modes of operation, these pins provide the expanded address addr[19:16] for the external bus and carry instruction pipe information. 1.2.3.23 pl[7:4] / fp[31:28] / an[15:12] ?port l i/o pins [7:4] pl7?l4 are general-purpose input or output pins. they can be configured as frontplane segment driver outputs fp31?p28 of the lcd module or analog inputs for the analog-to-digital converter. 1.2.3.24 pl[3:0] / fp[19:16] / an[11:8] ?port l i/o pins [3:0] pl3?l0 are general-purpose input or output pins. they can be configured as frontplane segment driver outputs fp19?p16 of the lcd module or analog inputs for the analog-to-digital converter. 1.2.3.25 pm5 / txcan1 ?port m i/o pin 5 pm5 is a general-purpose input or output pin. it can be configured as the transmit pin txcan1 of the scalable controller area network controller 1 (can1) 1.2.3.26 pm4 / rxcan1 ?port m i/o pin 4 pm4 is a general-purpose input or output pin. it can be configured as the receive pin rxcan1 of the scalable controller area network controller 1 (can1) 1.2.3.27 pm3 / txcan0 ?port m i/o pin 3 pm3 is a general-purpose input or output pin. it can be configured as the transmit pin txcan0 of the scalable controller area network controller 0 (can0) 1.2.3.28 pm2 / rxcan0 ?port m i/o pin 2 pm2 is a general-purpose input or output pin. it can be configured as the receive pin rxcan0 of the scalable controller area network controller 0 (can0). 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 46 freescale semiconductor 1.2.3.29 pm1 / cs1 ?port m i/o pin 1 pm1 is a general-purpose input or output pin. it can be configured to provide a chip-select output. 1.2.3.30 pp7 / pwm7 / scl1 / cs2 port p i/o pin 7 pp7 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm7 or the serial clock pin scl1 of the inter-ic bus interface 1 (iic1). it can be con?ured to provide a chip-select output. 1.2.3.31 pp6 / pwm6 / sda1 / cs0 port p i/o pin 6 pp6 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm6 or the serial data pin sda1 of the inter-ic bus interface 1 (iic1). it can be con?ured to provide a chip-select output. 1.2.3.32 pp5 / pwm5 / scl0 port p i/o pin 5 pp5 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm5 or the serial clock pin scl0 of the inter-ic bus interface 0 (iic0). 1.2.3.33 pp4 / pwm4 / sda0 port p i/o pin 4 pp4 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm4 or the serial data pin sda0 of the inter-ic bus interface 0 (iic0). 1.2.3.34 pp3 / pwm3 port p i/o pin 3 pp3 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm3. 1.2.3.35 pp2 / pwm2 / rxd1 port p i/o pin 2 pp2 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm2 or the receive pin rxd1 of the serial communication interface 1 (sci1). 1.2.3.36 pp1 / pwm1 port p i/o pin 1 pp1 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm1. 1.2.3.37 pp0 / pwm0 / txd1 port p i/o pin 0 pp0 is a general-purpose input or output pin. it can be configured as pulse width modulator (pwm) channel output pwm0 or the transmit pin txd1 of the serial communication interface 1 (sci1). 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 47 1.2.3.38 ps7 / ss ?port s i/o pin 7 ps7 is a general-purpose input or output pin. it can be configured as slave select pin ss of the serial peripheral interface (spi). 1.2.3.39 ps6 / sck ?port s i/o pin 6 ps6 is a general-purpose input or output pin. it can be configured as serial clock pin sck of the serial peripheral interface (spi). 1.2.3.40 ps5 / mosi ?port s i/o pin 5 ps5 is a general-purpose input or output pin. it can be configured as the master output (during master mode) or slave input (during slave mode) pin mosi of the serial peripheral interface (spi). 1.2.3.41 ps4 / miso ?port s i/o pin 4 ps4 is a general-purpose input or output pin. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso for the serial peripheral interface (spi). 1.2.3.42 ps3 / txd1 ?port s i/o pin 3 ps3 is a general-purpose input or output pin. it can be configured as transmit pin txd1 of the serial communication interface 1 (sci1). 1.2.3.43 ps2 / rxd1 / cs2 ?port s i/o pin 2 ps2 is a general-purpose input or output pin. it can be configured as receive pin rxd1 of the serial communication interface 1 (sci1). it can be configured to provide a chip-select output. 1.2.3.44 ps1 / txd0 ?port s i/o pin 1 ps1 is a general-purpose input or output pin. it can be configured as transmit pin txd0 of the serial communication interface 0 (sci0). 1.2.3.45 ps0 / rxd0 ?port s i/o pin 0 ps0 is a general-purpose input or output pin. it can be configured as receive pin rxd0 of the serial communication interface 0 (sci0). 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 48 freescale semiconductor 1.2.3.46 pt7 / ioc7 / scl1 ?port t i/o pin 7 pt7 is a general-purpose input or output pin. it can be configured as input capture or output compare pin ioc7 of the enhanced capture timer (ect) or the serial clock pin scl1 of the inter-ic bus interface 1 (iic1). 1.2.3.47 pt6 / ioc6 / sda1 ?port t i/o pin 6 pt6 is a general-purpose input or output pin. it can be configured as input capture or output compare pin ioc6 of the enhanced capture timer (ect) or the serial data pin sda1 of the inter-ic bus interface 1 (iic1). 1.2.3.48 pt5 / ioc5 / scl0 ?port t i/o pin 5 pt5 is a general-purpose input or output pin. it can be configured as input capture or output compare pin ioc5 of the enhanced capture timer (ect) or the serial clock pin scl0 of the inter-ic bus interface 0 (iic0). 1.2.3.49 pt4 / ioc4 / sda0 ?port t i/o pin 4 pt4 is a general-purpose input or output pin. it can be configured as input capture or output compare pin ioc4 of the enhanced capture timer (ect) or the serial data pin sda0 of the inter-ic bus interface 0 (iic0). 1.2.3.50 pt[3:0] / ioc[3:0] / fp[27:24] ?port t i/o pins [3:0] pt3?t0 are general-purpose input or output pins. they can be configured as input capture or output compare pins ioc3?oc0 of the enhanced capture timer (ect). they can be configured as frontplane segment driver outputs fp27?p24 of the lcd module. 1.2.3.51 pu[7:4] / m1c1(sin)p, m1c1(sin)m, m1c0(cos)p, m1c0(cos)m port u i/o pins [7:4] pu7?u4 are general-purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. these pins interface to the coils of motor 1. 1.2.3.52 pu[3:0] / m0c1(sin)p, m0c1(sin)m, m0c0(cos)p, m0c0(cos)m port u i/o pins [3:0] pu3?u0 are general-purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. these pins interface to the coils of motor 0. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 49 1.2.3.53 pv[7:4] / m3c1(sin)p, m3c1(sin)m, m3c0(cos)p, m3c0(cos)m port v i/o pins [7:4] pv7?v4 are general-purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. these pins interface to the coils of motor 3. 1.2.3.54 pv[3:0] / m2c1(sin)p, m2c1(sin)m, m2c0(cos)p, m2c0(cos)m port v i/o pins [3:0] pv3?v0 are general-purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. these pins interface to the coils of motor 2. 1.2.3.55 pw[7:4] / m5c1(sin)p, m5c1(sin)m, m5c0(cos)p, m5c0(cos)m port w i/o pins [7:4] pw7?w4 are general-purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. these pins interface to the coils of motor 5. 1.2.3.56 pw[3:0] / m4c1(sin)p, m4c1(sin)m, m4c0(cos)p, m4c0(cos)m port w i/o pins [3:0] pw3?w0 are general-purpose input or output pins. they can be configured as high current pwm output pins which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. these pins interface to the coils of motor 4. 1.2.4 power supply pins MC9S12XHZ512 power and ground pins are described below. note all v ss pins must be connected together in the application. 1.2.4.1 v ddr ?external power pin v ddr is the power supply pin for the internal voltage regulator. 1.2.4.2 v ddx1 , v ddx2 , v ssx1 , v ssx2 ?external power and ground pins external power and ground for i/o drivers. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. v ddx1 and v ddx2 as well as v ssx1 and v ssx2 are not internally connected. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 50 freescale semiconductor 1.2.4.3 v dd1 , v ss1 , v ss2 ?internal logic power pins power is supplied to the mcu through v dd and v ss . because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. this 2.5-v supply is derived from the internal voltage regulator. there is no static load on those pins allowed. v ss1 and v ss2 are internally connected. 1.2.4.4 v dda , v ssa ?power supply pins for atd and vreg v dda , v ssa are the power supply and ground pins for the voltage regulator and the analog-to-digital converter. 1.2.4.5 v rh , v rl ?atd reference voltage input pins v rh and v rl are the voltage reference pins for the analog-to-digital converter. 1.2.4.6 v ddpll , v sspll ?power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator and pll to be bypassed independently. this 2.5-v voltage is generated by the internal voltage regulator. 1.2.4.7 v ddm1 , v ddm2 , v ddm3 ?power supply pins for motor 0 to 3 v ddm1 , v ddm2 and v ddm3 are the supply pins for the ports u, v and w. v ddm1 , v ddm2 and v ddm3 are internally connected. 1.2.4.8 v ssm1 , v ssm2 , v ssm3 ?ground pins for motor 0 to 3 v ssm1 , v ssm2 and v ssm3 are the ground pins for the ports u, v and w. v ssm1 , v ssm2 and v ssm3 are internally connected. 1.2.4.9 v lcd ?power supply reference pin for lcd driver v lcd is the voltage reference pin for the lcd driver. adjusting the voltage on this pin will change the display contrast. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 51 1.3 system clock description the clock and reset generator module (crg) provides the internal clock signals for the core and all peripheral modules. figure 1-10 shows the clock connections from the crg to all modules. consult the crg block description chapter for details on clock generation. figure 1-10. clock connections the mcus system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: the on-chip phase locked loop (pll) the pll self clocking the oscillator the clock generated by the pll or oscillator provides the main system clock frequencies core clock and bus clock. as shown in figure 1-10 , this system clocks are used throughout the mcu to drive the core, the memories, and the peripherals. ssd0 . . ssd5 iic0 & iic1 sci0 & sci1 crg bus clock extal xtal core clock oscillator clock ram s12x xgate eeprom flash pit ect pim can0 & can1 spi lcd mc 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 52 freescale semiconductor the program flash memory and the eeprom are supplied by the bus clock and the oscillator clock.the oscillator clock is used as a time base to derive the program and erase times for the nvms. consult the ftx512k4 and eetx4k block description chapters for more details on the operation of the nvms. the can modules may be con?ured to have their clock sources derived either from the bus clock or directly from the oscillator clock. this allows the user to select its clock based on the required jitter performance. consult mscan block description for more details on the operation and con?uration of the can blocks. in order to ensure the presence of the clock the mcu includes an on-chip clock monitor connected to the output of the oscillator. the clock monitor can be con?ured to invoke the pll self-clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. in addition to the clock monitor, the mcu also provides a clock quality checker which performs a more accurate check of the clock. the clock quality checker counts a predetermined number of clock edges within a de?ed time window to insure that the clock is running. the checker can be invoked following speci? events such as on wake-up or clock monitor failure. 1.4 chip con?uration summary the mcu can operate in six different modes. the different modes, the state of romctl and eromctl signal on rising edge of reset, and the security state of the mcu affects the following device characteristics: external bus interface con?uration flash in memory map, or not debug features enabled or disabled the operating mode out of reset is determined by the states of the modc, modb, and moda signals during reset (see table 1-7 ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda signals are latched into these bits on the rising edge of reset. in normal expanded mode and in emulation modes the romon bit and the eromon bit in the mmcctl1 register de?es if the on chip ?sh memory is the memory map, or not. (see table 1-7 .) for a detailed description of the romon and eromon bits refer to the s12x_mmc bblock description chapter. the state of the romctl signal is latched into the romon bit in the mmcctl1 register on the rising edge of reset. the state of the eromctl signal is latched into the eromon bit in the misc register on the rising edge of reset. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 53 the con?uration of the oscillator can be selected using the xclks signal (see table 1-8 ). for a detailed description please refer to the crg block description chapter. 1.5 modes of operation 1.5.1 user modes 1.5.1.1 normal expanded mode ports k, a, and b are con?ured as a 23-bit address bus, ports c and d are con?ured as a 16-bit data bus, and port e provides bus control and status signals. this mode allows 16-bit external memory and peripheral devices to be interfaced to the system. the fastest external bus rate is divide by 2 from the internal bus rate. 1.5.1.2 normal single-chip mode there is no external bus in this mode. the processor program is executed from internal memory. ports a, b,c,d, k, and most pins of port e are available as general-purpose i/o. table 1-7. chip modes and data sources chip modes bkgd = modc pe6 = modb pe5 = moda pk7 = romctl pe3 = eromctl data source 1 1 internal means resources inside the mcu are read/written. internal flash means flash resources inside the mcu are read/written. emulation memory means resources inside the emulator are read/written (pru registers, flash replacement, ram, eeprom, and register space are always considered internal). external application means resources residing outside the mcu are read/written. normal single chip 1 0 0 x x internal special single chip 0 0 0 emulation single chip 0 0 1 x 0 emulation memory x 1 internal flash normal expanded 1 0 1 0 x external application 1 x internal flash emulation expanded 0 1 1 0 x external application 1 0 emulation memory 1 1 internal flash special test 0 1 0 0 x external application 1 x internal flash table 1-8. clock selection based on pe7 pe7 = xclks description 0 loop controlled pierce oscillator selected 1 full swing pierce oscillator or external clock source selected 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 54 freescale semiconductor 1.5.1.3 special single-chip mode this mode is used for debugging single-chip operation, boot-strapping, or security related operations. the background debug module bdm is active in this mode. the cpu executes a monitor program located in an on-chip rom. bdm ?mware is waiting for additional serial commands through the bkgd pin. there is no external bus after reset in this mode. 1.5.1.4 emulation of expanded mode developers use this mode for emulation systems in which the users target application is normal expanded mode. code is executed from external memory or from internal memory depending on the state of romon and eromon bit. in this mode the internal operation is visible on external bus interface. 1.5.1.5 emulation of single-chip mode developers use this mode for emulation systems in which the users target application is normal single-chip mode. code is executed from external memory or from internal memory depending on the state of romon and eromon bit. in this mode the internal operation is visible on external bus interface. 1.5.1.6 special test mode freescale internal use only. 1.5.2 low-power modes the microcontroller features two main low-power modes. consult the respective block description chapter for information on the module behavior in system stop, system pseudo stop, and system wait mode. an important source of information about the clock system is the clock and reset generator (crg) block description chapter. 1.5.2.1 system stop modes the system stop modes are entered if the cpu executes the stop instruction and the xgate doesnt execute a thread and the xgfact bit in the xgmctl register is cleared. depending on the state of the pstp bit in the clksel register the mcu goes into pseudo stop mode or full stop mode. please refer to crg block description chapter. asserting reset, xirq, irq or any other interrupt ends the system stop modes. 1.5.2.2 pseudo stop mode in this mode the clocks are stopped but the oscillator is still running and the real time interrupt (rti) or watchdog (cop) submodule can stay active. other peripherals are turned off. this mode consumes more current than the system stop mode, but the wake up time from this mode is signi?antly shorter. 1.5.2.3 full stop mode the oscillator is stopped in this mode. all clocks are switched off. all counters and dividers remain frozen. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 55 1.5.2.4 system wait mode this mode is entered when the cpu executes the wai instruction. in this mode the cpu will not execute instructions. the internal cpu clock is switched off. all peripherals and the xgate can be active in system wait mode. for further power consumption savings, the peripherals can individually turn off their local clocks. asserting reset, xirq, irq or any other interrupt that has not been masked ends system wait mode. 1.5.3 freeze mode the enhanced capture timer, pulse width modulator, analog-to-digital converter, the periodic interrupt timer and the xgate module provide a software programmable option to freeze the module status during the background debug module is active. this is useful when debugging application software. for detailed description of the behavior of the atd, ect, pwm, xgate and pit when the background debug module is active consult the corresponding module block description chapters. 1.6 resets and interrupts consult the s12xcpu block description chapter for information on exception processing. 1.6.1 vectors table 1-9 lists all interrupt sources and vectors in the default order of priority. the interrupt module (s12xint) provides an interrupt vector base register (ivbr) to relocate the vectors. associated with each i-bit maskable service request is a con?uration register. it selects if the service request is enabled, the service request priority level and whether the service request is handled either by the s12x cpu or by the xgate module. 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 56 freescale semiconductor table 1-9. interrupt vector locations (sheet 1 of 3) vector address 1 xgate channel id 2 interrupt source ccr mask local enable 0xfffe system reset or illegal access reset none none 0xfffc clock monitor reset none pllctl (cme, scme) 0xfffa cop watchdog reset none cop rate select vector base + 0xf8 unimplemented instruction trap none none vector base+ 0xf6 swi none none vector base+ 0xf4 xirq x bit none vector base+ 0xf2 irq i bit irqcr (irqen) vector base+ 0xf0 0x78 real time interrupt i bit crgint (rtie) vector base+ 0xee 0x77 enhanced capture timer channel 0 i bit tie (c0i) vector base + 0xec 0x76 enhanced capture timer channel 1 i bit tie (c1i) vector base+ 0xea 0x75 enhanced capture timer channel 2 i bit tie (c2i) vector base+ 0xe8 0x74 enhanced capture timer channel 3 i bit tie (c3i) vector base+ 0xe6 0x73 enhanced capture timer channel 4 i bit tie (c4i) vector base+ 0xe4 0x72 enhanced capture timer channel 5 i bit tie (c5i) vector base + 0xe2 0x71 enhanced capture timer channel 6 i bit tie (c6i) vector base+ 0xe0 0x70 enhanced capture timer channel 7 i bit tie (c7i) vector base+ 0xde 0x6f enhanced capture timer over?w i bit tsrc2 (tof) vector base+ 0xdc 0x6e pulse accumulator a over?w i bit pactl (paovi) vector base + 0xda 0x6d pulse accumulator input edge i bit pactl (pai) vector base + 0xd8 0x6c spi i bit spcr1 (spie, sptie) vector base+ 0xd6 0x6b sci0 i bit sci0cr2 (tie, tcie, rie, ilie) vector base + 0xd4 0x6a sci1 i bit sci1cr2 (tie, tcie, rie, ilie) vector base + 0xd2 0x69 atd i bit atdctl2 (ascie) vector base + 0xd0 0x68 reserved i bit reserved vector base + 0xce 0x67 port ad i bit piead (piead7 - piead0) vector base + 0xcc 0x66 reserved i bit reserved vector base + 0xca 0x65 modulus down counter under?w i bit mcctl(mczi) vector base + 0xc8 0x64 pulse accumulator b over?w i bit pbctl(pbovi) vector base + 0xc6 0x63 crg pll lock i bit crgint(lockie) vector base + 0xc4 0x62 crg self-clock mode i bit crgint (scmie) vector base + 0xc2 0x61 reserved i bit reserved vector base + 0xc0 0x60 iic0 bus i bit ib0cr (ibie) vector base + 0xbe 0x5f reserved i bit reserved 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 57 vector base + 0xbc 0x5e reserved i bit reserved vector base + 0xba 0x5d eeprom i bit ecnfg (ccie, cbeie) vector base + 0xb8 0x5c flash i bit fcnfg (ccie, cbeie) vector base + 0xb6 0x5b can0 wake-up i bit can0rier (wupie) vector base + 0xb4 0x5a can0 errors i bit can0rier (cscie, ovrie) vector base + 0xb2 0x59 can0 receive i bit can0rier (rxfie) vector base + 0xb0 0x58 can0 transmit i bit can0tier (txeie[2:0]) vector base + 0xae 0x57 can1 wake-up i bit can1rier (wupie) vector base + 0xac 0x56 can1 errors i bit can1rier (cscie, ovrie) vector base + 0xaa 0x55 can1 receive i bit can1rier (rxfie) vector base + 0xa8 0x54 can1 transmit i bit can1tier (txeie[2:0]) vector base + 0xa6 0x53 reserved i bit reserved vector base + 0xa4 0x52 reserved i bit reserved vector base + 0xa2 0x51 ssd4 i bit mdc4ctl (mczie, aovie) vector base + 0xa0 0x50 ssd0 i bit mdc0ctl (mczie, aovie) vector base + 0x9e 0x4f ssd1 i bit mdc1ctl (mczie, aovie) vector base+ 0x9c 0x4e ssd2 i bit mdc2ctl (mczie, aovie) vector base+ 0x9a 0x4d ssd3 i bit mdc3ctl (mczie, aovie) vector base + 0x98 0x4c ssd5 i bit mdc5ctl (mczie, aovie) vector base + 0x96 0x4b motor control timer over?w i bit mcctl1 (mcocie) vector base + 0x94 0x4a reserved i bit reserved vector base + 0x92 0x49 reserved i bit reserved vector base + 0x90 0x48 reserved i bit reserved vector base + 0x8e 0x47 reserved i bit reserved vector base+ 0x8c 0x46 pwm emergency shutdown i bit pwmsdn (pwmie) vector base + 0x8a 0x45 reserved i bit reserved vector base + 0x88 0x44 reserved i bit reserved vector base + 0x86 0x43 reserved i bit reserved vector base + 0x84 0x42 reserved i bit reserved vector base + 0x82 0x41 iic1 bus i bit ib1cr (ibie) vector base + 0x80 0x40 low-voltage interrupt (lvi) i bit vregctrl (lvie) vector base + 0x7e 0x3f autonomous periodical interrupt (api) i bit vregapictrl (apie) vector base + 0x7c 0x3e reserved i bit reserved vector base + 0x7a 0x3d periodic interrupt timer channel 0 i bit pitinte (pinte0) table 1-9. interrupt vector locations (sheet 2 of 3) vector address 1 xgate channel id 2 interrupt source ccr mask local enable 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 58 freescale semiconductor 1.6.2 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block description chapters for register reset states. 1.6.2.1 i/o pins refer to the pim block description chapter for reset con?urations of all peripheral module ports. 1.6.2.2 memory the ram array is not initialized out of reset. 1.7 cop con?uration the cop timeout rate bits cr[2:0] and the wcop bit in the copctl register are loaded on rising edge of reset from the flash control register fctl (0x0107) located in the flash eeprom block. see table 1-10 and table 1-11 for coding. the fctl register is loaded from the flash con?uration ?ld byte at global address 0x7fff0e during the reset sequence vector base + 0x78 0x3c periodic interrupt timer channel 1 i bit pitinte (pinte1) vector base + 0x76 0x3b periodic interrupt timer channel 2 i bit pitinte (pinte2) vector base + 0x74 0x3a periodic interrupt timer channel 3 i bit pitinte (pinte3) vector base + 0x72 0x39 xgate software trigger 0 i bit xgmctl (xgie) vector base + 0x70 0x38 xgate software trigger 1 i bit xgmctl (xgie) vector base + 0x6e 0x37 xgate software trigger 2 i bit xgmctl (xgie) vector base + 0x6c 0x36 xgate software trigger 3 i bit xgmctl (xgie) vector base + 0x6a 0x35 xgate software trigger 4 i bit xgmctl (xgie) vector base + 0x68 0x34 xgate software trigger 5 i bit xgmctl (xgie) vector base + 0x66 0x33 xgate software trigger 6 i bit xgmctl (xgie) vector base + 0x64 0x32 xgate software trigger 7 i bit xgmctl (xgie) vector base + 0x62 xgate software error interrupt i bit xgmctl (xgie) vector base + 0x60 s12xcpu ram access violation i bit ramwpc (avie) vector base+ 0x12 to vector base + 0x5e reserved reserved vector base + 0x10 spurious interrupt none 1 16 bits vector address based 2 for detailed description of xgate channel id refer to xgate block description chapter table 1-9. interrupt vector locations (sheet 3 of 3) vector address 1 xgate channel id 2 interrupt source ccr mask local enable 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 59 note if the mcu is secured the cop timeout rate is always set to the longest period (cr[2:0] = 111) after cop reset. 1.8 atd external trigger input connection the atd_10b16c module includes four external trigger inputs etrig0, etrig1, etrig2, and etrig3. the external trigger feature allows the user to synchronize atd conversion to external trigger events. table 1-12 shows the connection of the external trigger inputs on MC9S12XHZ512. consult the atd_10b16c block description chapter for information about the analog-to-digital converter module. table 1-10. initial cop rate con?uration nv[2:0] in fctl register cr[2:0] in copctl register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 table 1-11. initial wcop con?uration nv[3] in fctl register wcop in copctl register 10 01 table 1-12. atd external trigger sources external trigger input connectivity etrig0 pulse width modulator channel 1 etrig1 pulse width modulator channel 3 etrig2 periodic interrupt timer hardware trigger 0 etrig3 periodic interrupt timer hardware trigger 1 4 .com u datasheet
chapter 1 device overview (MC9S12XHZ512v1) MC9S12XHZ512 data sheet, rev. 1.02 60 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 61 chapter 2 port integration module (s12xhzpimv1) 2.1 lntroduction the port integration module establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (s12x_ebi) and the i/o pins for all ports. it controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. this section covers: port a, b and k associated with s12x_ebi module and the lcd driver port c and d associated with s12x_ebi module port e associated with s12x_ebi module, the irq, xirq interrupt inputs, and the lcd driver port ad associated with atd module (channels 7 through 0) and keyboard wake-up interrupts port l connected to the lcd driver and atd (channels 15 through 8) modules port m connected to 2 can modules port p connected to 1 sci, 2 iic and pwm modules port s connected to 2 sci and 1 spi modules port t connected to 2 iic, 1 ect and lcd driver modules port u, v and w associated with pwm motor control and stepper stall detect modules each i/o pin can be configured by several registers: input/output selection, drive strength reduction, enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags. 2.1.1 features a standard port has the following minimum features: input/output selection 5-v output drive with two selectable drive strength (or slew rates) 5-v digital and analog input input with selectable pull-up or pull-down device optional features: open drain for wired-or connections interrupt input with glitch filtering 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 62 freescale semiconductor 2.1.2 block diagram figure 2-1 is a block diagram of the s12xhzpim figure 2-1. s12xhzpim block diagram bkgd xirq irq eclk pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 miso mosi ps4 ps5 ps0 ps1 pk3 pk0 pk1 sck ss ps6 ps7 spi rxcan0 txcan0 pm2 pm3 ddra ddrb pta ptb ddre pte ptk ddrk pts ddrs ptm ddrm pk2 fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 fp22 fp21 fp20 lcd driver can0 modb/ taghi moda/ taglo/ re fp13 pb5 pb3 pb2 pb1 fp5 addr16/iqstat0 addr17/iqstat1 addr18/iqstat2 addr19/iqstat3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 fp24 fp25 fp26 fp27 an2 an6 an0 an7 an1 an3 an4 an5 pad3 pad4 pad5 pad6 pad7 pad0 pad1 pad2 analog to digital converter ddrad ew ait/romctl enhanced capture timer pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 single-wire background debug module rxcan1 txcan1 pm4 pm5 can1 m0c0m m0c0p pu0 pu1 ptu ddru pwm0 ssd0 m0c1m m0c1p pu2 pu3 pwm1 m1c0m m1c0p pu4 pu5 pwm2 ssd1 m1c1m m1c1p pu6 pu7 pwm3 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 ptp ddrp rxd0 txd0 sci0 an10 an14 an8 an15 an9 an11 an12 an13 an10 an14 an8 an15 an9 an11 an12 an13 kwad2 kwad6 kwad0 kwad7 kwad1 kwad3 kwad4 kwad5 m0cosm m0cosp m0sinm m0sinp m1cosm m1cosp m1sinm m1sinp ptad m2c0m m2c0p pv0 pv1 ptv ddrv pwm4 ssd2 m2c1m m2c1p pv2 pv3 pwm5 m3c0m m3c0p pv4 pv5 pwm6 ssd3 m3c1m m3c1p pv6 pv7 pwm7 m2cosm m2cosp m2sinm m2sinp m3cosm m3cosp m3sinm m3sinp rxd1 txd1 sci1 ps2 ps3 sda0 scl0 pm1 iic0 pp6 pp7 pk7 fp23 pc4 pc0 pc7 pc6 ddrc ptc pc5 pc3 pc2 pc1 data8 data9 data10 data11 data12 data13 data14 data15 pd4 pd0 pd7 pd6 ddrd ptd pd5 pd3 pd2 pd1 data0 data1 data2 data3 data4 data5 data6 data7 pe7 pe2 pe3 xclks/ eclkx2 lstrb/ lds/eromctl r w/ we pt4 pt3 pt2 pt1 pt0 pt7 pt6 pt5 ddrt ptt ioc0 ioc1 ioc2 ioc3 ioc4 ioc5 ioc6 ioc7 non-multiplexed external bus interface sda1 scl1 iic1 sda0 scl0 sda1 scl1 m4c0m m4c0p pw0 pw1 ptw ddrw pwm8 ssd4 m4c1m m4c1p pw2 pw3 pwm9 m5c0m m5c0p pw4 pw5 pwm10 ssd5 m5c1m m5c1p pw6 pw7 pwm11 m4cosm m4cosp m4sinm m4sinp m5cosm m5cosp m5sinm m5sinp pk4 addr20/acc0 pk5 addr21/acc1 pk6 addr22/acc2 cs1 cs3 cs0 cs2 port integration module pw6 pw7 module-to-port-routing 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 63 2.2 external signal description this section lists and describes the signals that connect off chip. table 2-1 shows all the pins and their functions that are controlled by the s12xhzpim. the order in which the pin functions are listed represents the functions priority (top ?highest priority, bottom ?lowest priority). table 2-1. detailed signal descriptions (sheet 1 of 6) port pin name pin function and priority i/o description pin function after reset bkgd modc i modc input during reset bkgd bkgd i/o s12x_bdm communication pin a pa[7:0] addr[15:8] mux ivd[15:8] o high-order external bus address output (multiplexed with ivis data) mode dependent fp[15:8] o lcd frontplane driver gpio i/o general-purpose i/o b pb[7:1] addr[7:1] mux ivd[7:1] o low-order external bus address output (multiplexed with ivis data) mode dependent fp[7:1] o lcd frontplane driver gpio i/o general-purpose i/o pb[0] addr0 mux ivd0 o low-order external bus address output (multiplexed with ivis data) uds o upper data strobe fp[0] o lcd frontplane driver gpio i/o general-purpose i/o c pc[7:0] data[15:8] i/o high-order bidirectional data input/output con?urable for reduced input threshold mode dependent gpio i/o general-purpose i/o d pd[7:0] data[7:0] i/o low-order bidirectional data input/output con?urable for reduced input threshold mode dependent gpio i/o general-purpose i/o 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 64 freescale semiconductor e pe[7] xclks i external clock selection input during reset mode dependent eclkx2 o free-running clock output at core clock rate (eclk x 2) fp[22] o lcd frontplane driver gpio i/o general-purpose i/o pe[6] modb i modb input during reset t a ghi i instruction tagging low pin con?urable for reduced input threshold gpio i/o general-purpose i/o pe[5] moda i moda input during reset re o read enable signal t a glo i instruction tagging low pin con?urable for reduced input threshold gpio i/o general-purpose i/o pe[4] eclk o free-running clock output at the bus clock rate or programmable divided in normal modes gpio i/o general-purpose i/o pe[3] eromctl i eromon bit control input during reset lstrb o low strobe bar output lds o lower data strobe fp[21] o lcd frontplane driver gpio i/o general-purpose i/o pe[2] r/ w o read/write output for external bus we o write enable fp[20] o lcd frontplane driver gpio i/o general-purpose i/o pe[1] irq i maskable level or falling edge-sensitive interrupt input gpio i/o general-purpose i/o pe[0] xirq i non-maskable level-sensitive interrupt input gpio i/o general-purpose i/o k pk[7] r omctl i romon bit control input during reset mode dependent ew ait i external wait signal con?urable for reduced input threshold fp[23] o lcd frontplane driver gpio i/o general-purpose i/o pk[6:4] addr[22:20] mux acc[2:0] o extended external bus address output (multiplexed with master access output) gpio i/o general-purpose i/o pk[3:0] addr[19:16] mux iqstat[3:0] o extended external bus address output (multiplexed with instruction pipe status bits) bp[3:0] o lcd backplane driver gpio i/o general-purpose i/o ad pad[7:0] an[7:0] i analog-to-digital converter input channel gpio kwad[7:0] i keyboard wake-up interrupt gpio i/o general-purpose i/o table 2-1. detailed signal descriptions (sheet 2 of 6) port pin name pin function and priority i/o description pin function after reset 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 65 l pl[7:4] fp[31:28] o lcd frontplane driver gpio an[15:12] i analog-to-digital converter input channel gpio i/o general-purpose i/o pl[3:0] fp[19:16] o lcd frontplane driver an[11:8] i analog-to-digital converter input channel gpio i/o general-purpose i/o m pm[5] txcan1 o mscan1 transmit pin gpio gpio i/o general-purpose i/o pm[4] rxcan1 i mscan1 receive pin gpio i/o general-purpose i/o pm[3] txcan0 o mscan0 transmit pin gpio i/o general-purpose i/o pm[2] rxcan0 i mscan0 receive pin gpio o general-purpose i/o pm[1] cs1 o chip select 1 gpio i/o general-purpose i/o p pp[7] cs2 o chip select 2 gpio pwm7 i/o pulse-width modulator channel 7 and emergency shutdown input scl1 i/o inter-integrated circuit 1 serial clock line gpio i/o general-purpose i/o pp[6] cs0 o chip select 0 pwm6 o pulse-width modulator channel 6 sda1 i/o inter-integrated circuit 1 serial data line gpio i/o general-purpose i/o pp[5] pwm5 i/o pulse-width modulator channel 5 and emergency shutdown input scl0 i/o inter-integrated circuit 0 serial clock line gpio i/o general-purpose i/o pp[4] pwm4 o pulse-width modulator channel 4 sda0 i/o inter-integrated circuit 0 serial data line gpio i/o general-purpose i/o pp[3] pwm3 o pulse-width modulator channel 3 gpio i/o general-purpose i/o pp[2] pwm2 o pulse-width modulator channel 2 rxd1 i serial communication interface 1 receive pin gpio i/o general-purpose i/o pp[1] pwm1 o pulse-width modulator channel 1 gpio i/o general-purpose i/o pp[0] pwm0 o pulse-width modulator channel 0 txd1 o serial communication interface 1 transmit pin gpio i/o general-purpose i/o table 2-1. detailed signal descriptions (sheet 3 of 6) port pin name pin function and priority i/o description pin function after reset 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 66 freescale semiconductor s ps[7] ss i/o serial peripheral interface slave select input/output in master mode, input in slave mode gpio gpio i/o general-purpose i/o ps[6] sck i/o serial peripheral interface serial clock pin gpio i/o general-purpose i/o ps[5] mosi i/o serial peripheral interface master out/slave in pin gpio i/o general-purpose i/o ps[4] miso i/o serial peripheral interface master in/slave out pin gpio i/o general-purpose i/o ps[3] txd1 o serial communication interface 1 transmit pin gpio i/o general-purpose i/o ps[2] cs3 o chip select 3 rxd1 i serial communication interface 1 receive pin gpio i/o general-purpose i/o ps[1] txd0 o serial communication interface 0 transmit pin gpio i/o general-purpose i/o ps[0] rxd0 i serial communication interface 0 receive pin gpio i/o general-purpose i/o t pt[7] ioc7 i/o timer channel gpio scl1 i/o inter-integrated circuit 1 serial clock line gpio i/o general-purpose i/o pt[6] ioc7 i/o timer channel sda1 i/o inter-integrated circuit 1 serial data line gpio i/o general-purpose i/o pt[5] ioc5 i/o timer channel scl0 i/o inter-integrated circuit 0 serial clock line gpio i/o general-purpose i/o pt[4] ioc4 i/o timer channel sda0 i/o inter-integrated circuit 0 serial data line gpio i/o general-purpose i/o pt[3:0] fp[27:24] i/o lcd frontplane driver ioc[3:0] i/o timer channel gpio i/o general-purpose i/o table 2-1. detailed signal descriptions (sheet 4 of 6) port pin name pin function and priority i/o description pin function after reset 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 67 u pu[7] m1sinp o ssd1 sine+ node gpio m1c1p o pwm motor controller channel 3 gpio i/o general-purpose i/o pu[6] m1sinm o ssd1 sine- node m1c1m o pwm motor controller channel 3 gpio i/o general-purpose i/o pu[5] m1cosp o ssd1 cosine+ node m1c0p o pwm motor controller channel 2 gpio i/o general-purpose i/o pu[4] m1cosm o ssd1 cosine- node m1c0m o pwm motor controller channel 2 gpio i/o general-purpose i/o pu[3] m0sinp o ssd0 sine+ node m0c1p o pwm motor controller channel 1 gpio i/o general-purpose i/o pu[2] m0sinm o ssd0 sine- node m0c1m o pwm motor controller channel 1 gpio i/o general-purpose i/o pu[1] m0cosp o ssd0 cosine+ node m0c0p o pwm motor controller channel 0 gpio i/o general-purpose i/o pu[0] m0cosm o ssd0 cosine- node m0c0m o pwm motor controller channel 0 gpio i/o general-purpose i/o v pv[7] m3sinp o ssd3 sine+ node gpio m3c1p o pwm motor controller channel 7 gpio i/o general-purpose i/o pv[6] m3sinm o ssd3 sine- node m3c1m o pwm motor controller channel 7 gpio i/o general-purpose i/o pv[5] m3cosp o ssd3 cosine+ node m3c0p o pwm motor controller channel 6 gpio i/o general-purpose i/o pv[4] m3cosm o ssd3 cosine- node m3c0m o pwm motor controller channel 6 gpio i/o general-purpose i/o pv[3] m2sinp o ssd2 sine+ node m2c1p o pwm motor controller channel 5 gpio i/o general-purpose i/o pv[2] m2sinm o ssd2 sine- node m2c1m o pwm motor controller channel 5 gpio i/o general-purpose i/o pv[1] m2cosp o ssd2 cosine+ node m2c0p o pwm motor controller channel 4 gpio i/o general-purpose i/o pv[0] m2cosm o ssd2 cosine- node m2c0m o pwm motor controller channel 4 gpio i/o general-purpose i/o table 2-1. detailed signal descriptions (sheet 5 of 6) port pin name pin function and priority i/o description pin function after reset 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 68 freescale semiconductor w pw[7] m5sinp o ssd5 sine+ node gpio m5c1p o pwm motor controller channel 11 gpio i/o general-purpose i/o pw[6] m5sinm o ssd5 sine- node m5c1m o pwm motor controller channel 11 gpio i/o general-purpose i/o pw[5] m5cosp o ssd5 cosine+ node m5c0p o pwm motor controller channel 10 gpio i/o general-purpose i/o pw[4] m5cosm o ssd5 cosine- node m5c0m o pwm motor controller channel 10 gpio i/o general-purpose i/o pw[3] m4sinp o ssd4 sine+ node m4c1p o pwm motor controller channel 9 gpio i/o general-purpose i/o pw[2] m4sinm o ssd4 sine- node m4c1m o pwm motor controller channel 9 gpio i/o general-purpose i/o pw[1] m4cosp o ssd4 cosine+ node m4c0p o pwm motor controller channel 8 gpio i/o general-purpose i/o pw[0] m4cosm o ssd4 cosine- node m4c0m o pwm motor controller channel 8 gpio i/o general-purpose i/o table 2-1. detailed signal descriptions (sheet 6 of 6) port pin name pin function and priority i/o description pin function after reset 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 69 2.3 memory map and register de?ition this section provides a detailed description of all registers. table 2-2 is a standard memory map of port integration module. table 2-2. s12xhzpim memory map address offset use access 0x0000 port a i/o register (pta) r/w 0x0001 port b i/o register (ptb) r/w 0x0002 port a data direction register (ddra) r/w 0x0003 port b data direction register (ddrb) r/w 0x0004 port c i/o register (ptc) r/w 0x0005 port d i/o register (ptd) r/w 0x0006 port c data direction register (ddrc) r/w 0x0007 port d data direction register (ddrd) r/w 0x0008 port e i/o register (pte) r/w 0x0009 port e data direction register (ddre) r/w 0x000a - 0x000b non-pim address range 0x000c pull up/down control register (pucr) r/w 0x000d reduced drive register (rdriv) r/w 0x000e - 0x001b non-pim address range 0x001c eclk control register (eclkcr) r/w 0x001d reserved 0x001e irq control register (irqcr) r/w 0x001f slew rate control register (srcr) r/w 0x0020 - 0x0031 non-pim address range 0x0032 port k i/o register (ptk) r/w 0x0033 port k data direction register (ddrk) r/w 0x0034 - 0x01ff non-pim address range 0x0200 port t i/o register (ptt) r/w 0x0201 port t input register (ptit) r 0x0202 port t data direction register (ddrt) r/w 0x0203 port t reduced drive register (rdrt) r/w 0x0204 port t pull device enable register (pert) r/w 0x0205 port t polarity select register (ppst) r/w 0x0206 port t wired-or mode register (womt) r/w 0x0207 port t slew rate register (srrt) r/w 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 70 freescale semiconductor 0x0208 port s i/o register (pts) r/w 0x0209 port s input register (ptis) r 0x020a port s data direction register (ddrs) r/w 0x020b port s reduced drive register (rdrs) r/w 0x020c port s pull device enable register (pers) r/w 0x020d port s polarity select register (ppss) r/w 0x020e port s wired-or mode register (woms) r/w 0x020f port s slew rate register (srrs) r/w 0x0210 port m i/o register (ptm) r/w 0x0211 port m input register (ptim) r 0x0212 port m data direction register (ddrm) r/w 0x0213 port m reduced drive register (rdrm) r/w 0x0214 port m pull device enable register (perm) r/w 0x0215 port m polarity select register (ppsm) r/w 0x0216 port m wired-or mode register (womm) r/w 0x0217 port m slew rate register (srrm) r/w 0x0218 port p i/o register (ptp) r/w 0x0219 port p input register (ptip) r 0x021a port p data direction register (ddrp) r/w 0x021b port p reduced drive register (rdrp) r/w 0x021c port p pull device enable register (perp) r/w 0x021d port p polarity select register (ppsp) r/w 0x021e port p wired-or mode register (womp) r/w 0x021f port p slew rate register (srrp) r/w 0x0220 - 0x022f reserved 0x0230 port l i/o register (ptl) r/w 0x0231 port l input register (ptil) r 0x0232 port l data direction register (ddrl) r/w 0x0233 port l reduced drive register (rdrl) r/w 0x0234 port l pull device enable register (perl) r/w 0x0235 port l polarity select register (ppsl) r/w 0x0236 reserved 0x0237 port l slew rate register (srrl) r/w 0x0238 port u i/o register (ptu) r/w 0x0239 port u input register (ptiu) r 0x023a port u data direction register (ddru) r/w 0x023b port u slew rate register (srru) r/w 0x023c port u pull device enable register (peru) r/w 0x023d port u polarity select register (ppsu) r/w 0x023e - 0x023f reserved table 2-2. s12xhzpim memory map (continued) address offset use access 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 71 0x0240 port v i/o register (ptv) r/w 0x0241 port v input register (ptiv) r 0x0242 port v data direction register (ddrv) r/w 0x0243 port v slew rate register (srrv) r/w 0x0244 port v pull device enable register (perv) r/w 0x0245 port v polarity select register (ppsv) r/w 0x0246 - 0x0247 reserved 0x0248 port w i/o register (ptw) r/w 0x0249 port w input register (ptiw) r 0x024a port w data direction register (ddrw) r/w 0x024b port w slew rate register (srrw) r/w 0x024c port w pull device enable register (perw) r/w 0x024d port w polarity select register (ppsw) r/w 0x024e - 0x0250 reserved 0x0251 port ad i/o register (ptad) r/w 0x0252 reserved 0x0253 port ad input register (ptiad) r 0x0254 reserved 0x0255 port ad data direction register (ddrad) r/w 0x0256 reserved 0x0257 port ad reduced drive register (rdrad) r/w 0x0258 reserved 0x0259 port ad pull device enable register (perad) r/w 0x025a reserved 0x025b port ad polarity select register (ppsad) r/w 0x025c reserved 0x025d port ad interrupt enable register (piead) r/w 0x025e reserved 0x025f port ad interrupt flag register (pifad) r/w 0x0260 - 0x027f reserved table 2-2. s12xhzpim memory map (continued) address offset use access 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 72 freescale semiconductor 2.3.1 port a and port b port a and port b are associated with the external address bus outputs addr15-addr0, the external read visibility ivd15-ivd0 and the liquid crystal display (lcd) driver. each pin is assigned to these functions according to the following priority: lcd driver > xebi > general-purpose i/o. if the corresponding lcd frontplane drivers are enabled (and lcd module is enabled), the fp[15:0] outputs of the lcd module are available on port b and port a pins. refer to the lcd block description chapter for information on enabling and disabling the lcd and its frontplane drivers.refer to the s12x_ebi block description chapter for information on external bus. during reset, port a and port b pins are configured as inputs with pull down. 2.3.1.1 port a i/o register (pta) read: anytime. write: anytime. if the associated data direction bit (ddrax) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrax) is set to 0 (input) and the lcd frontplane driver is enabled (and lcd module is enabled), the associated i/o register bit (ptax) reads ?? if the associated data direction bit (ddrax) is set to 0 (input) and the lcd frontplane driver is disabled (or lcd module is disabled), a read returns the value of the pin. 76543210 r pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 w xebi: addr15 mux ivd15 addr14 mux ivd14 addr13 mux ivd13 addr12 mux ivd12 addr11 mux ivd11 addr10 mux ivd10 addr9 mux ivd9 addr8 mux ivd8 lcd: fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 reset 0 0 0 00000 figure 2-2. port a i/o register (pta) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 73 2.3.1.2 port b i/o register (ptb) read: anytime. write: anytime. if the associated data direction bit (ddrbx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrbx) is set to 0 (input) and the lcd frontplane driver is enabled (and lcd module is enabled), the associated i/o register bit (ptbx) reads ?? if the associated data direction bit (ddrbx) is set to 0 (input) and the lcd frontplane driver is disabled (or lcd module is disabled), a read returns the value of the pin. 2.3.1.3 port a data direction register (ddra) read: anytime. write: anytime. this register configures port pins pa[7:0] as either input or output.if a lcd frontplane driver is enabled (and lcd module is enabled), it outputs an analog signal to the corresponding pin and the associated data direction register bit has no effect. if a lcd frontplane driver is disabled (or lcd module is disabled), the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 76543210 r ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 w xebi: addr7 mux ivd7 addr6 mux ivd6 addr5 mux ivd5 addr4 mux ivd4 addr3 mux ivd3 addr2 mux ivd2 addr1 mux ivd1 addr0 mux ivd0 or uds lcd: fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 reset 0 0 0 00000 figure 2-3. port b i/o register (ptb) 76543210 r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w reset 0 0 0 00000 figure 2-4. port a data direction register (ddra) table 2-3. ddra field descriptions field description 7:0 ddra[7:0] data direction port a 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 74 freescale semiconductor 2.3.1.4 port b data direction register (ddrb) read: anytime. write: anytime. this register configures port pins pb[7:0] as either input or output.if a lcd frontplane driver is enabled (and lcd module is enabled), it outputs an analog signal to the corresponding pin and the associated data direction register bit has no effect. if a lcd frontplane driver is disabled (or lcd module is disabled), the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 76543210 r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w reset 0 0 0 00000 figure 2-5. port b data direction register (ddrb) table 2-4. ddrb field descriptions field description 7:0 ddrb[7:0] data direction port b 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 75 2.3.2 port c and port d port c and port d pins can be used for either general-purpose i/o or the external data bus input/outputs data15-data0. refer to the s12x_ebi block description chapter for information on external bus. 2.3.2.1 port c i/o register (ptc) read: anytime. write: anytime. if the data direction bit of the associated i/o pin (ddrcx) is set to 1 (output), a write to the corresponding i/o register bit sets the value to be driven to the port c pin. if the data direction bit of the associated i/o pin (ddrcx) is set to 0 (input), a write to the corresponding i/o register bit takes place but has no effect on the port c pin. if the associated data direction bit (ddrcx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrcx) is set to 0 (input), a read returns the value of the pin. 2.3.2.2 port d i/o register (ptd) read: anytime. write: anytime. if the data direction bit of the associated i/o pin (ddrdx) is set to 1 (output), a write to the corresponding i/o register bit sets the value to be driven to the port d pin. if the data direction bit of the associated i/o pin (ddrdx) is set to 0 (input), a write to the corresponding i/o register bit takes place but has no effect on the port d pin. if the associated data direction bit (ddrdx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrdx) is set to 0 (input), a read returns the value of the pin. 76543210 r ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 w xebi: data15 data14 data13 data12 data11 data10 data9 data8 reset 0 0 0 00000 figure 2-6. port c i/o register (ptc) 76543210 r ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 w xebi: data7 data6 data5 data4 data3 data2 data1 data0 reset 0 0 0 00000 figure 2-7. port d i/o register (ptd) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 76 freescale semiconductor 2.3.2.3 port c data direction register (ddrc) read: anytime. write: anytime. this register configures port pins pc[7:0] as either input or output. 2.3.2.4 port d data direction register (ddrd) read: anytime. write: anytime. this register configures port pins pd[7:0] as either input or output. 76543210 r ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 w reset 0 0 0 00000 figure 2-8. port c data direction register (ddrc) table 2-5. ddrc field descriptions field description 7:0 ddrc[7:0] data direction port c 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 76543210 r ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 w reset 0 0 0 00000 figure 2-9. port d data direction register (ddrd) table 2-6. ddrd field descriptions field description 7:0 ddrd[7:0] data direction port d 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 77 2.3.3 port e port e pins can be used for either general-purpose i/o, or the liquid crystal display (lcd) driver, or the external bus control outputs r/ w, we, lstrb, lds and re, the free running clock outputs eclk and eclkx2, or the inputs t a ghi, t a glo, moda, modb, eromctl, xclks and interrupts irq and xirq. refer to the lcd block description chapter for information on enabling and disabling the lcd and its frontplane drivers. refer to the s12x_ebi block description chapter for information on external bus. port e pin pe[7] can be used for either general-purpose i/o, or as the free-running clock eclkx2 output running at the core clock rate, or the frontplane driver fp22. the clock eclkx2 output is always enabled in emulation modes. port e pin pe[4] can be used for either general-purpose i/o or as the free-running clock eclk output running at the bus clock rate or at the programmed divided clock rate. the clock output is always enabled in emulation modes. port e pin pe[1] can be used for either general-purpose input or as the level- or falling edge-sensitive irq interrupt inpu. irq will be enabled by setting the irqen configuration bit and clearing the i-bit in the cpu? condition code register. it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. port e pin pe[0] can be used for either general-purpose input or as the level-sensitive xirq interrupt input. xirq can be enabled by clearing the x-bit in the cpu? condition code register. it is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up. 2.3.3.1 port e i/o register (pte) read: anytime. write: anytime. if the associated data direction bit (ddrex) is set to 1 (output), a read returns the value of the i/o register bit. 76543210 r pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 w xebi: xclks 1 or eclkx2 1 function active when reset asserted. modb 1 or t a ghi moda 1 or t a glo or re eclk eromctl 1 or lstrb or lds r/ w or we irq xirq lcd: fp22 fp21 fp20 reset 0 0 0 0 0 0 2 2 these registers are reset to zero. two bus clock cycles after reset release the register values are updated with the associated pin values. 2 figure 2-10. port e i/o register (pte) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 78 freescale semiconductor if the associated data direction bit (ddrex) is set to 0 (input) and the lcd frontplane driver is enabled (and lcd module is enabled), the associated i/o register bit (ptex) reads ?? if the associated data direction bit (ddrex) is set to 0 (input) and the lcd frontplane driver is disabled (or lcd module is disabled), a read returns the value of the pin. 2.3.3.2 port e data direction register (ddre) read: anytime. write: anytime. this register configures port pins pe[7:0] as either input or output.if a lcd frontplane driver is enabled (and lcd module is enabled), it outputs an analog signal to the corresponding pin and the associated data direction register bit has no effect. if a lcd frontplane driver is disabled (or lcd module is disabled), the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 76543210 r ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 00 w reset 0 0 0 00000 = reserved or unimplemented figure 2-11. port e data direction register (ddre) table 2-7. ddre field descriptions field description 7:2 ddre[7:2] data direction port e 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 79 2.3.4 port k port k pins can be used for either general-purpose i/o, or the liquid crystal display (lcd) driver, or the external address bus outputs addr22-addr16 muxed with master access output acc2-acc0 and instruction pipe signals iqstat3-iqstat0, or inputs ew ait and romctl. refer to the lcd block description chapter for information on enabling and disabling the lcd and its frontplane drivers. refer to the s12x_ebi block description chapter for information on external bus. 2.3.4.1 port k i/o register (ptk) read: anytime. write: anytime. if the associated data direction bit (ddrkx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrkx) is set to 0 (input) and the lcd frontplane driver is enabled (and lcd module is enabled), the associated i/o register bit (ptkx) reads ?? if the associated data direction bit (ddrkx) is set to 0 (input) and the lcd frontplane driver is disabled (or lcd module is disabled), a read returns the value of the pin. 2.3.4.2 port k data direction register (ddrk) read: anytime. write: anytime. this register configures port pins pk[7:0] as either input or output.if a lcd frontplane driver is enabled (and lcd module is enabled), it outputs an analog signal to the corresponding pin and the associated data 76543210 r ptk7 ptk6 ptk5 ptk4 ptk3 ptk2 ptk1 ptk0 w xebi: romctl 1 or ew ait 1 function active when reset asserted. addr22 or acc2 addr21 or acc1 addr20 or acc0 addr19 or iqstat3 addr18 or iqstat2 addr17 or iqstat1 addr16 or iqstat0 lcd: fp23 bp3 bp2 bp1 bp0 reset 0 0 0 0 0000 figure 2-12. port k i/o register (ptk) 76543210 r ddrk7 ddrk6 ddrk5 ddrk4 ddrk3 ddrk2 ddrk1 ddrk0 w reset 0 0 0 00000 figure 2-13. port k data direction register (ddrk) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 80 freescale semiconductor direction register bit has no effect. if a lcd frontplane driver is disabled (or lcd module is disabled), the corresponding data direction register bit reverts to control the i/o direction of the associated pin. table 2-8. ddrk field descriptions field description 7:0 ddrk[7:0] data direction port k 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 81 2.3.5 miscellaneous registers 2.3.5.1 pull up/down control register (pucr) read: anytime. write: anytime except bkpue which is writable in special test mode only. this register is used to enable pull up/down devices for the associated ports a, b, c, d, e and k. pull up/down devices are assigned on a per-port basis and apply to any pin in the corresponding port currently configured as an input. 76543210 r pupke bkgpe 0 pupee pupde pupce pupbe pupae w reset 1 1 0 10011 figure 2-14. pull up/down control register (pucr) table 2-9. pucr field descriptions field description 7 pupke pull-down port k enable 0 port k pull-down devices are disabled. 1 enable pull-down devices for port k input pins. 6 bkpue bkgd pin pull-up enable 0 bkgd pull-up device is disabled. 1 enable pull-up device on bkgd pin. 4 pupee pull port e enable 0 port e pull-down devices on pins 7, 4? are disabled. port e pull-up devices on pins 1? are disabled. 1 enable pull-down devices for port e input pins 7, 4?. enable pull-up devices for port e input pins 1?. note: bits 5 and 6 of port e have pull-down devices which are only enabled during reset. this bit has no effect on these pins. 3 pupde pull-up port d enable 0 port d pull-up devices are disabled. 1 enable pull-up devices for all port d input pins. 2 pupce pull-up port c enable 0 port c pull-up devices are disabled. 1 enable pull-up devices for all port c. 1 pupbe pull-down port b enable 0 port b pull-down devices are disabled. 1 enable pull-down devices for all port b input pins. 0 pupae pull-down port a enable 0 port a pull-down devices are disabled. 1 enable pull-down devices for all port a input pins. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 82 freescale semiconductor 2.3.5.2 reduced drive register (rdriv) read: anytime. write: anytime. this register is used to select reduced drive for the pins associated with ports a, b, c, d, e, and k. if enabled, the pins drive at about 1/6 of the full drive strength. the reduced drive function is independent of which function is being used on a particular pin. the reduced drive functionality does not take effect on the pins in emulation modes. 76543210 r rdpk 00 rdpe rdpd rdpc rdpb rdpa w reset 0 0 0 00000 = reserved or unimplemented figure 2-15. reduced drive register (rdriv) table 2-10. rdriv field descriptions field description 7 rdpk reduced drive of port k 0 all port k output pins have full drive enabled. 1 all port k output pins have reduced drive enabled. 4 rdpe reduced drive of port e 0 all port e output pins have full drive enabled. 1 all port e output pins have reduced drive enabled. 3 rdpd reduced drive of port d 0 all port d output pins have full drive enabled. 1 all port d output pins have reduced drive enabled. 2 rdpc reduced drive of port c 0 all port c output pins have full drive enabled. 1 all port c output pins have reduced drive enabled. 1 rdpb reduced drive of port b 0 all port b output pins have full drive enabled. 1 all port b output pins have reduced drive enabled. 0 rdpa reduced drive of port a 0 all port a output pins have full drive enabled. 1 all port a output pins have reduced drive enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 83 2.3.5.3 eclk control register (eclkcr) read: anytime. write: anytime. the eclkctl register is used to control the availability of the free-running clocks and the free-running clock divider. 76543210 r neclk nclkx2 0000 ediv1 ediv0 w reset 0 1 1 neclk reset value is 1 in emulation single-chip and normal single-chip modes. 1000000 = reserved or unimplemented figure 2-16. eclk control register (eclkcr) table 2-11. eclkctl field descriptions field description 7 neclk no eclk ?this bit controls the availability of a free-running clock on the eclk pin. clock output is always active in emulation modes and if enabled in all other operating modes. 0 eclk enabled 1 eclk disabled 6 nclkx2 no eclkx2 this bit controls the availability of a free-running clock on the eclkx2 pin. this clock has a xed rate of twice the internal bus clock. clock output is always active in emulation modes and if enabled in all other operating modes. 0 eclkx2 is enabled 1 eclkx2 is disabled 1? ediv[1:0] free-running eclk divider these bits determine the rate of the free-running clock on the eclk pin r . the usage of the bits is shown in table 2-12 . divider is always disabled in emulation modes and active as programmed in all other operating modes. table 2-12. free-running eclk clock rate ediv[1:0] rate of free-running eclk 00 eclk = bus clock rate 01 eclk = bus clock rate divided by 2 10 eclk = bus clock rate divided by 3 11 eclk = bus clock rate divided by 4 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 84 freescale semiconductor 2.3.5.4 irq control register (irqcr) read: see individual bit descriptions below. write: see individual bit descriptions below. 76543210 r irqe irqen 000000 w reset 0 1 0 00000 = reserved or unimplemented figure 2-17. port e data direction register (ddre) table 2-13. irqcr field descriptions field description 7 irqe irq select edge sensitive only special modes: read or write anytime. normal and emulation modes: read anytime, write once. 0 irq con?ured for low level recognition. 1 irq con?ured to respond only to falling edges. falling edges on the irq pin will be detected anytime irqe = 1. the edge detector is cleared only upon the servicing of the irq interrupt or a reset . 6 irqen external irq enable read or write anytime. 0 external irq pin is disconnected from interrupt logic. 1 external irq pin is connected to interrupt logic. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 85 2.3.5.5 slew rate control register (srcr) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for the pins associated with ports a, b, c, d, e, and k. 76543210 r srrk 00 srre srrd srrc srrb srra w reset 0 0 0 00000 = reserved or unimplemented figure 2-18. slew rate control register (srcr) table 2-14. srcr field descriptions field description 7 srrk slew rate of port k 0 disables slew rate control and enables digital input buffer for all port k pins. 1 enables slew rate control and disables digital input buffer for all port k pins. 4 srre slew rate of port e 0 disables slew rate control and enables digital input buffer for all port e pins. 1 enables slew rate control and disables digital input buffer for all port e pins. 3 srrd slew rate of port d 0 disables slew rate control and enables digital input buffer for all port d pins. 1 enables slew rate control and disables digital input buffer for all port d pins. 2 srrc slew rate of port c 0 disables slew rate control and enables digital input buffer for all port c pins. 1 enables slew rate control and disables digital input buffer for all port c pins. 1 srrb slew rate of port b 0 disables slew rate control and enables digital input buffer for all port b pins. 1 enables slew rate control and disables digital input buffer for all port b pins. 0 srra slew rate of port a 0 disables slew rate control and enables digital input buffer for all port a pins. 1 enables slew rate control and disables digital input buffer for all port a pins. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 86 freescale semiconductor 2.3.6 port ad port ad is associated with the analog-to-digital converter (atd) and keyboard wake-up (kwu) interrupts . each pin is assigned to these modules according to the following priority: atd > kwu > general-purpose i/o. for the pins of port ad to be used as inputs, the corresponding bits of the atddien1 register in the atd module must be set to 1 (digital input buffer is enabled). the atddien1 register does not affect the port ad pins when they are configured as outputs. refer to the atd block description chapter for information on the atddien1 register. during reset, port ad pins are configured as high-impedance analog inputs (digital input buffer is disabled). 2.3.6.1 port ad i/o register (ptad) read: anytime. write: anytime. if the data direction bit of the associated i/o pin (ddradx) is set to 1 (output), a write to the corresponding i/o register bit sets the value to be driven to the port ad pin. if the data direction bit of the associated i/o pin (ddradx) is set to 0 (input), a write to the corresponding i/o register bit takes place but has no effect on the port ad pin. if the associated data direction bit (ddradx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddradx) is set to 0 (input) and the associated atddien1 bits is set to 0 (digital input buffer is disabled), the associated i/o register bit (ptadx) reads ?? if the associated data direction bit (ddradx) is set to 0 (input) and the associated atddien1 bits is set to 1 (digital input buffer is enabled), a read returns the value of the pin. 76543210 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w kwu: kwad7 kwad6 kwad5 kwad4 kwad3 kwad2 kwad1 kwad0 atd: an7 an6 an55 an4 an3 an2 an1 an0 reset 0 0 0 00000 figure 2-19. port ad i/o register (ptad) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 87 2.3.6.2 port ad input register (ptiad) read: anytime. write: never; writes to these registers have no effect. if the atddien1 bit of the associated i/o pin is set to 0 (digital input buffer is disabled), a read returns a 1. if the atddien1 bit of the associated i/o pin is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin. 2.3.6.3 port ad data direction register (ddrad) read: anytime. write: anytime. this register configures port pins pad[7:0] as either input or output. if a data direction bit is 0 (pin configured as input), then a read value on ptadx depends on the associated atddien1 bit. if the associated atddien1 bit is set to 1 (digital input buffer is enabled), a read on ptadx returns the value on port ad pin. if the associated atddien1 bit is set to 0 (digital input buffer is disabled), a read on ptadx returns a 1. 76543210 r ptiad7 ptiad6 ptiad5 ptiad4 ptiad3 ptiad2 ptiad1 ptiad0 w reset 1 1 1 11111 = reserved or unimplemented figure 2-20. port ad input register (ptiad) 76543210 r ddrad7 ddrad6 ddrad5 ddrad4 ddrad3 ddrad2 ddrad1 ddrad0 w reset 0 0 0 00000 figure 2-21. port ad data direction register (ddrad) table 2-15. ddrad field descriptions field description 7:0 ddrad[7:0] data direction port ad 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 88 freescale semiconductor 2.3.6.4 port ad reduced drive register (rdrad) read: anytime. write: anytime. this register configures the drive strength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduced drive register bit has no effect. 2.3.6.5 port ad pull device enable register (perad) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input pins. if a pin is configured as output, the corresponding pull device enable register bit has no effect. 76543210 r rdrad7 rdrad6 rdrad5 rdrad4 rdrad3 rdrad2 rdrad1 rdrad0 w reset 0 0 0 00000 figure 2-22. port ad reduced drive register (rdrad) table 2-16. rdrad field descriptions field description 7:0 rdrad[7:0] reduced drive port a 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r perad7 perad6 perad5 perad4 perad3 perad2 perad1 perad0 w reset 0 0 0 00000 figure 2-23. port ad pull device enable register (perad) table 2-17. perad field descriptions field description 7:0 perad[7:0] pull device enable port ad 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 89 2.3.6.6 port ad polarity select register (ppsad) read: anytime. write: anytime. the port ad polarity select register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled (peradx = 1). the port ad polarity select register is effective only when the corresponding data direction register bit is set to 0 (input). in pull-down mode (ppsadx = 1), a rising edge on a port ad pin sets the corresponding pifadx bit. in pull-up mode (ppsadx = 0), a falling edge on a port ad pin sets the corresponding pifadx bit. 2.3.6.7 port ad interrupt enable register (piead) read: anytime. write: anytime. this register disables or enables on a per pin basis the edge sensitive external interrupt associated with port ad. 76543210 r ppsad7 ppsad6 ppsad5 ppsad4 ppsad3 ppsad2 ppsad1 ppsad0 w reset 0 0 0 00000 figure 2-24. port ad polarity select register (ppsad) table 2-18. ppsad field descriptions field description 7:0 ppsad[7:0] polarity select port ad 0 a pull-up device is connected to the associated port ad pin, and detects falling edge for interrupt generation. 1 a pull-down device is connected to the associated port ad pin, and detects rising edge for interrupt generation. 76543210 r piead7 piead6 piead5 piead4 piead3 piead2 piead1 piead0 w reset 0 0 0 00000 figure 2-25. port ad interrupt enable register (piead) table 2-19. piead field descriptions field description 7:0 piead[7:0] interrupt enable port ad 0 interrupt is disabled (interrupt ?g masked). 1 interrupt is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 90 freescale semiconductor 2.3.6.8 port ad interrupt flag register (pifad) read: anytime. write: anytime. each flag is set by an active edge on the associated input pin. the active edge could be rising or falling based on the state of the corresponding ppsadx bit. to clear each flag, write ??to the corresponding pifadx bit. writing a ??has no effect. note if the atddien1 bit of the associated pin is set to 0 (digital input buffer is disabled), active edges can not be detected. 76543210 r pifad7 pifad6 pifad5 pifad4 pifad3 pifad2 pifad1 pifad0 w reset 0 0 0 00000 figure 2-26. port ad interrupt flag register (pifad) table 2-20. pifad field descriptions field description 7:0 pifad[7:0] interrupt flags port ad 0 no active edge pending. writing a ??has no effect. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). writing a ??clears the associated ?g. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 91 2.3.7 port l port l is associated with the analog-to-digital converter (atd) and the liquid crystal display (lcd) driver. if the atd module is enabled, the an[15:8] inputs of atd module are available on port l pins pl[7:0]. if the corresponding lcd frontplane drivers are enabled, the fp[31:28] and fp[19:16] outputs of lcd module are available on port l pins pl[7:0] and the general purpose i/os are disabled. for the pins of port l to be used as inputs, the corresponding lcd frontplane drivers must be disabled and the associated atddien0 register in the atd module must be set to 1 (digital input buffer is enabled). the atddien0 register does not affect the port l pins when they are configured as outputs. refer to the lcd block description chapter for information on enabling and disabling the lcd and its frontplane drivers. refer to the atd block description chapter for information on the atddien0 register. during reset, port l pins are configured as inputs with pull down. 2.3.7.1 port l i/o register (ptl) read: anytime. write: anytime. if the data direction bit of the associated i/o pin (ddrlx) is set to 1 (output), a write to the corresponding i/o register bit sets the value to be driven to the port l pin. if the data direction bit of the associated i/o pin (ddrlx) is set to 0 (input), a write to the corresponding i/o register bit takes place but has no effect on the port l pin. if the associated data direction bit (ddrlx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrlx) is set to 0 (input) and the associated atddien0 bits is set to 0 (digital input buffer is disabled), the associated i/o register bit (ptlx) reads ?? if the associated data direction bit (ddrlx) is set to 0 (input), the associated atddien0 bit is set to 1 (digital input buffer is enabled), and the lcd frontplane driver is enabled (and lcd module is enabled), the associated i/o register bit (ptlx) reads ?? if the associated data direction bit (ddrlx) is set to 0 (input), the associated atddien0 bit is set to 1 (digital input buffer is enabled), and the lcd frontplane driver is disabled (or lcd module is disabled), a read returns the value of the pin. 76543210 r ptl7 ptl6 ptl5 ptl4 ptl3 ptl2 ptl1 ptl0 w atd: an15 an14 an13 an12 an11 an10 an9 an8 lcd: 1 1 1 11111 reset 0 0 0 00000 figure 2-27. port l i/o register (ptl) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 92 freescale semiconductor 2.3.7.2 port l input register (ptil) read: anytime. write: never, writes to this register have no effect. if the lcd frontplane driver of an associated i/o pin is enabled (and lcd module is enabled) or the associated atddien0 bit is set to 0 (digital input buffer is disabled), a read returns a 1. if the lcd frontplane driver of an associated i/o pin is disabled (or lcd module is disabled) and the associated atddien0 bit is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin. 2.3.7.3 port l data direction register (ddrl) read: anytime. write: anytime. this register configures port pins pl[7:0] as either input or output. if a lcd frontplane driver is enabled (and lcd module is enabled), it outputs an analog signal to the corresponding pin and the associated data direction register bit has no effect. if a lcd frontplane driver is disabled (or lcd module is disabled), the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 76543210 r ptil7 ptil6 ptil5 ptil4 ptil3 ptil2 ptil1 ptil0 w reset 1 1 1 11111 = reserved or unimplemented figure 2-28. port l input register (ptil) 76543210 r ddrl7 ddrl6 ddrl5 ddrl4 ddrl3 ddrl2 ddrl1 ddrl0 w reset 0 0 0 00000 figure 2-29. port l data direction register (ddrl) table 2-21. ddrl field descriptions field description 7:0 ddrl[7:0] data direction port l 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 93 2.3.7.4 port l reduced drive register (rdrl) read: anytime. write: anytime. this register configures the drive strength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduced drive register bit has no effect. 2.3.7.5 port l pull device enable register (perl) read:anytime. write:anytime. this register configures whether a pull-up or a pull-down device is activated on configured input pins. if a pin is configured as output, the corresponding pull device enable register bit has no effect. 76543210 r rdrl7 rdrl6 rdrl5 rdrl4 rdrl3 rdrl2 rdrl1 rdrl0 w reset 0 0 0 00000 figure 2-30. port l reduced drive register (rdrl) table 2-22. rdrl field descriptions field description 7:0 rdrl[7:0] reduced drive port l 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r perl7 perl6 perl5 perl4 perl3 perl2 perl1 perl0 w reset 1 1 1 11111 figure 2-31. port l pull device enable register (perl) table 2-23. perl field descriptions field description 7:0 perl[7:0] pull device enable port l 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 94 freescale semiconductor 2.3.7.6 port l polarity select register (ppsl) read: anytime. write: anytime. the port l polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port l polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 2.3.7.7 port l slew rate register (srrl) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pl[7:0]. 76543210 r ppsl7 ppsl6 ppsl5 ppsl4 ppsl3 ppsl2 ppsl1 ppsl0 w reset 1 1 1 11111 figure 2-32. port l polarity select register (ppsl) table 2-24. ppsl field descriptions field description 7:0 ppsl[7:0] pull select port l 0 a pull-up device is connected to the associated port l pin. 1 a pull-down device is connected to the associated port l pin. 76543210 r srrl7 srrl6 srrl5 srrl4 srrl3 srrl2 srrl1 srrl0 w reset 0 0 0 00000 figure 2-33. port l slew rate register (srrl) table 2-25. srrl field descriptions field description 7:0 srrl[7:0] slew rate port l 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 95 2.3.8 port m port m is associated with the chip select 1 and the freescale? scalable controller area network (can1 and can0) modules. each pin is assigned to these modules according to the following priority: cs1/can1/can0 > general-purpose i/o. when the can1 module is enabled, pm[5:4] pins become txcan1 (transmitter) and rxcan1 (receiver) pins for the can1 module. when the can0 module is enabled, pm[3:2] pins become txcan0 (transmitter) and rxcan0 (receiver) pins for the can0 module. refer to the mscan block description chapter for information on enabling and disabling the can module. during reset, port m pins are configured as high-impedance inputs. 2.3.8.1 port m i/o register (ptm) read: anytime. write: anytime. if the associated data direction bit (ddrmx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrmx) is set to 0 (input), a read returns the value of the pin. 2.3.8.2 port m input register (ptim) read: anytime. write: never, writes to this register have no effect. this register always reads back the status of the associated pins. 76543210 r0 0 ptm5 ptm4 ptm3 ptm2 ptm1 0 w can0/can1: txcan1 rxcan1 txcan0 rxcan0 chip select: cs1 reset 0 0 000000 = reserved or unimplemented figure 2-34. port m i/o register (ptm) 76543210 r 0 0 ptim5 ptim4 ptim3 ptim2 ptim1 0 w reset 0 0 u uuuu0 = reserved or unimplemented u = unaffected by reset figure 2-35. port m input register (ptim) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 96 freescale semiconductor 2.3.8.3 port m data direction register (ddrm) read: anytime. write: anytime. this register configures port pins pm[5:1] as either input or output. when a can module is enabled, the corresponding transmitter (txcanx) pin becomes an output, the corresponding receiver (rxcanx) pin becomes an input, and the associated data direction register bits have no effect. if a can module is disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 2.3.8.4 port m reduced drive register (rdrm) read: anytime. write: anytime. this register configures the drive strength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduced drive register bit has no effect. 76543210 r0 0 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-36. port m data direction register (ddrm) table 2-26. ddrm field descriptions field description 5:1 ddrm[5:1] data direction port m 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 76543210 r0 0 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-37. port m reduced drive register (rdrm) table 2-27. rdrm field descriptions field description 5:1 rdrm[5:1] reduced drive port m 0 full drive strength at output 1 associated pin drives at about 1/3 of the full drive strength. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 97 2.3.8.5 port m pull device enable register (perm) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins. if a pin is configured as push-pull output, the corresponding pull device enable register bit has no effect. 2.3.8.6 port m polarity select register (ppsm) read: anytime. write: anytime. the port m polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port m polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. if a can module is enabled, a pull-up device can be activated on the receiver pin, and on the transmitter pin if the corresponding wired-or mode bit is set. pull-down devices can not be activated on can pins. 76543210 r0 0 perm5 perm4 perm3 perm2 perm1 0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-38. port m pull device enable register (perm) table 2-28. perm field descriptions field description 5:1 perm[5:1] pull device enable port m 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 76543210 r0 0 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-39. port m polarity select register (ppsm) table 2-29. ppsm field descriptions field description 5:1 ppsm[5:1] pull select port m 0 a pull-up device is connected to the associated port m pin. 1 a pull-down device is connected to the associated port m pin. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 98 freescale semiconductor 2.3.8.7 port m wired-or mode register (womm) read: anytime. write: anytime. this register selects whether a port m output is configured as push-pull or wired-or. when a wired-or mode register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. a wired-or mode register bit has no effect if the corresponding pin is configured as an input. these bits apply also to the can transmitter and allow a multipoint connection of several serial modules. 2.3.8.8 port m slew rate register (srrm) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pm[5:1]. 76543210 r0 0 womm5 womm4 womm3 womm2 womm1 0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-40. port m wired-or mode register (womm) table 2-30. womm field descriptions field description 5:1 womm[5:1] wired-or mode port m 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. 76543210 r0 0 srrm5 srrm4 srrm3 srrm2 srrm1 0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-41. port m slew rate register (srrm) table 2-31. srrm field descriptions field description 5:1 srrm[5:1] slew rate port m 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 99 2.3.9 port p port p is associated with the chip selects 0 and 2, the pulse width modulator (pwm), the serial communication interface (sci1) and the inter-ic bus (iic0 and iic1) modules. each pin is assigned to these modules according to the following priority: cs0/ cs2 > pwm > sci1/iic1/iic0 > general-purpose i/o. when a pwm channel is enabled, the corresponding pin becomes a pwm output with the exception of pp[5] which can be pwm input or output. refer to the pwm block description chapter for information on enabling and disabling the pwm channels. when the iic1 module is enabled and modrr1 is clear, pp[7:6] pins become scl1 and sda1 respectively as long as the corresponding pwm channels are disabled. when the iic0 module is enabled and modrr0 is clear, pp[5:4] pins become scl0 and sda0 respectively as long as the corresponding pwm channels are disabled. refer to the iic block description chapter for information on enabling and disabling the iic bus. when the sci1 receiver and transmitter are enabled and modrr2 is clear, the pp[2] and pp[0] pins become rxd1 and txd1 respectively as long as the corresponding pwm channels are disabled. refer to the sci block description chapter for information on enabling and disabling the sci receiver and transmitter. during reset, port p pins are configured as high-impedance inputs. 2.3.9.1 port p i/o register (ptp) read: anytime. write: anytime. if the associated data direction bit (ddrpx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrpx) is set to 0 (input), a read returns the value of the pin. the pwm function takes precedence over the general-purpose i/o function if the associated pwm channel is enabled. the pwm channels 6-0 are outputs if the respective channels are enabled. pwm channel 7 can be an output, or an input if the shutdown feature is enabled. 76543210 r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w sci1/ iic1/iic0: scl1 sda1 scl0 sda0 rxd1 txd1 pwm: pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 chip select: cs2 cs0 reset 0 0 0 00000 figure 2-42. port p i/o register (ptp) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 100 freescale semiconductor the iic function takes precedence over the general-purpose i/o function if the iic bus is enabled and the corresponding pwm channels remain disabled. the sda and scl pins are bidirectional with outputs configured as open-drain. if enabled, the sci1 transmitter takes precedence over the general-purpose i/o function, and the corresponding txd1 pin is configured as an output. if enabled, the sci1 receiver takes precedence over the general-purpose i/o function, and the corresponding rxd1 pin is configured as an input. 2.3.9.2 port p input register (ptip) read: anytime. write: never, writes to this register have no effect. this register always reads back the status of the associated pins. 2.3.9.3 port p data direction register (ddrp) read: anytime. write: anytime. this register configures port pins pp[7:0] as either input or output. if a pwm channel is enabled, the corresponding pin is forced to be an output and the associated data direction register bit has no effect. channel 5 can also force the corresponding pin to be an input if the shutdown feature is enabled. when an iic bus is enabled, the corresponding pins become the scl and sda bidirectional pins respectively as long as the corresponding pwm channels are disabled. the associated data direction register bits have no effect. when the sci1 transmitter is enabled, the pp[0] pin becomes the txd1 output pin and the associated data direction register bit has no effect. when the sci1 receiver is enabled, the pp[2] pin becomes the rxd1 input pin and the associated data direction register bit has no effect. 76543210 r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w reset u u u uuuuu = reserved or unimplemented u = unaffected by reset figure 2-43. port p i/o register (ptp) 76543210 r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w reset 0 0 0 00000 figure 2-44. port p data direction register (ddrp) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 101 if the pwm, iic0, iic1 and sci1 functions are disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 2.3.9.4 port p reduced drive register (rdrp) read:anytime. write:anytime. this register configures the drive strength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduced drive register bit has no effect. table 2-32. ddrp field descriptions field description 7:0 ddrp[7:0] data direction port p 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 76543210 r rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w reset 0 0 0 00000 figure 2-45. port p reduced drive register (rdrp) table 2-33. rdrp field descriptions field description 7:0 rdrp[7:0] reduced drive port p 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 102 freescale semiconductor 2.3.9.5 port p pull device enable register (perp) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. if a pin is configured as push-pull output, the corresponding pull device enable register bit has no effect. 2.3.9.6 port p polarity select register (ppsp) read: anytime. write: anytime. the port p polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port p polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. if an iic module is enabled, a pull-up device can be activated on either the scl or sda pins. pull-down devices can not be activated on iic pins. 76543210 r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w reset 0 0 0 00000 figure 2-46. port p pull device enable register (perp) table 2-34. perp field descriptions field description 7:0 perp[7:0] pull device enable port p 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 76543210 r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w reset 0 0 0 00000 figure 2-47. port p polarity select register (ppsp) table 2-35. ppsp field descriptions field description 7:0 ppsp[7:0] polarity select port p 0 a pull-up device is connected to the associated port p pin. 1 a pull-down device is connected to the associated port p pin. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 103 2.3.9.7 port p wired-or mode register (womp) read: anytime. write: anytime. this register selects whether a port p output is configured as push-pull or wired-or. when a wired-or mode register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. a wired-or mode register bit has no effect if the corresponding pin is configured as an input. if iic is enabled and the corresponding pwm channels are disabled, the pins are configured as wired-or and the corresponding wired-or mode register bits have no effect. 76543210 r womp7 womp6 womp5 womp4 0 womp2 0 wompo w reset 0 0 0 00000 = reserved or unimplemented figure 2-48. port p wired-or mode register (womp) table 2-36. womp field descriptions field description 7:4 womp[7:4] wired-or mode port p 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. 2 womp2 wired-or mode port p 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. 0 womp0 wired-or mode port p 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 104 freescale semiconductor 2.3.9.8 port p slew rate register (srrp) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pp[7:0]. 76543210 r srrp7 srrp6 srrp5 srrp4 srrp3 srrp2 srrp1 srrp0 w reset 0 0 0 00000 figure 2-49. port p slew rate register (srrp) table 2-37. srrp field descriptions field description 7:0 srrp[7:0] slew rate port p 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 105 2.3.10 port s port s is associated with the chip select 3, the serial peripheral interface (spi) and the serial communication interface (sci0). each pin is assigned to these modules according to the following priority: cs3 > spi/sci1/sci0 > general-purpose i/o. when the spi is enabled, the ps[7:4] pins become ss, sck, mosi, and miso respectively. refer to the spi block description chapter for information on enabling and disabling the spi. when the sci0 receiver and transmitter are enabled, the ps[1:0] pins become txd0 and rxd0 respectively. when the sci1 receiver and transmitter are enabled and modrr2 is set, the ps[3:2] pins become txd1 and rxd1 respectively. refer to the sci block description chapter for information on enabling and disabling the sci receiver and transmitter. during reset, port s pins are configured as high-impedance inputs. 2.3.10.1 port s i/o register (pts) read: anytime. write: anytime. if the associated data direction bit (ddrsx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrsx) is set to 0 (input), a read returns the value of the pin. the spi function takes precedence over the general-purpose i/o function if the spi is enabled. if enabled, the sci0(1) transmitter takes precedence over the general-purpose i/o function, and the corresponding txd0(1) pin is configured as an output. if enabled, the sci0(1) receiver takes precedence over the general-purpose i/o function, and the corresponding rxd0(1) pin is configured as an input. 76543210 r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w spi/ sci1/sci0: ss sck mosi miso txd1 rxd1 txd0 rxd0 chip select: cs3 reset 0 0 0 00000 = reserved or unimplemented figure 2-50. port s i/o register (pts) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 106 freescale semiconductor 2.3.10.2 port s input register (ptis) read: anytime. write: never, writes to this register have no effect. this register always reads back the status of the associated pins. 2.3.10.3 port s data direction register (ddrs) read: anytime. write: anytime. this register configures port pins ps[7:0] as either input or output. when the spi is enabled, the ps[7:4] pins become the spi bidirectional pins. the associated data direction register bits have no effect. when the sci1 transmitter is enabled, the ps[3] pin becomes the txd1 output pin and the associated data direction register bit has no effect. when the sci1 receiver is enabled, the ps[2] pin becomes the rxd1 input pin and the associated data direction register bit has no effect. when the sci0 transmitter is enabled, the ps[1] pin becomes the txd0 output pin and the associated data direction register bit has no effect. when the sci0 receiver is enabled, the ps[0] pin becomes the rxd0 input pin and the associated data direction register bit has no effect. if the spi, sci1 and sci0 functions are disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. 76543210 r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w reset u u u uuuuu = reserved or unimplemented u = unaffected by reset figure 2-51. port s input register (ptis) 76543210 r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w reset 0 0 0 00000 figure 2-52. port s data direction register (ddrs) table 2-38. ddrs field descriptions field description 7:0 ddrs[7:0] data direction port s 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 107 2.3.10.4 port s reduced drive register (rdrs) read: anytime. write: anytime. this register configures the drive strength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduced drive register bit has no effect. 2.3.10.5 port s pull device enable register (pers) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. if a pin is configured as push-pull output, the corresponding pull device enable register bit has no effect. 76543210 r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w reset 0 0 0 00000 figure 2-53. port s reduced drive register (rdrs) table 2-39. rdrs field descriptions field description 7:0 rdrs[7:0] reduced drive port s 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 76543210 r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w reset 0 0 0 00000 figure 2-54. port s pull device enable register (pers) table 2-40. pers field descriptions field description 7:0 pers[7:0] pull device enable port s 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 108 freescale semiconductor 2.3.10.6 port s polarity select register (ppss) read: anytime. write: anytime. the port s polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port s polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 2.3.10.7 port s wired-or mode register (woms) read: anytime. write: anytime. this register selects whether a port s output is configured as push-pull or wired-or. when a wired-or mode register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. a wired-or mode register bit has no effect if the corresponding pin is configured as an input. 76543210 r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w reset 0 0 0 00000 figure 2-55. port s polarity select register (ppss) table 2-41. ppss field descriptions field description 7:0 ppss[7:0] pull select port s 0 a pull-up device is connected to the associated port s pin. 1 a pull-down device is connected to the associated port s pin. 76543210 r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w reset 0 0 0 00000 figure 2-56. port s wired-or mode register (woms) table 2-42. woms field descriptions field description 7:0 woms[7:0] wired-or mode port s 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 109 2.3.10.8 port s slew rate register (srrs) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins ps[7:0]. 76543210 r srrs7 srrs6 srrs5 srrs4 srrs3 srrs2 srrs1 srrs0 w reset 0 0 0 00000 figure 2-57. port s slew rate register (srrs) table 2-43. srrs field descriptions field description 7:0 srrs[7:0] slew rate port s 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 110 freescale semiconductor 2.3.11 port t port t is associated with the 8-channel enhanced capture timer (ect), the inter-ic (iic0 and iic1) modules and the liquid crystal display (lcd) driver. each pin is assigned to these modules according to the following priority: lcd driver > iic1/iic0 > ect > general-purpose i/o. when the iic1 module is enabled and modrr1 is set, pt[7:6] pins become scl1 and sda1 pins respectively. when the iic0 module is enabled and modrr0 is set, pt[5:4] pins become scl0 and sda0 respectively. refer to the iic block description chapter for information on enabling and disabling the iic bus. if the corresponding lcd frontplane drivers are enabled (and lcd module is enabled), the fp[27:24] outputs of the lcd module are available on port t pins pt[3:0]. if the corresponding lcd frontplane drivers are disabled (or lcd module is disabled) and the ect is enabled, the timer channels configured for output compare are available on port t pins pt[3:0]. refer to the lcd block description chapter for information on enabling and disabling the lcd and its frontplane drivers.refer to the ect block description chapter for information on enabling and disabling the ect module. during reset, port t pins are configured as inputs with pull down. 2.3.11.1 port t i/o register (ptt) read: anytime. write: anytime. if the associated data direction bit (ddrtx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrtx) is set to 0 (input) and the lcd frontplane driver is enabled (and lcd module is enabled), the associated i/o register bit (pttx) reads ?? if the associated data direction bit (ddrtx) is set to 0 (input) and the lcd frontplane driver is disabled (or lcd module is disabled), a read returns the value of the pin. 76543210 r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w ect: oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 iic1/iic0: scl1 sda1 scl0 sda0 lcd: 1111 reset 0 0 0 00000 figure 2-58. port t i/o register (ptt) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 111 2.3.11.2 port t input register (ptit) read: anytime. write: never, writes to this register have no effect. if the lcd frontplane driver of an associated i/o pin is enabled (and lcd module is enabled), a read returns a 1. if the lcd frontplane driver of the associated i/o pin is disabled (or lcd module is disabled), a read returns the status of the associated pin. 2.3.11.3 port t data direction register (ddrt) read: anytime. write: anytime. this register configures port pins pt[7:0] as either input or output. if a lcd frontplane driver is enabled (and lcd module is enabled), it outputs an analog signal to the corresponding pin and the associated data direction register bit has no effect. if a lcd frontplane driver is disabled (or lcd module is disabled), the corresponding data direction register bit reverts to control the i/o direction of the associated pin. if the ect module is enabled, each port pin configured for output compare is forced to be an output and the associated data direction register bit has no effect. if the associated timer output compare is disabled, the corresponding data direction register bit reverts to control the i/o direction of the associated pin. if the ect module is enabled, each port pin configured as an input capture has the corresponding data direction register bit controlling the i/o direction of the associated pin. 76543210 r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w reset u u u uuuuu = reserved or unimplemented u = unaffected by reset figure 2-59. port t input register (ptit) 76543210 r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w reset 0 0 0 00000 figure 2-60. port t data direction register (ddrt) table 2-44. ddrt field descriptions field description 7:0 ddrt[7:0] data direction port t 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 112 freescale semiconductor 2.3.11.4 port t reduced drive register (rdrt) read: anytime. write: anytime. this register configures the drive strength of configured output pins as either full or reduced. if a pin is configured as input, the corresponding reduced drive register bit has no effect. 76543210 r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w reset 0 0 0 00000 figure 2-61. port t reduced drive register (rdrt) table 2-45. rdrt field descriptions field description 7:0 rdrt[7:0] reduced drive port t 0 full drive strength at output. 1 associated pin drives at about 1/3 of the full drive strength. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 113 2.3.11.5 port t pull device enable register (pert) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input pins. if a pin is configured as output, the corresponding pull device enable register bit has no effect. for port pins pt[7:4], a pull-up device can be activated on wired-or (open drain) output pins. if the pin is configured as push-pull output, the corresponding pull device enable register bit has no effect. 2.3.11.6 port t polarity select register (ppst) read: anytime. write: anytime. the port t polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port t polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. if an iic module is enabled, a pull-up device can be activated on either the scl or sda pins. pull-down devices can not be activated on iic pins. 76543210 r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w reset 0 0 0 01111 figure 2-62. port t pull device enable register (pert) table 2-46. pert field descriptions field description 7:0 pert[7:0] pull device enable port t 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 76543210 r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w reset 0 0 0 01111 figure 2-63. port t polarity select register (ppst) table 2-47. ppst field descriptions field description 7:0 ppst[7:0] pull select port t 0 a pull-up device is connected to the associated port t pin. 1 a pull-down device is connected to the associated port t pin. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 114 freescale semiconductor 2.3.11.7 port t wired-or mode register (womt) read: anytime. write: anytime. this register selects whether a port t output is configured as push-pull or wired-or. when a wired-or mode register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. a wired-or mode register bit has no effect if the corresponding pin is configured as an input. if iic is enabled, the pins are configured as wired-or and the corresponding wired-or mode register bits have no effect. this register also configures the re-routing of iic0, iic1 and sci1 on alternative ports. 76543210 r womt7 womt6 womt5 womt4 0 modrr2 modrr1 modrr0 w reset 0 0 0 00000 = reserved or unimplemented figure 2-64. port t wired-or mode register (womt) table 2-48. womt field descriptions field description 7:4 womt[7:4] wired-or mode port t 0 output buffers operate as push-pull outputs. 1 output buffers operate as open-drain outputs. 2 modrr2 sci1 routing bit ?see table 2-49 .. 1 modrr1 iic1 routing bit ?see table 2-50 .. 0 modrr0 iic0 routing bit ?see table 2-51 .. table 2-49. sci1 routing modrr[2] txd1 rxd1 0 pp0 pp2 1 ps3 ps2 table 2-50. iic1 routing modrr[1] sda1 scl1 0 pp6 pp7 1 pt6 pt7 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 115 2.3.11.8 port t slew rate register (srrt) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pt[7:0]. table 2-51. iic0 routing modrr[0] sda0 scl0 0 pp4 pp5 1 pt4 pt5 76543210 r srrt7 srrt6 srrt5 srrt4 srrt3 srrt2 srrt1 srrt0 w reset 0 0 0 00000 figure 2-65. port t slew rate register (srrt) table 2-52. srrt field descriptions field description 7:0 srrt[7:0] slew rate port t 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 116 freescale semiconductor 2.3.12 port u port u is associated with the stepper stall detect (ssd1 and ssd0) and motor controller (mc1 and mc0) modules. each pin is assigned to these modules according to the following priority: ssd1/ssd0 > mc1/mc0 > general-purpose i/o. if ssd1 module is enabled, the pu[7:4] pins are controlled by the ssd1 module. if ssd1 module is disabled, the pu[7:4] pins are controlled by the motor control pwm channels 3 and 2 (mc1). if ssd0 module is enabled, the pu[3:0] pins are controlled by the ssd0 module. if ssd0 module is disabled, the pu[3:0] pins are controlled by the motor control pwm channels 1 and 0 (mc0). refer to the ssd and mc block description chapters for information on enabling and disabling the ssd module and the motor control pwm channels respectively. during reset, port u pins are configured as high-impedance inputs. 2.3.12.1 port u i/o register (ptu) read: anytime. write: anytime. if the associated data direction bit (ddrux) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrux) is set to 0 (input) and the slew rate is enabled, the associated i/o register bit (ptux) reads ?? if the associated data direction bit (ddrux) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. 76543210 r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w mc: m1c1p m1c1m m1cop m1com m0c1p m0c1m m0c0p m0c0m ssd1/ ssd0: m1sinp m1sinm m1cosp m1cosm m0sinp m0sinm m1cosp m0cosm reset 0 0 0 00000 figure 2-66. port u i/o register (ptu) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 117 2.3.12.2 port u input register (ptiu) read: anytime. write: never, writes to this register have no effect. if the associated slew rate control is enabled (digital input buffer is disabled), a read returns a ?? if the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin. 2.3.12.3 port u data direction register (ddru) read: anytime. write: anytime. this register configures port pins pu[7:0] as either input or output. when enabled, the ssd or mc modules force the i/o state to be an output for each associated pin and the associated data direction register bit has no effect. if the ssd and mc modules are disabled, the corresponding data direction register bits revert to control the i/o direction of the associated pins. 76543210 r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w reset u u u uuuuu = reserved or unimplemented u = unaffected by reset figure 2-67. port u input register (ptiu) 76543210 r ddru7 ddru6 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 w reset 0 0 0 00000 figure 2-68. port u data direction register (ddru) table 2-53. ddru field descriptions field description 7:0 ddru[7:0] data direction port u 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 118 freescale semiconductor 2.3.12.4 port u slew rate register (srru) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pu[7:0]. 2.3.12.5 port u pull device enable register (peru) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input pins. if a pin is configured as output, the corresponding pull device enable register bit has no effect. 76543210 r srru7 srru6 srru5 srru4 srru3 srru2 srru1 srru0 w reset 0 0 0 00000 figure 2-69. port u slew rate register (srru) table 2-54. srru field descriptions field description 7:0 srru[7:0] slew rate port u 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 76543210 r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w reset 0 0 0 00000 figure 2-70. port u pull device enable register (peru) table 2-55. peru field descriptions field description 7:0 peru[7:0] pull device enable port u 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 119 2.3.12.6 port u polarity select register (ppsu) read: anytime. write: anytime. the port u polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port u polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 w reset 0 0 0 00000 figure 2-71. port u polarity select register (ppsu) table 2-56. ppsu field descriptions field description 7:0 ppsu[7:0] pull select port u 0 a pull-up device is connected to the associated port u pin. 1 a pull-down device is connected to the associated port u pin. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 120 freescale semiconductor 2.3.13 port v port v is associated with the stepper stall detect (ssd3 and ssd2) and motor controller (mc3 and mc2) modules. each pin is assigned to these modules according to the following priority: ssd3/ssd2 > mc3/mc2 > general-purpose i/o. if ssd3 module is enabled, the pv[7:4] pins are controlled by the ssd3 module. if ssd3 module is disabled, the pv[7:4] pins are controlled by the motor control pwm channels 7 and 6 (mc3). if ssd2 module is enabled, the pv[3:0] pins are controlled by the ssd2 module. if ssd2 module is disabled, the pv[3:0] pins are controlled by the motor control pwm channels 5 and 4 (mc2). refer to the ssd and mc block description chapters for information on enabling and disabling the ssd module and the motor control pwm channels respectively. during reset, port v pins are configured as high-impedance inputs. 2.3.13.1 port v i/o register (ptv) read: anytime. write: anytime. if the associated data direction bit (ddrvx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrvx) is set to 0 (input) and the slew rate is enabled, the associated i/o register bit (ptvx) reads ?? if the associated data direction bit (ddrvx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. 76543210 r ptv7 ptv6 ptv5 ptv4 ptv3 ptv2 ptv1 ptv0 w mc: m3c1p m3c1m m3c0p m3c0m m2c1p m2c1m m2c0p m2c0m ssd3/ ssd2 m3sinp m3sinm m3cosp m3cosm m2sinp m2sinm m2cosp m2cosm reset 0 0 0 00000 figure 2-72. port v i/o register (ptv) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 121 2.3.13.2 port v input register (ptiv) read: anytime. write: never, writes to this register have no effect. if the associated slew rate control is enabled (digital input buffer is disabled), a read returns a ?? if the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin. 2.3.13.3 port v data direction register (ddrv) read: anytime. write: anytime. this register configures port pins pv[7:0] as either input or output. when enabled, the ssd or mc modules force the i/o state to be an output for each associated pin and the associated data direction register bit has no effect. if the ssd and mc modules are disabled, the corresponding data direction register bits revert to control the i/o direction of the associated pins. 76543210 r ptiv7 ptiv6 ptiv5 ptiv4 ptiv3 ptiv2 ptiv1 ptiv0 w reset u u u uuuuu = reserved or unimplemented u = unaffected by reset figure 2-73. port v input register (ptiv) 76543210 r ddrv7 ddrv6 ddrv5 ddrv4 ddrv3 ddrv2 ddrv1 ddrv0 w reset 0 0 0 00000 figure 2-74. port v data direction register (ddrv) table 2-57. ddrv field descriptions field description 7:0 ddrv[7:0] data direction port v 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 122 freescale semiconductor 2.3.13.4 port v slew rate register (srrv) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pv[7:0]. 2.3.13.5 port v pull device enable register (perv) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input pins. if a pin is configured as output, the corresponding pull device enable register bit has no effect. 76543210 r srrv7 srrv6 srrv5 srrv4 srrv3 srrv2 srrv1 srrv0 w reset 0 0 0 00000 figure 2-75. port v slew rate register (srrv) table 2-58. srrv field descriptions field description 7:0 srrv[7:0] slew rate port v 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 76543210 r perv7 perv6 perv5 perv4 perv3 perv2 perv1 perv0 w reset 0 0 0 00000 figure 2-76. port v pull device enable register (perv) table 2-59. perv field descriptions field description 7:0 perv[7:0] pull device enable port v 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 123 2.3.13.6 port v polarity select register (ppsv) read: anytime. write: anytime. the port v polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port v polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r ppsv7 ppsv6 ppsv5 ppsv4 ppsv3 ppsv2 ppsv1 ppsv0 w reset 0 0 0 00000 figure 2-77. port v polarity select register (ppsv) table 2-60. ppsv field descriptions field description 7:0 ppsv[7:0] pull select port v 0 a pull-up device is connected to the associated port v pin. 1 a pull-down device is connected to the associated port v pin. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 124 freescale semiconductor 2.3.14 port w port w is associated with the stepper stall detect (ssd5 and ssd4) and motor controller (mc5 and mc4) modules. each pin is assigned to these modules according to the following priority: ssd5/ssd4 > mc5/mc4 > general-purpose i/o. if ssd5 module is enabled, the pw[7:4] pins are controlled by the ssd5 module. if ssd5 module is disabled, the pw[7:4] pins are controlled by the motor control pwm channels 11 and 10 (mc5). if ssd4 module is enabled, the pw[3:0] pins are controlled by the ssd4 module. if ssd4 module is disabled, the pw[3:0] pins are controlled by the motor control pwm channels 9 and 8 (mc4). refer to the ssd and mc block description chapters for information on enabling and disabling the ssd module and the motor control pwm channels respectively. during reset, port w pins are configured as high-impedance inputs. 2.3.14.1 port w i/o register (ptw) read: anytime. write: anytime. if the associated data direction bit (ddrwx) is set to 1 (output), a read returns the value of the i/o register bit. if the associated data direction bit (ddrwx) is set to 0 (input) and the slew rate is enabled, the associated i/o register bit (ptwx) reads ?? if the associated data direction bit (ddrwx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. 76543210 r ptw7 ptw6 ptw5 ptw4 ptw3 ptw2 ptw1 ptw0 w mc: m5c1p m3c1m m5c0p m5c0m m4c1p m4c1m m4c0p m4c0m ssd5/ ssd4 m5sinp m3sinm m5cosp m5cosm m4sinp m4sinm m4cosp m4cosm reset 0 0 0 00000 figure 2-78. port w i/o register (ptw) 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 125 2.3.14.2 port w input register (ptiw) read: anytime. write: never, writes to this register have no effect. if the associated slew rate control is enabled (digital input buffer is disabled), a read returns a ?? if the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin. 2.3.14.3 port w data direction register (ddrw) read: anytime. write: anytime. this register configures port pins pw[7:0] as either input or output. when enabled, the ssd or mc modules force the i/o state to be an output for each associated pin and the associated data direction register bit has no effect. if the ssd and mc modules are disabled, the corresponding data direction register bits revert to control the i/o direction of the associated pins. 76543210 r ptiw7 ptiw6 ptiw5 ptiw4 ptiw3 ptiw2 ptiw1 ptiw0 w reset u u u uuuuu = reserved or unimplemented u = unaffected by reset figure 2-79. port w input register (ptiw) 76543210 r ddrw7 ddrw6 ddrw5 ddrw4 ddrw3 ddrw2 ddrw1 ddrw0 w reset 0 0 0 00000 figure 2-80. port w data direction register (ddrw) table 2-61. ddrw field descriptions field description 7:0 ddrw[7:0] data direction port w 0 associated pin is con?ured as input. 1 associated pin is con?ured as output. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 126 freescale semiconductor 2.3.14.4 port w slew rate register (srrw) read: anytime. write: anytime. this register enables the slew rate control and disables the digital input buffer for port pins pw[7:0]. 2.3.14.5 port w pull device enable register (perw) read: anytime. write: anytime. this register configures whether a pull-up or a pull-down device is activated on configured input pins. if a pin is configured as output, the corresponding pull device enable register bit has no effect. 76543210 r srrw7 srrw6 srrw5 srrw4 srrw3 srrw2 srrw1 srrw0 w reset 0 0 0 00000 figure 2-81. port w slew rate register (srrw) table 2-62. srrw field descriptions field description 7:0 srrw[7:0] slew rate port w 0 disables slew rate control and enables digital input buffer. 1 enables slew rate control and disables digital input buffer. 76543210 r perw7 perw6 perw5 perw4 perw3 perw2 perw1 perw0 w reset 0 0 0 00000 figure 2-82. port w pull device enable register (perw) table 2-63. perw field descriptions field description 7:0 perw[7:0] pull device enable port w 0 pull-up or pull-down device is disabled. 1 pull-up or pull-down device is enabled. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 127 2.3.14.6 port w polarity select register (ppsw) read: anytime. write: anytime. the port w polarity select register selects whether a pull-down or a pull-up device is connected to the pin. the port w polarity select register is effective only when the corresponding data direction register bit is set to 0 (input) and the corresponding pull device enable register bit is set to 1. 76543210 r ppsw7 ppsw6 ppsw5 ppsw4 ppsw3 ppsw2 ppsw1 ppsw0 w reset 0 0 0 00000 figure 2-83. port w polarity select register (ppsw) table 2-64. ppsw field descriptions field description 7:0 ppsw[7:0] pull select port w 0 a pull-up device is connected to the associated port w pin. 1 a pull-down device is connected to the associated port w pin. 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 128 freescale semiconductor 2.4 functional description each pin except pe0, pe1, and bkgd can act as general-purpose i/o. in addition the pin can act as an output from a peripheral module or an input to a peripheral module. a set of configuration registers is common to all ports. all registers can be written at any time, however a specific configuration might not become active. example: selecting a pull-up resistor. this resistor does not become active while the port is used as a push-pull output. 2.4.1 i/o register the i/o register holds the value driven out to the pin if the port is used as a general-purpose i/o. writing to the i/o register only has an effect on the pin if the port is used as general-purpose output. when reading the i/o register, the value of each pin is returned if the corresponding data direction register bit is set to 0 (pin configured as input). if the data direction register bits is set to 1, the content of the i/o register bit is returned. this is independent of any other configuration ( figure 2-84 ). due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the i/o register when changing the data direction register. 2.4.2 input register the input register is a read-only register and generally returns the value of the pin ( figure 2-84 ).it can be used to detect overload or short circuit conditions. table 2-65. register availability per port 1 1 each cell represents one register with individual con?uration bits port data data direction input reduced drive pull enable polarity select wired-or mode slew rate interrupt enable interrupt flag a yes yes yes yes yes byesyes cyesyes dyesyes eyesyes kyesyes ad yes yes yes yes yes yes yes yes l yes yes yes yes yes yes yes m yes yes yes yes yes yes yes yes p yes yes yes yes yes yes yes yes s yes yes yes yes yes yes yes yes t yes yes yes yes yes yes yes yes u yes yes yes yes yes yes v yes yes yes yes yes yes w yes yes yes yes yes yes 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 129 due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the input register when changing the data direction register. 2.4.3 data direction register the data direction register defines whether the pin is used as an input or an output. . a data direction register bit set to 0 configures the pin as an input. a data direction register bit set to 1 configures the pin as an output. if a peripheral module controls the pin the contents of the data direction register is ignored ( figure 2-84 ). figure 2-84. illustration of i/o pin functionality figure 2-85 shows the state of digital inputs and outputs when an analog module drives the port. when the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read ??. figure 2-85. digital ports and analog module ptx ddrx output enable module enable 1 0 1 1 0 0 pad ptix data out digital module analog module 1 0 1 pad digital input digital output 1 0 analog module enable output pim boundary 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 130 freescale semiconductor 2.4.4 reduced drive register if the port is used as an output the reduced drive register allows the configuration of the drive strength. 2.4.5 pull device enable register the pull device enable register turns on a pull-up or pull-down device. the pull device becomes active only if the pin is used as an input or as a wired-or output. 2.4.6 polarity select register the polarity select register selects either a pull-up or pull-down device if enabled. the pull device becomes active only if the pin is used as an input or as a wired-or output. 2.4.7 pin con?uration summary the following table summarizes the effect of various configuration in the data direction (ddr), input/output (i/o), reduced drive (rdr), pull enable (pe), pull select (ps) and interrupt enable (ie) register bits. the ps configuration bit is used for two purposes: 1. con?ure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. select either a pull-up or pull-down device if pe is set to ?? table 2-66. pin con?uration summary ddr io rdr pe ps ie 1 1 applicable only on port ad. function 2 2 digital outputs are disabled and digital input logic is forced to ? when an analog module associated with the port is enabled. pull device interrupt 0 x x 0 x 0 input disabled disabled 0 x x 1 0 0 input pull up disabled 0 x x 1 1 0 input pull down disabled 0 x x 0 0 1 input disabled falling edge 0 x x 0 1 1 input disabled rising edge 0 x x 1 0 1 input pull up falling edge 0 x x 1 1 1 input pull down rising edge 1 0 0 x x 0 output to 0, full drive disabled disabled 1 1 0 x x 0 output to 1, full drive disabled disabled 1 0 1 x x 0 output to 0, reduced drive disabled disabled 1 1 1 x x 0 output to 1, reduced drive disabled disabled 1 0 0 x 0 1 output to 0, full drive disabled falling edge 1 1 0 x 1 1 output to 1, full drive disabled rising edge 1 0 1 x 0 1 output to 0, reduced drive disabled falling edge 1 1 1 x 1 1 output to 1, reduced drive disabled rising edge 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 131 2.5 resets the reset values of all registers are given in the register description in section 2.3, ?emory map and register definition . all ports start up as general-purpose inputs on reset. 2.5.1 reset initialization all registers including the data registers get set/reset asynchronously. table 2-67 summarizes the port properties after reset initialization. p table 2-67. port reset state summary port reset states data direction pull mode reduced drive slew rate wired-or mode interrupt a input pull down disabled disabled n/a n/a b input pull down disabled disabled n/a n/a c input hi-z disabled disabled n/a n/a d input hi-z disabled disabled n/a n/a e input pull down 1 1 pe[1:0] pins have pull-ups instead of pull-downs. disabled disabled n/a n/a k input pull down disabled disabled n/a n/a ad input hi-z disabled n/a n/a disabled l input pull down disabled disabled n/a n/a m input hi-z disabled disabled disabled n/a p input hi-z disabled disabled disabled n/a s input hi-z disabled disabled disabled n/a t[7:4] input hi-z disabled disabled disabled n/a t[3:0] input pull down disabled disabled disabled n/a u input hi-z disabled disabled n/a n/a v input hi-z disabled disabled n/a n/a w input hi-z disabled disabled n/a n/a 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 132 freescale semiconductor 2.6 interrupts 2.6.1 general port ad generates an edge sensitive interrupt if enabled. it offers eight i/o pins with edge triggered interrupt capability in wired-or fashion. the interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. all eight bits/pins share the same interrupt vector. interrupts can be used with the pins configured as inputs (with the corresponding atddien1 bit set to 1)or outputs. an interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. this external interrupt feature is capable to wake up the cpu when it is in stop or wait mode. a digital filter on each pin prevents pulses ( figure 2-87 ) shorter than a specified time from generating an interrupt. the minimum time varies over process conditions, temperature and voltage ( figure 2-86 and table 2-68 ). figure 2-86. interrupt glitch filter on port ad (pps = 0) table 2-68. pulse detection criteria pulse mode st op stop 1 1 these values include the spread of the oscillator frequency over temperature, voltage and process. unit unit ignored t pulse <= 3 bus clock t pulse <= 3.2 s uncertain 3 < t pulse < 4 bus clock 3.2 < t pulse < 10 s valid t pulse >= 4 bus clock t pulse >= 10 s glitch, ?tered out, no interrupt ?g set valid pulse, interrupt ?g set t ifmin t ifmax 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 133 figure 2-87. pulse illustration a valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly the filters are continuously clocked by the bus clock in run and wait mode. in stop mode the clock is generated by a single rc oscillator in the port integration module. to maximize current saving the rc oscillator runs only if the following condition is true on any pin:sample count <= 4 and port interrupt enabled (pie=1) and port interrupt flag not set (pif=0). 2.6.2 interrupt sources note vector addresses and their relative interrupt priority are determined at the mcu level. 2.6.3 operation in stop mode all clocks are stopped in stop mode. the port integration module has asynchronous paths on port ad to generate wake-up interrupts from stop mode. for other sources of external interrupts refer to the respective block description chapters. table 2-69. port integration module interrupt sources interrupt source interrupt flag local enable global (ccr) mask port ad pifad[7:0] piead[7:0] i bit t pulse 4 .com u datasheet
chapter 2 port integration module (s12xhzpimv1) MC9S12XHZ512 data sheet, rev. 1.02 134 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 135 chapter 3 512 kbyte flash module (s12xftx512k4v3) 3.1 introduction this document describes the ftx512k4 module that includes a 512k kbyte flash (nonvolatile) memory. the flash memory may be read as either bytes, aligned words or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. the flash memory is ideal for program and data storage for single-supply applications allowing for ?ld reprogramming without requiring external voltage sources for program or erase. program and erase functions are controlled by a command driven interface. the flash module supports both block erase and sector erase. an erased bit reads 1 and a programmed bit reads 0. the high voltage required to program and erase the flash memory is generated internally. it is not possible to read from a flash block while it is being erased or programmed. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. 3.1.1 glossary command write sequence ?a three-step mcu instruction sequence to execute built-in algorithms (including program and erase) on the flash memory. multiple-input signature register (misr) ?a multiple-input signature register is an output response analyzer implemented using a linear feedback shift-register (lfsr). a 16-bit misr is used to compress data and generate a signature that is particular to the data read from a flash block. 3.1.2 features 512 kbytes of flash memory comprised of four 128 kbyte blocks with each block divided into 128 sectors of 1024 bytes automated program and erase algorithm interrupts on flash command completion, command buffer empty fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times sector erase abort feature for critical interrupt response flexible protection scheme to prevent accidental program or erase single power supply for all flash operations including program and erase 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 136 freescale semiconductor security feature to prevent unauthorized access to the flash memory code integrity check using built-in data compression 3.1.3 modes of operation program, erase, erase verify, and data compress operations (please refer to section 3.4.1, ?lash command operations for details). 3.1.4 block diagram a block diagram of the flash module is shown in figure 3-1 . 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 137 figure 3-1. ftx512k4 block diagram 3.2 external signal description the flash module contains no signals that connect off-chip. ftx512k4 flash block 0 64k * 16 bits flash block 1 64k * 16 bits flash block 2 64k * 16 bits 64k * 16 bits flash block 3 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 oscillator clock divider clock command interrupt request fclk protection security command pipeline cmd2 addr2 data2_0 cmd1 addr1 data1_0 registers data2_1 data1_1 data2_2 data1_2 data2_3 data1_3 flash interface 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 138 freescale semiconductor 3.3 memory map and register de?ition this section describes the memory map and registers for the flash module. 3.3.1 module memory map the flash memory map is shown in figure 3-2 . the hcs12x architecture places the flash memory addresses between global addresses 0x78_0000 and 0x7f_ffff. the fprot register, described in section 3.3.2.5, ?lash protection register (fprot) , can be set to protect regions in the flash memory from accidental program or erase. three separate memory regions, one growing upward from global address 0x7f_8000 in the flash memory (called the lower region), one growing downward from global address 0x7f_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection. the flash memory addresses covered by these protectable regions are shown in the flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. the lower address region can be used for eeprom emulation in an mcu without an eeprom module since it can be left unprotected while the remaining addresses are protected from program or erase. default protection settings as well as security information that allows the mcu to restrict access to the flash module are stored in the flash con?uration ?ld as described in table 3-1 . table 3-1. flash con?uration field global address size ( b ytes) description 0x7f_ff00 ?0x7f_ff07 8 backdoor comparison key refer to section 3.6.1, ?nsecuring the mcu using backdoor key access 0x7f_ff08 ?0x7f_ff0c 5 reserved 0x7f_ff0d 1 flash protection byte refer to section 3.3.2.5, ?lash protection register (fprot) 0x7f_ff0e 1 flash nonvolatile byte refer to section 3.3.2.8, ?lash control register (fctl) 0x7f_ff0f 1 flash security byte refer to section 3.3.2.2, ?lash security register (fsec) 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 139 figure 3-2. flash memory map flash registers flash con?uration field 0x7f_c000 flash protected/unprotected lower region 1, 2, 4, 8 kbytes 0x7f_8000 0x7f_9000 0x7f_8400 0x7f_8800 0x7f_a000 flash end = 0x7f_ffff 0x7f_f800 0x7f_f000 0x7f_e000 flash protected/unprotected higher region 2, 4, 8, 16 kbytes flash protected/unprotected region 8 kbytes (up to 29 kbytes) 16 bytes 16 bytes (0x7f_ff00 - 0x7f_ff0f) flash protected/unprotected region 480 kbytes flash start = 0x78_0000 module base + 0x0000 module base + 0x000f 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 140 freescale semiconductor the flash module also contains a set of 16 control and status registers located between module base + 0x0000 and 0x000f. a summary of the flash module registers is given in table 3-2 while their accessibility is detailed in section 3.3.2, ?egister descriptions . table 3-2. flash register map module base + register name normal mode access 0x0000 flash clock divider register (fclkdiv) r/w 0x0001 flash security register (fsec) r 0x0002 flash test mode register (ftstmod) r/w 0x0003 flash con?uration register (fcnfg) r/w 0x0004 flash protection register (fprot) r/w 0x0005 flash status register (fstat) r/w 0x0006 flash command register (fcmd) r/w 0x0007 flash control register (fctl) r 0x0008 flash high address register (faddrhi) 1 r 0x0009 flash low address register (faddrlo) 1 r 0x000a flash high data register (fdatahi) r 0x000b flash low data register (fdatalo) r 0x000c reserved1 1 r 0x000d reserved2 1 r 0x000e reserved3 1 r 0x000f reserved4 1 1 intended for factory test purposes only. r 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 141 3.3.2 register descriptions register name bit 7 6 5 4 3 2 1 bit 0 fclkdiv r fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w fsec r keyen rnv5 rnv4 rnv3 rnv2 sec w ftstmod r 0 mrds 00000 w fcnfg r cbeie ccie keyacc 00000 w fprot r fpopen rnv6 fphdis fphs fpldis fpls w fstat r cbeif ccif pviol accerr 0 blank 0 0 w fcmd r 0 cmdb w fctl r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w faddrhi r faddrhi w faddrlo r faddrlo w fdatahi r fdatahi w fdatalo r fdatalo w reserved1 r 00000000 w figure 3-3. ftx512k4 register summary 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 142 freescale semiconductor 3.3.2.1 flash clock divider register (fclkdiv) the fclkdiv register is used to control timed events in program and erase algorithms. all bits in the fclkdiv register are readable, bits 6-0 are write once and bit 7 is not writable. 3.3.2.2 flash security register (fsec) the fsec register holds all bits associated with the security of the mcu and flash module. reserved2 r 00000000 w reserved3 r 00000000 w reserved4 r 00000000 w 76543210 r fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w reset 00000000 = unimplemented or reserved figure 3-4. flash clock divider register (fclkdiv) table 3-3. fclkdiv field descriptions field description 7 fdivld clock divider loaded. 0 register has not been written. 1 register has been written to since the last reset. 6 prdiv8 enable prescalar by 8 . 0 the oscillator clock is directly fed into the clock divider . 1 the oscillator clock is divided by 8 before feeding into the clock divider. 5-0 fdiv[5:0] clock divider bits ?the combination of prdiv8 and fdiv[5:0] must divide the oscillator clock down to a frequency of 150 khz?00 khz. the maximum divide ratio is 512. please refer to section 3.4.1.1, ?riting the fclkdiv register for more information. register name bit 7 6 5 4 3 2 1 bit 0 figure 3-3. ftx512k4 register summary (continued) 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 143 all bits in the fsec register are readable but are not writable. the fsec register is loaded from the flash con?uration field at address 0x7f_ff0f during the reset sequence, indicated by f in figure 3-5 . the security function in the flash module is described in section 3.6, ?lash module security . 3.3.2.3 flash test mode register (ftstmod) the ftstmod register is used to control flash test features. 76543210 r keyen rnv5 rnv4 rnv3 rnv2 sec w reset f f ffffff = unimplemented or reserved figure 3-5. flash security register (fsec) table 3-4. fsec field descriptions field description 7-6 keyen[1:0] backdoor key security enable bits the keyen[1:0] bits de?e the enabling of backdoor key access to the flash module as shown in table 3-5 . 5-2 rnv[5:2] reserved nonvolatile bits ?the rnv[5:2] bits should remain in the erased state for future enhancements. 1-0 sec[1:0] flash security bits the sec[1:0] bits de?e the security state of the mcu as shown in table 3-6 . if the flash module is unsecured using backdoor key access, the sec[1:0] bits are forced to 1:0. table 3-5. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 1 1 preferred keyen state to disable backdoor key access. disabled 10 enabled 11 disabled table 3-6. flash security states sec[1:0] status of security 00 secured 01 1 1 preferred sec state to set mcu to secured state. secured 10 unsecured 11 secured 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 144 freescale semiconductor mrds bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. the wrall bit is writable only in special mode to simplify mass erase and erase verify operations. when writing to the ftstmod register in special mode, all unimplemented/reserved bits must be written to 0. 3.3.2.4 flash con?uration register (fcnfg) the fcnfg register enables the flash interrupts and gates the security backdoor writes. 76543210 r0 mrds 00000 w reset 00000000 = unimplemented or reserved figure 3-6. flash test mode register (ftstmod ?ormal mode) 76543210 r0 mrds wrall 0000 w reset 00000000 = unimplemented or reserved figure 3-7. flash test mode register (ftstmod ?special mode) table 3-7. ftstmod field descriptions field description 6? mrds[1:0] margin read setting the mrds[1:0] bits are used to set the sense-amp margin level for reads of the flash array as shown in table 3-8 . 4 wrall write to all register banks ?if the wrall bit is set, all banked fdata registers sharing the same register address will be written simultaneously during a register write. 0 write only to the fdata register bank selected using bksel. 1 write to all fdata register banks. table 3-8. ftstmod margin read settings mrds[1:0] margin read setting 00 normal 01 program margin 1 1 flash array reads will be sensitive to program margin. 10 erase margin 2 2 flash array reads will be sensitive to erase margin. 11 normal 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 145 cbeie, ccie and keyacc bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. keyacc is only writable if keyen (see section 3.3.2.2, ?lash security register (fsec) is set to the enabled state. bksel is readable and writable in special mode to simplify mass erase and erase verify operations. when writing to the fcnfg register in special mode, all unimplemented/ reserved bits must be written to 0. 76543210 r cbeie ccie keyacc 00000 w reset 00000000 = unimplemented or reserved figure 3-8. flash con?uration register (fcnfg ?normal mode) 76543210 r cbeie ccie keyacc 000 bksel w reset 00000000 = unimplemented or reserved figure 3-9. flash con?uration register (fcnfg ?special mode) table 3-9. fcnfg field descriptions field description 7 cbeie command buffer empty interrupt enable the cbeie bit enables an interrupt in case of an empty command buffer in the flash module. 0 command buffer empty interrupt disabled. 1 an interrupt will be requested whenever the cbeif ?g (see section 3.3.2.6, ?lash status register (fstat)? is set. 6 ccie command complete interrupt enable the ccie bit enables an interrupt in case all commands have been completed in the flash module. 0 command complete interrupt disabled. 1 an interrupt will be requested whenever the ccif ?g (see section 3.3.2.6, ?lash status register (fstat) ) is set. 5 keyacc enable security key writing 0 flash writes are interpreted as the start of a command write sequence. 1 writes to flash array are interpreted as keys to open the backdoor. reads of the flash array return invalid data. 1? bksel[1:0] block select ?the bksel[1:0] bits indicates which register bank is active according to table 3-10 . table 3-10. flash register bank selects bksel[1:0] selected block 00 flash block 0 01 flash block 1 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 146 freescale semiconductor 3.3.2.5 flash protection register (fprot) the fprot register defines which flash sectors are protected against program or erase operations. all bits in the fprot register are readable and writable with restrictions (see section 3.3.2.5.1, ?lash protection restrictions ) except for rnv[6] which is only readable. during the reset sequence, the fprot register is loaded from the flash con?uration field at global address 0x7f_ff0d. to change the flash protection that will be loaded during the reset sequence, the upper sector of the flash memory must be unprotected, then the flash protect/security byte located as described in table 3-1 must be reprogrammed. trying to alter data in any protected area in the flash memory will result in a protection violation error and the pviol ?g will be set in the fstat register. the mass erase of a flash block is not possible if any of the flash sectors contained in the flash block are protected. 10 flash block 2 11 flash block 3 76543210 r fpopen rnv6 fphdis fphs fpldis fpls w reset f f ffffff = unimplemented or reserved figure 3-10. flash protection register (fprot) table 3-11. fprot field descriptions field description 7 fpopen flash protection open the fpopen bit determines the protection function for program or erase as shown in table 3-12 . 0 the fphdis and fpldis bits de?e unprotected address ranges as speci?d by the corresponding fphs[1:0] and fpls[1:0] bits. for an mcu without an eeprom module, the fpopen clear state allows the main part of the flash block to be protected while a small address range can remain unprotected for eeprom emulation. 1 the fphdis and fpldis bits enable protection for the address range speci?d by the corresponding fphs[1:0] and fpls[1:0] bits. 6 rnv6 reserved nonvolatile bit ?the rnv[6] bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ?the fphdis bit determines whether there is a protected/unprotected area in a speci? region of the flash memory ending with global address 0x7f_ffff. 0 protection/unprotection enabled. 1 protection/unprotection disabled. 4? fphs[1:0] flash protection higher address size the fphs[1:0] bits determine the size of the protected/unprotected area as shown in table 3-13 . the fphs[1:0] bits can only be written to while the fphdis bit is set. table 3-10. flash register bank selects bksel[1:0] selected block 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 147 all possible flash protection scenarios are shown in figure 3-11 . although the protection scheme is loaded from the flash array at global address 0x7f_ff0d during the reset sequence, it can be changed by the user. this protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if re-programming is not required. 2 fpldis flash protection lower address range disable ?the fpldis bit determines whether there is a protected/unprotected area in a speci? region of the flash memory beginning with global address 0x7f_8000. 0 protection/unprotection enabled. 1 protection/unprotection disabled. 1? fpls[1:0] flash protection lower address size the fpls[1:0] bits determine the size of the protected/unprotected area as shown in table 3-14 . the fpls[1:0] bits can only be written to while the fpldis bit is set. table 3-12. flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to table 3-13 and table 3-14 . 1 1 1 no protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 3-13. flash protection higher address range fphs[1:0] global address range protected size 00 0x7f_f800?x7f_ffff 2 kbytes 01 0x7f_f000?x7f_ffff 4 kbytes 10 0x7f_e000?x7f_ffff 8 kbytes 11 0x7f_c000?x7f_ffff 16 kbytes table 3-14. flash protection lower address range fpls[1:0] global address range protected size 00 0x7f_8000?x7f_83ff 1 kbytes 01 0x7f_8000?x7f_87ff 2 kbytes 10 0x7f_8000?x7f_8fff 4 kbytes 11 0x7f_8000?x7f_9fff 8 kbytes table 3-11. fprot field descriptions (continued) field description 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 148 freescale semiconductor figure 3-11. flash protection scenarios 7 6 5 4 3 2 1 0 fphdis=1 fpldis=1 fphdis=1 fpldis=0 fphdis=0 fpldis=1 fphdis=0 fpldis=0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x7f_8000 0x7f_ffff 0x7f_8000 0x7f_ffff 0x78_0000 0x78_0000 fphs[1:0] fpls[1:0] fpopen=1 fphs[1:0] fpls[1:0] fpopen=0 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 149 3.3.2.5.1 flash protection restrictions the general guideline is that flash protection can only be added and not removed. table 3-15 speci?s all valid transitions between flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored and the fprot register will remain unchanged. the contents of the fprot register re?ct the active protection scenario. see the fphs and fpls descriptions for additional restrictions. 3.3.2.6 flash status register (fstat) the fstat register defines the operational status of the module. table 3-15. flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x. 01234567 0 xxxx 1 xx 2 xx 3 x 4 xx 5 xxxx 6 xxxx 7 xxxxxxxx 76543210 r cbeif ccif pviol accerr 0 blank 0 0 w reset 11000000 = unimplemented or reserved figure 3-12. flash status register (fstat ?normal mode) 76543210 r cbeif ccif pviol accerr 0 blank fail 0 w reset 11000000 = unimplemented or reserved figure 3-13. flash status register (fstat ?special mode) 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 150 freescale semiconductor cbeif, pviol, and accerr are readable and writable, ccif and blank are readable and not writable, remaining bits read 0 and are not writable in normal mode. fail is readable and writable in special mode. fail must be clear in special mode when starting a command write sequence. table 3-16. fstat field descriptions field description 7 cbeif command buffer empty interrupt flag ?the cbeif ?g indicates that the address, data and command buffers are empty so that a new command write sequence can be started. writing a 0 to the cbeif ?g has no effect on cbeif. writing a 0 to cbeif after writing an aligned word to the flash address space, but before cbeif is cleared, will abort a command write sequence and cause the accerr ?g to be set. writing a 0 to cbeif outside of a command write sequence will not set the accerr ?g. the cbeif ?g is cleared by writing a 1 to cbeif. the cbeif ?g is used together with the cbeie bit in the fcnfg register to generate an interrupt request (see figure 3-32 ). 0 command buffers are full. 1 command buffers are ready to accept a new command. 6 ccif command complete interrupt flag the ccif ?g indicates that there are no more commands pending. the ccif ?g is cleared when cbeif is cleared and sets automatically upon completion of all active and pending commands. the ccif ?g does not set when an active commands completes and a pending command is fetched from the command buffer. writing to the ccif ?g has no effect on ccif. the ccif ?g is used together with the ccie bit in the fcnfg register to generate an interrupt request (see figure 3-32 ). 0 command in progress. 1 all commands are completed. 5 pviol protection violation flag ?he pviol ?g indicates an attempt was made to program or erase an address in a protected area of the flash memory during a command write sequence. writing a 0 to the pviol ?g has no effect on pviol. the pviol ?g is cleared by writing a 1 to pviol. while pviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected. 1 protection violation has occurred. 4 accerr access error flag the accerr ?g indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 3.4.1.2, ?ommand write sequence ), issuing an illegal flash command (see table 3-18 ), launching the sector erase abort command terminating a sector erase operation early (see section 3.4.2.6, ?ector erase abort command ) or the execution of a cpu stop instruction while a command is executing (ccif = 0). writing a 0 to the accerr ?g has no effect on accerr. the accerr ?g is cleared by writing a 1 to accerr.while accerr is set, it is not possible to launch a command or start a command write sequence. if accerr is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 no access error detected. 1 access error has occurred. 2 blank flag indicating the erase verify operation status when the ccif ?g is set after completion of an erase verify command, the blank ?g indicates the result of the erase verify operation. the blank ?g is cleared by the flash module when cbeif is cleared as part of a new valid command write sequence. writing to the blank ?g has no effect on blank. 0 flash block veri?d as not erased. 1 flash block veri?d as erased. 1 fail flag indicating a failed flash operation ?the fail ?g will set if the erase verify operation fails (selected flash block veri?d as not erased). writing a 0 to the fail ?g has no effect on fail. the fail ?g is cleared by writing a 1 to fail. 0 flash operation completed without error. 1 flash operation failed. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 151 3.3.2.7 flash command register (fcmd) the fcmd register is the flash command register. all cmdb bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. 3.3.2.8 flash control register (fctl) the fctl register is the flash control register. all bits in the fctl register are readable but are not writable. 76543210 r0 cmdb w reset 11000000 = unimplemented or reserved figure 3-14. flash command register (fcmd) table 3-17. fcmd field descriptions field description 6-0 cmdb[6:0] flash command ?valid flash commands are shown in table 3-18 . writing any command other than those listed in table 3-18 sets the accerr ?g in the fstat register. table 3-18. valid flash command list cmdb[6:0] nvm command 0x05 erase verify 0x06 data compress 0x20 word program 0x40 sector erase 0x41 mass erase 0x47 sector erase abort 76543210 r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w reset f f ffffff = unimplemented or reserved figure 3-15. flash control register (fctl) 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 152 freescale semiconductor the fctl register is loaded from the flash con?uration field byte at global address 0x7f_ff0e during the reset sequence, indicated by f in figure 3-15 . 3.3.2.9 flash address registers (faddr) the faddrhi and faddrlo registers are the flash address registers. all faddrhi and faddrlo bits are readable but are not writable. after an array write as part of a command write sequence, the faddr registers will contain the mapped mcu address written. 3.3.2.10 flash data registers (fdata) the fdatahi and fdatalo registers are the flash data registers. table 3-19. fctl field descriptions field description 7-0 nv[7:0] non volatile bits the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. 76543210 r faddrhi w reset 00000000 = unimplemented or reserved figure 3-16. flash address high register (faddrhi) 76543210 r faddrlo w reset 00000000 = unimplemented or reserved figure 3-17. flash address low register (faddrlo) 76543210 r fdatahi w reset 00000000 = unimplemented or reserved figure 3-18. flash data high register (fdatahi) 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 153 all fdatahi and fdatalo bits are readable but are not writable. at the completion of a data compress operation, the resulting 16-bit signature is stored in the fdata registers. the data compression signature is readable in the fdata registers until a new command write sequence is started. 3.3.2.11 reserved1 this register is reserved for factory testing and is not accessible. all bits read 0 and are not writable. 3.3.2.12 reserved2 this register is reserved for factory testing and is not accessible. all bits read 0 and are not writable. 3.3.2.13 reserved3 this register is reserved for factory testing and is not accessible. 76543210 r fdatalo w reset 00000000 = unimplemented or reserved figure 3-19. flash data low register (fdatalo) 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 3-20. reserved1 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 3-21. reserved2 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 154 freescale semiconductor all bits read 0 and are not writable. 3.3.2.14 reserved4 this register is reserved for factory testing and is not accessible. all bits read 0 and are not writable. 3.4 functional description 3.4.1 flash command operations write operations are used to execute program, erase, erase verify, erase abort, and data compress algorithms described in this section. the program and erase algorithms are controlled by a state machine whose timebase, fclk, is derived from the oscillator clock via a programmable divider. the command register, as well as the associated address and data registers, operate as a buffer and a register (2-stage fifo) so that a second command along with the necessary data and address can be stored to the buffer while the ?st command is still in progress. this pipelined operation allows a time optimization when programming more than one word on a speci? row in the flash block as the high voltage generation can be kept active in between two programming commands. the pipelined operation also allows a simpli?ation of command launching. buffer empty as well as command completion are signalled by ?gs in the flash status register with corresponding interrupts generated, if enabled. the next sections describe: 1. how to write the fclkdiv register 2. command write sequences to program, erase, erase verify, erase abort, and data compress operations on the flash memory 3. valid flash commands 4. effects resulting from illegal flash command write sequences or aborting flash operations 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 3-22. reserved3 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 3-23. reserved4 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 155 3.4.1.1 writing the fclkdiv register prior to issuing any flash command after a reset, the user is required to write the fclkdiv register to divide the oscillator clock down to within the 150 khz to 200 khz range. since the program and erase timings are also a function of the bus clock, the fclkdiv determination must take this information into account. if we de?e: fclk as the clock of the flash timing control block tbus as the period of the bus clock int(x) as taking the integer part of x (e.g. int(4.323) = 4) then fclkdiv register bits prdiv8 and fdiv[5:0] are to be set as described in figure 3-24 . for example, if the oscillator clock frequency is 950khz and the bus clock frequency is 10mhz, fclkdiv bits fdiv[5:0] should be set to 0x04 (000100) and bit prdiv8 set to 0. the resulting fclk frequency is then 190khz. as a result, the flash program and erase algorithm timings are increased over the optimum target by: if the oscillator clock frequency is 16mhz and the bus clock frequency is 40mhz, fclkdiv bits fdiv[5:0] should be set to 0x0a (001010) and bit prdiv8 set to 1. the resulting fclk frequency is then 182khz. in this case, the flash program and erase algorithm timings are increased over the optimum target by: caution program and erase command execution time will increase proportionally with the period of fclk. because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the flash memory cannot be performed if the bus clock runs at less than 1 mhz. programming or erasing the flash memory with fclk < 150 khz should be avoided. setting fclkdiv to a value such that fclk < 150 khz can destroy the flash memory due to overstress. setting fclkdiv to a value such that (1/fclk+tbus) < 5 s can result in incomplete programming or erasure of the flash memory cells. if the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if the fclkdiv register has not been written to, the flash command loaded during a command write sequence will not execute and the accerr ?g in the fstat register will set. 200 190 () 200 ? 100 5% = 200 182 () 200 ? 100 9% = 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 156 freescale semiconductor figure 3-24. determination procedure for prdiv8 and fdiv bits prdiv8=1 yes no prdiv8=0 (reset) 12.8mhz? fclk=(prdclk)/(1+fdiv[5:0]) prdclk=oscillator_clock prdclk=oscillator_clock/8 prdclk[mhz]*(5+tbus[ s]) no fdiv[5:0]=prdclk[mhz]*(5+tbus[ s])-1 yes start tbus < 1 s? an integer? fdiv[5:0]=int(prdclk[mhz]*(5+tbus[ s])) 1/fclk[mhz] + tbus[ s] > 5 and fclk > 0.15mhz ? end yes no fdiv[5:0] > 4? all commands impossible yes no all commands impossible no try to decrease tbus yes oscillator_clock 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 157 3.4.1.2 command write sequence the flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. before starting a command write sequence, the accerr and pviol ?gs in the fstat register must be clear (see section 3.3.2.6, ?lash status register (fstat) ) and the cbeif ?g should be tested to determine the state of the address, data and command buffers. if the cbeif ?g is set, indicating the buffers are empty, a new command write sequence can be started. if the cbeif ?g is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. a command write sequence consists of three steps which must be strictly adhered to with writes to the flash module not permitted between the steps. however, flash register and array reads are allowed during a command write sequence. the basic command write sequence is as follows: 1. write to a valid address in the flash memory. addresses in multiple flash blocks can be written to as long as the location is at the same relative address in each available flash block. multiple addresses must be written in flash block order starting with the lower flash block. 2. write a valid command to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the command. the address written in step 1 will be stored in the faddr registers and the data will be stored in the fdata registers. if the cbeif ?g in the fstat register is clear when the ?st flash array write occurs, the contents of the address and data buffers will be overwritten and the cbeif ?g will be set. when the cbeif ?g is cleared, the ccif ?g is cleared on the same bus cycle by the flash command controller indicating that the command was successfully launched. for all command write sequences except data compress and sector erase abort, the cbeif ?g will set four bus cycles after the ccif ?g is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. for data compress and sector erase abort operations, the cbeif ?g will remain clear until the operation completes. except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. the sector erase abort command is launched when the cbeif ?g is cleared as part of a sector erase abort command write sequence. once a command is launched, the completion of the command operation is indicated by the setting of the ccif ?g in the fstat register. the ccif ?g will set upon completion of all active and buffered commands. 3.4.2 flash commands table 3-20 summarizes the valid flash commands along with the effects of the commands on the flash block. table 3-20. flash command description fcmdb nvm command function on flash memory 0x05 erase verify verify all memory bytes in the flash block are erased. if the flash block is erased, the blank ?g in the fstat register will set upon command completion. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 158 freescale semiconductor caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. 0x06 data compress compress data from a selected portion of the flash block. the resulting signature is stored in the fdata register. 0x20 program program a word (two bytes) in the flash block. 0x40 sector erase erase all memory bytes in a sector of the flash block. 0x41 mass erase erase all memory bytes in the flash block. a mass erase of the full flash block is only possible when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command. 0x47 sector erase abort abort the sector erase operation. the sector erase operation will terminate according to a set procedure. the flash sector should not be considered erased if the accerr ?g is set upon command completion. table 3-20. flash command description fcmdb nvm command function on flash memory 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 159 3.4.2.1 erase verify command the erase verify operation will verify that a flash block is erased. an example ?w to execute the erase verify operation is shown in figure 3-25 . the erase verify command write sequence is as follows: 1. write to a flash block address to start the command write sequence for the erase verify command. the address and data written will be ignored. multiple flash blocks can be simultaneously erase veri?d by writing to the same relative address in each flash block. 2. write the erase verify command, 0x05, to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the erase verify command. after launching the erase verify command, the ccif ?g in the fstat register will set after the operation has completed unless a new command write sequence has been buffered. the number of bus cycles required to execute the erase verify operation is equal to the number of addresses in a flash block plus 14 bus cycles as measured from the time the cbeif ?g is cleared until the ccif ?g is set. upon completion of the erase verify operation, the blank ?g in the fstat register will be set if all addresses in the selected flash blocks are veri?d to be erased. if any address in a selected flash block is not erased, the erase verify operation will terminate and the blank ?g in the fstat register will remain clear. the mrds bits in the ftstmod register will determine the sense-amp margin setting during the erase verify operation. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 160 freescale semiconductor figure 3-25. example erase verify command flow write: flash block address write: fcmd register erase verify command 0x05 write: fstat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: fstat register yes no access error and protection violation no and dummy data bit polling for command completion check read: fstat register yes read: fstat register no start yes check cbeif set? next no yes address, data, command buffer empty check flash block? ccif set? accerr/ pviol set? no erase verify status yes exit flash block not erased exit flash block erased blank set? decrement global address write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? note: fclkdiv needs to be set once after each reset. simultaneous multiple flash block decision by 128k 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 161 3.4.2.2 data compress command the data compress operation will check flash code integrity by compressing data from a selected portion of the flash memory into a signature analyzer. an example ?w to execute the data compress operation is shown in figure 3-26 . the data compress command write sequence is as follows: 1. write to a flash block address to start the command write sequence for the data compress command. the address written determines the starting address for the data compress operation and the data written determines the number of consecutive words to compress. if the data value written is 0x0000, 64k addresses or 128 kbytes will be compressed. multiple flash blocks can be simultaneously compressed by writing to the same relative address in each flash block. if more than one flash block is written to in this step, the ?st data written will determine the number of consecutive words to compress in each selected flash block. 2. write the data compress command, 0x06, to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the data compress command. after launching the data compress command, the ccif ?g in the fstat register will set after the data compress operation has completed. the number of bus cycles required to execute the data compress operation is equal to two times the number of consecutive words to compress plus the number of flash blocks simultaneously compressed plus 18 bus cycles as measured from the time the cbeif ?g is cleared until the ccif ?g is set. once the ccif ?g is set, the signature generated by the data compress operation is available in the fdata registers. the signature in the fdata registers can be compared to the expected signature to determine the integrity of the selected data stored in the selected flash memory. if the last address of a flash block is reached during the data compress operation, data compression will continue with the starting address of the same flash block. the mrds bits in the ftstmod register will determine the sense-amp margin setting during the data compress operation. note since the fdata registers (or data buffer) are written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. the cbeif ?g will not set after launching the data compress command to indicate that a command should not be buffered behind it. if an attempt is made to start a new command write sequence with a data compress operation active, the accerr ?g in the fstat register will be set. a new command write sequence should only be started after reading the signature stored in the fdata registers. in order to take corrective action, it is recommended that the data compress command be executed on a flash sector or subset of a flash sector. if the data compress operation on a flash sector returns an invalid signature, the flash sector should be erased using the sector erase command and then reprogrammed using the program command. the data compress command can be used to verify that a sector or sequential set of sectors are erased. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 162 freescale semiconductor figure 3-26. example data compress command flow write: flash address to start write: fcmd register data compress command 0x06 write: fstat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: fstat register yes no access error and protection violation no compression and number of word bit polling for command completion check read: fstat register yes read: fstat register no start yes check cbeif set? next no yes address, data, command buffer empty check flash block? ccif set? accerr/ pviol set? exit erase and reprogram by 128k decrement global address write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? note: fclkdiv needs to be set once after each reset. simultaneous multiple flash block decision flash sector(s) compressed data compress signature read: fdata registers no yes signature valid? addresses to compress note: address used to select flash block; data ignored. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 163 3.4.2.2.1 data compress operation the flash module contains a 16-bit multiple-input signature register (misr) for each flash block to generate a 16-bit signature based on selected flash array data. if multiple flash blocks are selected for simultaneous compression, then the signature from each flash block is further compressed to generate a single 16-bit signature. the ?al 16-bit signature, found in the fdata registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation: misr[15:0] = {misr[14:0], ^misr[15,4,2,1]} ^ data[15:0] eqn. 3-1 where misr is the content of the internal signature register associated with each flash block and data is the data to be compressed as shown in figure 3-27 . figure 3-27. 16-bit misr diagram during the data compress operation, the following steps are executed: 1. misr for each flash block is reset to 0xffff. 2. initialized data equal to 0xffff is compressed into the misr for each selected flash block which results in the misr containing 0x0001. 3. data equal to the selected flash array data range is read and compressed into the misr for each selected flash block with addresses incrementing. 4. data equal to the selected flash array data range is read and compressed into the misr for each selected flash block with addresses decrementing. 5. if flash block 0 is selected for compression, data equal to the contents of the misr for flash block 0 is compressed into the misr for flash block 0. if data in flash block 0 was not selected for compression, the misr for flash block 0 contains 0xffff. 6. if flash block 1 is selected for compression, data equal to the contents of the misr for flash block 1 is compressed into the misr for flash block 0. 7. if flash block 2 is selected for compression, data equal to the contents of the misr for flash block 2 is compressed into the misr for flash block 0. 8. if flash block 3 is selected for compression, data equal to the contents of the misr for flash block 3 is compressed into the misr for flash block 0. 9. the contents of the misr for flash block 0 are written to the fdata registers. dq > + + = exclusive-or data[0] m0 dq > + data[1] m1 dq > + data[2] m2 dq > + data[3] m3 dq > + data[4] m4 dq > + data[5] m5 dq > + data[15] m15 ... + + + misr[15:0] = q[15:0] 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 164 freescale semiconductor 3.4.2.3 program command the program operation will program a previously erased word in the flash memory using an embedded algorithm. an example ?w to execute the program operation is shown in figure 3-28 . the program command write sequence is as follows: 1. write to a flash block address to start the command write sequence for the program command. the data written will be programmed to the address written. multiple flash blocks can be simultaneously programmed by writing to the same relative address in each flash block. 2. write the program command, 0x20, to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the program command. if a word to be programmed is in a protected area of the flash block, the pviol ?g in the fstat register will set and the program command will not launch. once the program command has successfully launched, the ccif ?g in the fstat register will set after the program operation has completed unless a new command write sequence has been buffered. by executing a new program command write sequence on sequential words after the cbeif ?g in the fstat register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the ccif ?g to set after each program operation. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 165 figure 3-28. example program command flow write: flash address write: fcmd register program command 0x20 write: fstat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: fstat register yes no access error and protection violation no and program data bit polling for buffer empty check read: fstat register yes read: fstat register no start yes check cbeif set? next no yes address, data, command buffer empty check flash block? cbeif set? accerr/ pviol set? exit by 128k decrement global address write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? note: fclkdiv needs to be set once after each reset. simultaneous multiple flash block decision no yes sequential programming decision next word? no bit polling for command completion check read: fstat register yes ccif set? 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 166 freescale semiconductor 3.4.2.4 sector erase command the sector erase operation will erase all addresses in a 1 kbyte sector of flash memory using an embedded algorithm. an example ?w to execute the sector erase operation is shown in figure 3-29 . the sector erase command write sequence is as follows: 1. write to a flash block address to start the command write sequence for the sector erase command. the flash address written determines the sector to be erased while global address bits [9:0] and the data written are ignored. multiple flash sectors can be simultaneously erased by writing to the same relative address in each flash block. 2. write the sector erase command, 0x40, to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the sector erase command. if a flash sector to be erased is in a protected area of the flash block, the pviol ?g in the fstat register will set and the sector erase command will not launch. once the sector erase command has successfully launched, the ccif ?g in the fstat register will set after the sector erase operation has completed unless a new command write sequence has been buffered. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 167 figure 3-29. example sector erase command flow write: flash sector address write: fcmd register sector erase command 0x40 write: fstat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: fstat register yes no access error and protection violation and dummy data read: fstat register read: fstat register no start yes check cbeif set? next no yes address, data, command buffer empty check flash block? accerr/ pviol set? exit by 128k decrement global address write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? note: fclkdiv needs to be set once after each reset. simultaneous multiple flash block decision no bit polling for command completion check yes ccif set? 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 168 freescale semiconductor 3.4.2.5 mass erase command the mass erase operation will erase all addresses in a flash block using an embedded algorithm. an example ?w to execute the mass erase operation is shown in figure 3-30 . the mass erase command write sequence is as follows: 1. write to a flash block address to start the command write sequence for the mass erase command. the address and data written will be ignored. multiple flash blocks can be simultaneously mass erased by writing to the same relative address in each flash block. 2. write the mass erase command, 0x41, to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the mass erase command. if a flash block to be erased contains any protected area, the pviol ?g in the fstat register will set and the mass erase command will not launch. once the mass erase command has successfully launched, the ccif ?g in the fstat register will set after the mass erase operation has completed unless a new command write sequence has been buffered. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 169 figure 3-30. example mass erase command flow write: flash block address write: fcmd register mass erase command 0x41 write: fstat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: fstat register yes no access error and protection violation and dummy data read: fstat register read: fstat register no start yes check cbeif set? next no yes address, data, command buffer empty check flash block? accerr/ pviol set? exit by 128k decrement global address write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? note: fclkdiv needs to be set once after each reset. simultaneous multiple flash block decision no bit polling for command completion check yes ccif set? 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 170 freescale semiconductor 3.4.2.6 sector erase abort command the sector erase abort operation will terminate the active sector erase operation so that other sectors in a flash block are available for read and program operations without waiting for the sector erase operation to complete. an example ?w to execute the sector erase abort operation is shown in figure 3-31 . the sector erase abort command write sequence is as follows: 1. write to any flash block address to start the command write sequence for the sector erase abort command. the address and data written are ignored. 2. write the sector erase abort command, 0x47, to the fcmd register. 3. clear the cbeif ?g in the fstat register by writing a 1 to cbeif to launch the sector erase abort command. if the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the accerr ?g will set once the operation completes as indicated by the ccif ?g being set. the accerr ?g sets to inform the user that the flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that speci? sector. if the sector erase abort command is launched but the active sector erase operation completes normally, the accerr ?g will not set upon completion of the operation as indicated by the ccif ?g being set. therefore, if the accerr ?g is not set after the sector erase abort command has completed, a flash sector being erased when the abort command was launched will be fully erased. the maximum number of cycles required to abort a sector erase operation is equal to four fclk periods (see section 3.4.1.1, ?riting the fclkdiv register ) plus ve bus cycles as measured from the time the cbeif ?g is cleared until the ccif ?g is set. if sectors in multiple flash blocks are being simultaneously erased, the sector erase abort operation will be applied to all active flash blocks without writing to each flash block in the sector erase abort command write sequence. note since the accerr bit in the fstat register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. the cbeif ?g will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. if an attempt is made to start a new command write sequence with a sector erase abort operation active, the accerr ?g in the fstat register will be set. a new command write sequence may be started after clearing the accerr ?g, if set. note the sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 171 figure 3-31. example sector erase abort command flow write: dummy flash address write: fcmd register sector erase abort cmd 0x47 write: fstat register clear cbeif 0x80 1. 2. 3. read: fstat register and dummy data bit polling for command completion check yes ccif set? execute sector erase command flow no bit polling for command completion check read: fstat register yes ccif set? no yes abort needed? erase clear accerr 0x10 write: fstat register yes no access error check accerr set? sector erase completed sector erase aborted no exit exit sector erase completed exit 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 172 freescale semiconductor 3.4.3 illegal flash operations the accerr ?g will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. writing to a flash address before initializing the fclkdiv register. 2. writing a byte or misaligned word to a valid flash address. 3. starting a command write sequence while a data compress operation is active. 4. starting a command write sequence while a sector erase abort operation is active. 5. writing a flash address in step 1 of a command write sequence that is not the same relative address as the ?st one written in the same command write sequence. 6. writing to any flash register other than fcmd after writing to a flash address. 7. writing a second command to the fcmd register in the same command write sequence. 8. writing an invalid command to the fcmd register. 9. when security is enabled, writing a command other than mass erase to the fcmd register when the write originates from a non-secure memory location or from the background debug mode. 10. writing to a flash address after writing to the fcmd register. 11. writing to any flash register other than fstat (to clear cbeif) after writing to the fcmd register. 12. writing a 0 to the cbeif ?g in the fstat register to abort a command write sequence. the accerr ?g will not be set if any flash register is read during a valid command write sequence. the accerr ?g will also be set if any of the following events occur: 1. launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see section 3.4.2.6, ?ector erase abort command ). 2. the mcu enters stop mode and a program or erase operation is in progress. the operation is aborted immediately and any pending command is purged (see section 3.5.2, ?top mode ). if the flash memory is read during execution of an algorithm (ccif = 0), the read operation will return invalid data and the accerr ?g will not be set. if the accerr ?g is set in the fstat register, the user must clear the accerr ?g before starting another command write sequence (see section 3.3.2.6, ?lash status register (fstat) ). the pviol ?g will be set after the command is written to the fcmd register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. writing the program command if an address written in the command write sequence was in a protected area of the flash memory 2. writing the sector erase command if an address written in the command write sequence was in a protected area of the flash memory 3. writing the mass erase command to a flash block while any flash protection is enabled in the block 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 173 if the pviol ?g is set in the fstat register, the user must clear the pviol ?g before starting another command write sequence (see section 3.3.2.6, ?lash status register (fstat) ). 3.5 operating modes 3.5.1 wait mode if a command is active (ccif = 0) when the mcu enters wait mode, the active command and any buffered command will be completed. the flash module can recover the mcu from wait mode if the cbeif and ccif interrupts are enabled (see section 3.8, ?nterrupts ). 3.5.2 stop mode if a command is active (ccif = 0) when the mcu enters stop mode, the operation will be aborted and, if the operation is program or erase, the flash array data being programmed or erased may be corrupted and the ccif and accerr ?gs will be set. if active, the high voltage circuitry to the flash memory will immediately be switched off when entering stop mode. upon exit from stop mode, the cbeif ?g is set and any buffered command will not be launched. the accerr ?g must be cleared before starting a command write sequence (see section 3.4.1.2, ?ommand write sequence ). note as active commands are immediately aborted when the mcu enters stop mode, it is strongly recommended that the user does not use the stop instruction during program or erase operations. 3.5.3 background debug mode in background debug mode (bdm), the fprot register is writable. if the mcu is unsecured, then all flash commands listed in table 3-20 can be executed. if the mcu is secured and is in special single chip mode, only mass erase can be executed. 3.6 flash module security the flash module provides the necessary security information to the mcu. after each reset, the flash module determines the security state of the mcu as de?ed in section 3.3.2.2, ?lash security register (fsec) ? the contents of the flash security byte at 0x7f_ff0f in the flash con?uration field must be changed directly by programming 0x7f_ff0f when the mcu is unsecured and the higher address sector is unprotected. if the flash security byte is left in a secured state, any reset will cause the mcu to initialize to a secure operating mode. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 174 freescale semiconductor 3.6.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7f_ff00?x7f_ff07). if the keyen[1:0] bits are in the enabled state (see section 3.3.2.2, ?lash security register (fsec) ) and the keyacc bit is set, a write to a backdoor key address in the flash memory triggers a comparison between the written data and the backdoor key data stored in the flash memory. if all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the flash memory, the mcu will be unsecured. the data must be written to the backdoor keys sequentially starting with 0x7f_ff00? and ending with 0x7f_ff06?. 0x0000 and 0xffff are not permitted as backdoor keys. while the keyacc bit is set, reads of the flash memory will return invalid data. the user code stored in the flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 3.3.2.2, ?lash security register (fsec) ), the mcu can be unsecured by the backdoor key access sequence described below: 1. set the keyacc bit in the flash con?uration register (fcnfg). 2. write the correct four 16-bit words to flash addresses 0xff00?xff07 sequentially starting with 0x7f_ff00. 3. clear the keyacc bit. depending on the user code used to write the backdoor keys, a wait cycle (nop) may be required before clearing the keyacc bit. 4. if all four 16-bit words match the backdoor keys stored in flash addresses 0x7f_ff00?x7f_ff07, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 1:0. the backdoor key access sequence is monitored by an internal security state machine. an illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the mcu in the secured state. a reset of the mcu will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. the following operations during the backdoor key access sequence will lock the security state machine: 1. if any of the four 16-bit words does not match the backdoor keys programmed in the flash array. 2. if the four 16-bit words are written in the wrong sequence. 3. if more than four 16-bit words are written. 4. if any of the four 16-bit words written are 0x0000 or 0xffff. 5. if the keyacc bit does not remain set while the four 16-bit words are written. 6. if any two of the four 16-bit words are written on successive mcu clock cycles. after the backdoor keys have been correctly matched, the mcu will be unsecured. once the mcu is unsecured, the flash security byte can be programmed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7f_ff00?x7f_ff07 in the flash con?uration field. the security as de?ed in the flash security byte (0x7f_ff0f) is not changed by using the backdoor key access sequence to unsecure. the backdoor keys stored in addresses 0x7f_ff00?x7f_ff07 are 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 175 unaffected by the backdoor key access sequence. after the next reset of the mcu, the security state of the flash module is determined by the flash security byte (0x7f_ff0f). the backdoor key access sequence has no effect on the program and erase protections de?ed in the flash protection register. it is not possible to unsecure the mcu in special single chip mode by using the backdoor key access sequence in background debug mode (bdm). 3.6.2 unsecuring the mcu in special single chip mode using bdm the mcu can be unsecured in special single chip mode by erasing the flash module by the following method: reset the mcu into special single chip mode, delay while the erase test is performed by the bdm secure rom, send bdm commands to disable protection in the flash module, and execute a mass erase command write sequence to erase the flash memory. after the ccif ?g sets to indicate that the mass operation has completed, reset the mcu into special single chip mode. the bdm secure rom will verify that the flash memory is erased and will assert the unsec bit in the bdm status register. this bdm action will cause the mcu to override the flash security state and the mcu will be unsecured. all bdm commands will be enabled and the flash security byte may be programmed to the unsecure state by the following method: send bdm commands to execute a word program sequence to program the flash security byte to the unsecured state and reset the mcu. 3.7 resets 3.7.1 flash reset sequence on each reset, the flash module executes a reset sequence to hold cpu activity while loading the following registers from the flash memory according to table 3-1 : fprot ?flash protection register (see section 3.3.2.5 ). fctl - flash control register (see section 3.3.2.8 ). fsec ?flash security register (see section 3.3.2.2 ). 3.7.2 reset while flash command active if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed. 3.8 interrupts the flash module can generate an interrupt when all flash command operations have completed, when the flash address, data and command buffers are empty. 4 .com u datasheet
chapter 3 512 kbyte flash module (s12xftx512k4v3) MC9S12XHZ512 data sheet, rev. 1.02 176 freescale semiconductor note vector addresses and their relative interrupt priority are determined at the mcu level. 3.8.1 description of flash interrupt operation the logic used for generating interrupts is shown in figure 3-32 . the flash module uses the cbeif and ccif ?gs in combination with the cbie and ccie enable bits to generate the flash command interrupt request. figure 3-32. flash interrupt implementation for a detailed description of the register bits, refer to section 3.3.2.4, ?lash con?uration register (fcnfg) and section 3.3.2.6, ?lash status register (fstat) . table 3-21. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash address, data and command buffers empty cbeif (fstat register) cbeie (fcnfg register) i bit all flash commands completed ccif (fstat register) ccie (fcnfg register) i bit flash command interrupt request cbeie cbeif ccie ccif 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 177 chapter 4 4 kbyte eeprom module (s12xeetx4kv2) 4.1 introduction this document describes the eetx4k module which includes a 4 kbyte eeprom (nonvolatile) memory. the eeprom memory may be read as either bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. the eeprom memory is ideal for data storage for single-supply applications allowing for ?ld reprogramming without requiring external voltage sources for program or erase. program and erase functions are controlled by a command driven interface. the eeprom module supports both block erase (all memory bytes) and sector erase (4 memory bytes). an erased bit reads 1 and a programmed bit reads 0. the high voltage required to program and erase the eeprom memory is generated internally. it is not possible to read from the eeprom block while it is being erased or programmed. caution an eeprom word (2 bytes) must be in the erased state before being programmed. cumulative programming of bits within a word is not allowed. 4.1.1 glossary command write sequence ?a three-step mcu instruction sequence to execute built-in algorithms (including program and erase) on the eeprom memory. 4.1.2 features 4 kbytes of eeprom memory divided into 1024 sectors of 4 bytes automated program and erase algorithm interrupts on eeprom command completion and command buffer empty fast sector erase and word program operation 2-stage command pipeline sector erase abort feature for critical interrupt response flexible protection scheme to prevent accidental program or erase single power supply for all eeprom operations including program and erase 4.1.3 modes of operation program, erase and erase verify operations (please refer to section 4.4.1, ?eprom command operations for details). 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 178 freescale semiconductor 4.1.4 block diagram a block diagram of the eeprom module is shown in figure 4-1 . figure 4-1. eetx4k block diagram 4.2 external signal description the eeprom module contains no signals that connect off-chip. 4.3 memory map and register de?ition this section describes the memory map and registers for the eeprom module. 4.3.1 module memory map the eeprom memory map is shown in figure 4-2 . the hcs12x architecture places the eeprom memory addresses between global addresses 0x13_f000 and 0x13_ffff. the eprot register, described in section 4.3.2.5, ?eprom protection register (eprot) , can be set to protect the upper region in the eeprom memory from accidental program or erase. the eeprom addresses covered by this protectable eetx4k eeprom 2k * 16 bits sector 0 sector 1 sector 1023 oscillator clock divider clock command interrupt request eeclk protection command pipeline cmd2 addr2 data2 cmd1 addr1 data1 registers eeprom interface 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 179 region are shown in the eeprom memory map. the default protection setting is stored in the eeprom con?uration ?ld as described in table 4-1 . table 4-1. eeprom con?uration field global address size (bytes) description 0x13_fffc 1 reserved 0x13_fffd 1 eeprom protection byte refer to section 4.3.2.5, ?eprom protection register (eprot) 0x13_fffe ?0x13_ffff 2 reserved 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 180 freescale semiconductor figure 4-2. eeprom memory map eeprom registers module base+ 0x0000 eeprom con?uration field module base + 0x000b eeprom start = 0x13_f000 eeprom end = 0x13_ffff 0x13_ffc0 0x13_ff80 eeprom memory protected region 64, 128, 192, 256, 320, 384, 448, 512 bytes eeprom memory 3584 bytes (up to 4032 bytes) 12 bytes 4 bytes (0x13_fffc ?0x13_ffff) 0x13_ff40 0x13_ff00 0x13_fec0 0x13_fe80 0x13_fe40 0x13_fe00 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 181 4.3.2 register descriptions the eeprom module also contains a set of 12 control and status registers located between eeprom module base + 0x0000 and 0x000b. a summary of the eeprom module registers is given in figure 4-3 . detailed descriptions of each register bit are provided. register name bit 7 6 5 4 3 2 1 bit 0 eclkdiv r edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 w reserved1 r 00000000 w reserved2 r 00000000 w ecnfg r cbeie ccie 000000 w eprot r epopen rnv6 rnv5 rnv4 epdis eps2 eps1 eps0 w estat r cbeif ccif pviol accerr 0 blank 0 0 w ecmd r 0 cmdb w reserved3 r 00000000 w eaddrhi r 00000 eabhi w eaddrlo r eablo w edatahi r edhi w edatalo r edlo w = unimplemented or reserved figure 4-3. eetx4k register summary 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 182 freescale semiconductor 4.3.2.1 eeprom clock divider register (eclkdiv) the eclkdiv register is used to control timed events in program and erase algorithms. all bits in the eclkdiv register are readable, bits 6? are write once and bit 7 is not writable. 4.3.2.2 reserved1 this register is reserved for factory testing and is not accessible. all bits read 0 and are not writable. 4.3.2.3 reserved2 this register is reserved for factory testing and is not accessible. 76543210 r edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 w reset 00000000 = unimplemented or reserved figure 4-4. eeprom clock divider register (eclkdiv) table 4-2. eclkdiv field descriptions field description 7 edivld clock divider loaded 0 register has not been written. 1 register has been written to since the last reset. 6 prdiv8 enable prescalar by 8 0 the oscillator clock is directly fed into the eclkdiv divider. 1 enables a prescalar by 8, to divide the oscillator clock before feeding into the clock divider. 5:0 ediv[5:0] clock divider bits the combination of prdiv8 and ediv[5:0] effectively divides the eeprom module input oscillator clock down to a frequency of 150 khz ?200 khz. the maximum divide ratio is 512. please refer to section 4.4.1.1, ?riting the eclkdiv register for more information. 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 4-5. reserved1 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 183 all bits read 0 and are not writable. 4.3.2.4 eeprom con?uration register (ecnfg) the ecnfg register enables the eeprom interrupts. cbeie and ccie bits are readable and writable while all remaining bits read 0 and are not writable. 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 4-6. reserved2 76543210 r cbeie ccie 000000 w reset 00000000 = unimplemented or reserved figure 4-7. eeprom con?uration register (ecnfg) table 4-3. ecnfg field descriptions field description 7 cbeie command buffer empty interrupt enable the cbeie bit enables an interrupt in case of an empty command buffer in the eeprom module. 0 command buffer empty interrupt disabled. 1 an interrupt will be requested whenever the cbeif ?g (see section 4.3.2.6, ?eprom status register (estat) ) is set. 6 ccie command complete interrupt enable the ccie bit enables an interrupt in case all commands have been completed in the eeprom module. 0 command complete interrupt disabled. 1 an interrupt will be requested whenever the ccif ?g (see section 4.3.2.6, ?eprom status register (estat) ) is set. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 184 freescale semiconductor 4.3.2.5 eeprom protection register (eprot) the eprot register de?es which eeprom sectors are protected against program or erase operations. during the reset sequence, the eprot register is loaded from the eeprom protection byte at address offset 0x0ffd (see table 4-1 ).all bits in the eprot register are readable and writable except for rnv[6:4] which are only readable. the epopen and epdis bits can only be written to the protected state. the eps bits can be written anytime until bit epdis is cleared. if the epopen bit is cleared, the state of the epdis and eps bits is irrelevant. to change the eeprom protection that will be loaded during the reset sequence, the eeprom memory must be unprotected, then the eeprom protection byte must be reprogrammed. trying to alter data in any protected area in the eeprom memory will result in a protection violation error and the pviol ?g will be set in the estat register. the mass erase of an eeprom block is possible only when protection is fully disabled by setting the epopen and epdis bits. 76543210 r epopen rnv6 rnv5 rnv4 epdis eps2 eps1 eps0 w reset f f ffffff = unimplemented or reserved figure 4-8. eeprom protection register (eprot) table 4-4. eprot field descriptions field description 7 epopen opens the eeprom for program or erase 0 the entire eeprom memory is protected from program and erase. 1 the eeprom sectors not protected are enabled for program or erase. 6:4 rnv[6:4] reserved nonvolatile bits the rnv[6:4] bits should remain in the erased state ? for future enhancements. 3 epdis eeprom protection address range disable the epdis bit determines whether there is a protected area in a speci? region of the eeprom memory ending with address offset 0x0fff. 0 protection enabled. 1 protection disabled. 2:0 eps[2:0] eeprom protection address size ?the eps[2:0] bits determine the size of the protected area as shown in table 4-5 . the eps bits can only be written to while the epdis bit is set. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 185 4.3.2.6 eeprom status register (estat) the estat register de?es the operational status of the module. cbeif, pviol, and accerr are readable and writable, ccif and blank are readable and not writable, remaining bits read 0 and are not writable in normal mode. fail is readable and writable in special mode. table 4-5. eeprom protection address range eps[2:0] address offset range protected size 000 0x0fc0 ?0x0fff 64 bytes 001 0x0f80 ?0x0fff 128 bytes 010 0x0f40 ?0x0fff 192 bytes 011 0x0f00 ?0x0fff 256 bytes 100 0x0ec0 ?0x0fff 320 bytes 101 0x0e80 ?0x0fff 384 bytes 110 0x0e40 ?0x0fff 448 bytes 111 0x0e00 ?0x0fff 512 bytes 76543210 r cbeif ccif pviol accerr 0 blank 0 0 w reset 11000000 = unimplemented or reserved figure 4-9. eeprom status register (estat ?normal mode) 76543210 r cbeif ccif pviol accerr 0 blank fail 0 w reset 11000000 = unimplemented or reserved figure 4-10. eeprom status register (estat ?special mode) 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 186 freescale semiconductor table 4-6. estat field descriptions field description 7 cbeif command buffer empty interrupt flag ?the cbeif ?g indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. the cbeif ?g is cleared by writing a 1 to cbeif. writing a 0 to the cbeif ?g has no effect on cbeif. writing a 0 to cbeif after writing an aligned word to the eeprom address space but before cbeif is cleared will abort a command write sequence and cause the accerr ?g to be set. writing a 0 to cbeif outside of a command write sequence will not set the accerr ?g. the cbeif ?g is used together with the cbeie bit in the ecnfg register to generate an interrupt request (see figure 4-24 ). 0 buffers are full. 1 buffers are ready to accept a new command. 6 ccif command complete interrupt flag the ccif ?g indicates that there are no more commands pending. the ccif ?g is cleared when cbeif is clear and sets automatically upon completion of all active and pending commands. the ccif ?g does not set when an active commands completes and a pending command is fetched from the command buffer. writing to the ccif ?g has no effect on ccif. the ccif ?g is used together with the ccie bit in the ecnfg register to generate an interrupt request (see figure 4-24 ). 0 command in progress. 1 all commands are completed. 5 pviol protection violation flag ?the pviol ?g indicates an attempt was made to program or erase an address in a protected area of the eeprom memory during a command write sequence. the pviol ?g is cleared by writing a 1 to pviol. writing a 0 to the pviol ?g has no effect on pviol. while pviol is set, it is not possible to launch a command or start a command write sequence. 0 no failure. 1 a protection violation has occurred. 4 accerr access error flag ?the accerr ?g indicates an illegal access has occurred to the eeprom memory caused by either a violation of the command write sequence (see section 4.4.1.2, ?ommand write sequence ), issuing an illegal eeprom command (see table 4-8 ), launching the sector erase abort command terminating a sector erase operation early (see section 4.4.2.5, ?ector erase abort command ) or the execution of a cpu stop instruction while a command is executing (ccif = 0). the accerr ?g is cleared by writing a 1 to accerr. writing a 0 to the accerr ?g has no effect on accerr. while accerr is set, it is not possible to launch a command or start a command write sequence. if accerr is set by an erase verify operation, any buffered command will not launch. 0 no access error detected. 1 access error has occurred. 2 blank flag indicating the erase verify operation status when the ccif ?g is set after completion of an erase verify command, the blank ?g indicates the result of the erase verify operation. the blank ?g is cleared by the eeprom module when cbeif is cleared as part of a new valid command write sequence. writing to the blank ?g has no effect on blank. 0 eeprom block veri?d as not erased. 1 eeprom block veri?d as erased. 1 fail flag indicating a failed eeprom operation ?the fail ?g will set if the erase verify operation fails (eeprom block veri?d as not erased). the fail ?g is cleared by writing a 1 to fail. writing a 0 to the fail ?g has no effect on fail. 0 eeprom operation completed without error. 1 eeprom operation failed. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 187 4.3.2.7 eeprom command register (ecmd) the ecmd register is the eeprom command register. all cmdb bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. 4.3.2.8 reserved3 this register is reserved for factory testing and is not accessible. all bits read 0 and are not writable. eeprom address registers (eaddr) 76543210 r0 cmdb w reset 00000000 = unimplemented or reserved figure 4-11. eeprom command register (ecmd) table 4-7. ecmd field descriptions field description 6:0 cmdb[6:0] eeprom command bits ?valid eeprom commands are shown in table 4-8 . writing any command other than those listed in table 4-8 sets the accerr ?g in the estat register. table 4-8. valid eeprom command list cmdb[6:0] command 0x05 erase verify 0x20 word program 0x40 sector erase 0x41 mass erase 0x47 sector erase abort 0x60 sector modify 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 4-12. reserved3 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 188 freescale semiconductor the eaddrhi and eaddrlo registers are the eeprom address registers. all eabhi and eablo bits read 0 and are not writable in normal modes. all eabhi and eablo bits are readable and writable in special modes. the mcu address bit ab0 is not stored in the eaddr registers since the eeprom block is not byte addressable. 4.3.2.9 eeprom data registers (edata) the edatahi and edatalo registers are the eeprom data registers. all edhi and edlo bits read 0 and are not writable in normal modes. 76543210 r00000 eabhi w reset 00000000 = unimplemented or reserved figure 4-13. eeprom address high register (eaddrhi) 76543210 r eablo w reset 00000000 = unimplemented or reserved figure 4-14. eeprom address low register (eaddrlo) 76543210 r edhi w reset 00000000 = unimplemented or reserved figure 4-15. eeprom data high register (edatahi) 76543210 r edlo w reset 00000000 = unimplemented or reserved figure 4-16. eeprom data low register (edatalo) 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 189 all edhi and edlo bits are readable and writable in special modes. 4.4 functional description 4.4.1 eeprom command operations write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. the program, erase, and sector modify algorithms are controlled by a state machine whose timebase, eeclk, is derived from the oscillator clock via a programmable divider. the command register as well as the associated address and data registers operate as a buffer and a register (2-stage fifo) so that a second command along with the necessary data and address can be stored to the buffer while the ?st command is still in progress. buffer empty as well as command completion are signalled by ?gs in the eeprom status register with interrupts generated, if enabled. the next sections describe: 1. how to write the eclkdiv register 2. command write sequences to program, erase, erase verify, sector erase abort, and sector modify operations on the eeprom memory 3. valid eeprom commands 4. effects resulting from illegal eeprom command write sequences or aborting eeprom operations 4.4.1.1 writing the eclkdiv register prior to issuing any eeprom command after a reset, the user is required to write the eclkdiv register to divide the oscillator clock down to within the 150 khz to 200 khz range. since the program and erase timings are also a function of the bus clock, the eclkdiv determination must take this information into account. if we de?e: eclk as the clock of the eeprom timing control block tbus as the period of the bus clock int(x) as taking the integer part of x (e.g., int(4.323)=4) then eclkdiv register bits prdiv8 and ediv[5:0] are to be set as described in figure 4-17 . for example, if the oscillator clock frequency is 950 khz and the bus clock frequency is 10 mhz, eclkdiv bits ediv[5:0] should be set to 0x04 (000100) and bit prdiv8 set to 0. the resulting eeclk frequency is then 190 khz. as a result, the eeprom program and erase algorithm timings are increased over the optimum target by: if the oscillator clock frequency is 16 mhz and the bus clock frequency is 40 mhz, eclkdiv bits ediv[5:0] should be set to 0x0a (001010) and bit prdiv8 set to 1. the resulting eeclk frequency is 200 190 () 200 ? 100 5% = 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 190 freescale semiconductor then 182 khz. in this case, the eeprom program and erase algorithm timings are increased over the optimum target by: caution program and erase command execution time will increase proportionally with the period of eeclk. because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the eeprom memory cannot be performed if the bus clock runs at less than 1 mhz. programming or erasing the eeprom memory with eeclk < 150 khz should be avoided. setting eclkdiv to a value such that eeclk < 150 khz can destroy the eeprom memory due to overstress. setting eclkdiv to a value such that (1/eeclk+tbus) < 5 s can result in incomplete programming or erasure of the eeprom memory cells. if the eclkdiv register is written, the edivld bit is set automatically. if the edivld bit is 0, the eclkdiv register has not been written since the last reset. if the eclkdiv register has not been written to, the eeprom command loaded during a command write sequence will not execute and the accerr ?g in the estat register will set. 200 182 () 200 ? 100 9% = 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 191 figure 4-17. determination procedure for prdiv8 and ediv bits prdiv8 = 1 yes no prdiv8 = 0 (reset) >12.8 mhz? eeclk = (prdclk)/(1+ediv[5:0]) prdclk = oscillator_clock prdclk = oscillator_clock/8 prdclk[mhz]*(5+tbus[ s]) no ediv[5:0]=prdclk[mhz]*(5+tbus[ s])? yes start tbus < 1 s? an integer? ediv[5:0]=int(prdclk[mhz]*(5+tbus[ s])) 1/eeclk[mhz] + tbus[ms] > 5 and eeclk > 0.15 mhz ? end yes no ediv[5:0] > 4? all commands impossible yes no all commands impossible no try to decrease tbus yes oscillator_clock 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 192 freescale semiconductor 4.4.1.2 command write sequence the eeprom command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. before starting a command write sequence, the accerr and pviol ?gs in the estat register must be clear (see section 4.3.2.6, ?eprom status register (estat) ) and the cbeif ?g should be tested to determine the state of the address, data and command buffers. if the cbeif ?g is set, indicating the buffers are empty, a new command write sequence can be started. if the cbeif ?g is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. a command write sequence consists of three steps which must be strictly adhered to with writes to the eeprom module not permitted between the steps. however, eeprom register and array reads are allowed during a command write sequence. the basic command write sequence is as follows: 1. write to one address in the eeprom memory. 2. write a valid command to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the command. the address written in step 1 will be stored in the eaddr registers and the data will be stored in the edata registers. if the cbeif ?g in the estat register is clear when the ?st eeprom array write occurs, the contents of the address and data buffers will be overwritten and the cbeif ?g will be set. when the cbeif ?g is cleared, the ccif ?g is cleared on the same bus cycle by the eeprom command controller indicating that the command was successfully launched. for all command write sequences except sector erase abort, the cbeif ?g will set four bus cycles after the ccif ?g is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. for sector erase abort operations, the cbeif ?g will remain clear until the operation completes. except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. the sector erase abort command is launched when the cbeif ?g is cleared as part of a sector erase abort command write sequence. once a command is launched, the completion of the command operation is indicated by the setting of the ccif ?g in the estat register. the ccif ?g will set upon completion of all active and buffered commands. 4.4.2 eeprom commands table 4-9 summarizes the valid eeprom commands along with the effects of the commands on the eeprom block. table 4-9. eeprom command description ecmdb command function on eeprom memory 0x05 erase verify verify all memory bytes in the eeprom block are erased. if the eeprom block is erased, the blank ?g in the estat register will set upon command completion. 0x20 program program a word (two bytes) in the eeprom block. 0x40 sector erase erase all four memory bytes in a sector of the eeprom block. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 193 caution an eeprom word (2 bytes) must be in the erased state before being programmed. cumulative programming of bits within a word is not allowed. 0x41 mass erase erase all memory bytes in the eeprom block. a mass erase of the full eeprom block is only possible when epopen and epdis bits in the eprot register are set prior to launching the command. 0x47 sector erase abort abort the sector erase operation. the sector erase operation will terminate according to a set procedure. the eeprom sector should not be considered erased if the accerr ?g is set upon command completion. 0x60 sector modify erase all four memory bytes in a sector of the eeprom block and reprogram the addressed word. table 4-9. eeprom command description ecmdb command function on eeprom memory 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 194 freescale semiconductor 4.4.2.1 erase verify command the erase verify operation will verify that the eeprom memory is erased. an example ?w to execute the erase verify operation is shown in figure 4-18 . the erase verify command write sequence is as follows: 1. write to an eeprom address to start the command write sequence for the erase verify command. the address and data written will be ignored. 2. write the erase verify command, 0x05, to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the erase verify command. after launching the erase verify command, the ccif ?g in the estat register will set after the operation has completed unless a new command write sequence has been buffered. the number of bus cycles required to execute the erase verify operation is equal to the number of words in the eeprom memory plus 14 bus cycles as measured from the time the cbeif ?g is cleared until the ccif ?g is set. upon completion of the erase verify operation, the blank ?g in the estat register will be set if all addresses in the eeprom memory are veri?d to be erased. if any address in the eeprom memory is not erased, the erase verify operation will terminate and the blank ?g in the estat register will remain clear. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 195 figure 4-18. example erase verify command flow write: eeprom address write: ecmd register erase verify command 0x05 write: estat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: estat register yes no access error and protection violation no and dummy data bit polling for command completion check read: estat register yes note: command write sequence aborted by writing 0x00 to estat register. note: command write sequence aborted by writing 0x00 to estat register. read: estat register no start yes check cbeif set? address, data, command buffer empty check ccif set? accerr/ pviol set? no erase verify status yes exit eeprom memory not erased exit eeprom memory erased blank set? write: eclkdiv register read: eclkdiv register yes no clock register written check edivld set? note: eclkdiv needs to be set once after each reset. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 196 freescale semiconductor 4.4.2.2 program command the program operation will program a previously erased word in the eeprom memory using an embedded algorithm. an example ?w to execute the program operation is shown in figure 4-19 . the program command write sequence is as follows: 1. write to an eeprom block address to start the command write sequence for the program command. the data written will be programmed to the address written. 2. write the program command, 0x20, to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the program command. if a word to be programmed is in a protected area of the eeprom memory, the pviol ?g in the estat register will set and the program command will not launch. once the program command has successfully launched, the ccif ?g in the estat register will set after the program operation has completed unless a new command write sequence has been buffered. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 197 figure 4-19. example program command flow write: eeprom address write: ecmd register program command 0x20 write: estat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: estat register yes no access error and protection violation no and program data bit polling for buffer empty check read: estat register yes note: command write sequence aborted by writing 0x00 to estat register. note: command write sequence aborted by writing 0x00 to estat register. read: estat register no start yes check cbeif set? address, data, command buffer empty check cbeif set? accerr/ pviol set? exit write: eclkdiv register read: eclkdiv register yes no clock register written check edivld set? note: eclkdiv needs to be set once after each reset. no yes sequential programming decision next word? no bit polling for command completion check read: estat register yes ccif set? 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 198 freescale semiconductor 4.4.2.3 sector erase command the sector erase operation will erase both words in a sector of eeprom memory using an embedded algorithm. an example ?w to execute the sector erase operation is shown in figure 4-20 . the sector erase command write sequence is as follows: 1. write to an eeprom memory address to start the command write sequence for the sector erase command. the eeprom address written determines the sector to be erased while global address bits [1:0] and the data written are ignored. 2. write the sector erase command, 0x40, to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the sector erase command. if an eeprom sector to be erased is in a protected area of the eeprom memory, the pviol ?g in the estat register will set and the sector erase command will not launch. once the sector erase command has successfully launched, the ccif ?g in the estat register will set after the sector erase operation has completed unless a new command write sequence has been buffered. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 199 figure 4-20. example sector erase command flow write: eeprom sector address write: ecmd register sector erase command 0x40 write: estat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: estat register yes no access error and protection violation and dummy data read: estat register note: command write sequence aborted by writing 0x00 to estat register. note: command write sequence aborted by writing 0x00 to estat register. read: estat register no start yes check cbeif set? address, data, command buffer empty check accerr/ pviol set? exit write: eclkdiv register read: eclkdiv register yes no clock register written check edivld set? note: eclkdiv needs to be set once after each reset. no bit polling for command completion check yes ccif set? 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 200 freescale semiconductor 4.4.2.4 mass erase command the mass erase operation will erase all addresses in an eeprom block using an embedded algorithm. an example ?w to execute the mass erase operation is shown in figure 4-21 . the mass erase command write sequence is as follows: 1. write to an eeprom memory address to start the command write sequence for the mass erase command. the address and data written will be ignored. 2. write the mass erase command, 0x41, to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the mass erase command. if the eeprom memory to be erased contains any protected area, the pviol ?g in the estat register will set and the mass erase command will not launch. once the mass erase command has successfully launched, the ccif ?g in the estat register will set after the mass erase operation has completed unless a new command write sequence has been buffered. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 201 figure 4-21. example mass erase command flow write: eeprom address write: ecmd register mass erase command 0x41 write: estat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: estat register yes no access error and protection violation and dummy data read: estat register note: command write sequence aborted by writing 0x00 to estat register. note: command write sequence aborted by writing 0x00 to estat register. read: estat register no start yes check cbeif set? address, data, command buffer empty check accerr/ pviol set? exit write: eclkdiv register read: eclkdiv register yes no clock register written check edivld set? note: eclkdiv needs to be set once after each reset. no bit polling for command completion check yes ccif set? 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 202 freescale semiconductor 4.4.2.5 sector erase abort command the sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an eeprom block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. an example ?w to execute the sector erase abort operation is shown in figure 4-22 . the sector erase abort command write sequence is as follows: 1. write to any eeprom memory address to start the command write sequence for the sector erase abort command. the address and data written are ignored. 2. write the sector erase abort command, 0x47, to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the sector erase abort command. if the sector erase abort command is launched resulting in the early termination of an active sector erase or sector modify operation, the accerr ?g will set once the operation completes as indicated by the ccif ?g being set. the accerr ?g sets to inform the user that the eeprom sector may not be fully erased and a new sector erase or sector modify command must be launched before programming any location in that speci? sector. if the sector erase abort command is launched but the active sector erase or sector modify operation completes normally, the accerr ?g will not set upon completion of the operation as indicated by the ccif ?g being set. if the sector erase abort command is launched after the sector modify operation has completed the sector erase step, the program step will be allowed to complete. the maximum number of cycles required to abort a sector erase or sector modify operation is equal to four eeclk periods (see section 4.4.1.1, ?riting the eclkdiv register ) plus ve bus cycles as measured from the time the cbeif ?g is cleared until the ccif ?g is set. note since the accerr bit in the estat register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. the cbeif ?g will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. if an attempt is made to start a new command write sequence with a sector erase abort operation active, the accerr ?g in the estat register will be set. a new command write sequence may be started after clearing the accerr ?g, if set. note the sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 203 figure 4-22. example sector erase abort command flow write: dummy eeprom address write: ecmd register sector erase abort cmd 0x47 write: estat register clear cbeif 0x80 1. 2. 3. read: estat register and dummy data bit polling for command completion check yes note: command write sequence aborted by writing 0x00 to estat register. note: command write sequence aborted by writing 0x00 to estat register. ccif set? execute sector erase/modify command flow no bit polling for command completion check read: estat register yes ccif set? no yes abort needed? erase clear accerr 0x10 write: estat register yes no access error check accerr set? sector erase or modify sector erase or modify no exit exit sector erase completed exit completed aborted 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 204 freescale semiconductor 4.4.2.6 sector modify command the sector modify operation will erase both words in a sector of eeprom memory followed by a reprogram of the addressed word using an embedded algorithm. an example ?w to execute the sector modify operation is shown in figure 4-23 . the sector modify command write sequence is as follows: 1. write to an eeprom memory address to start the command write sequence for the sector modify command. the eeprom address written determines the sector to be erased and word to be reprogrammed while byte address bit 0 is ignored. 2. write the sector modify command, 0x60, to the ecmd register. 3. clear the cbeif ?g in the estat register by writing a 1 to cbeif to launch the sector erase command. if an eeprom sector to be modi?d is in a protected area of the eeprom memory, the pviol ?g in the estat register will set and the sector modify command will not launch. once the sector modify command has successfully launched, the ccif ?g in the estat register will set after the sector modify operation has completed unless a new command write sequence has been buffered. 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 205 figure 4-23. example sector modify command flow write: eeprom word address write: ecmd register sector modify command 0x60 write: estat register clear cbeif 0x80 1. 2. 3. clear accerr/pviol 0x30 write: estat register yes no access error and protection violation and program data read: estat register note: command write sequence aborted by writing 0x00 to estat register. note: command write sequence aborted by writing 0x00 to estat register. read: estat register no start yes check cbeif set? address, data, command buffer empty check accerr/ pviol set? exit write: eclkdiv register read: eclkdiv register yes no clock register written check edivld set? note: eclkdiv needs to be set once after each reset. no bit polling for command completion check yes ccif set? 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 206 freescale semiconductor 4.4.3 illegal eeprom operations the accerr ?g will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. writing to an eeprom address before initializing the eclkdiv register. 2. writing a byte or misaligned word to a valid eeprom address. 3. starting a command write sequence while a sector erase abort operation is active. 4. writing to any eeprom register other than ecmd after writing to an eeprom address. 5. writing a second command to the ecmd register in the same command write sequence. 6. writing an invalid command to the ecmd register. 7. writing to an eeprom address after writing to the ecmd register. 8. writing to any eeprom register other than estat (to clear cbeif) after writing to the ecmd register. 9. writing a 0 to the cbeif ?g in the estat register to abort a command write sequence. the accerr ?g will not be set if any eeprom register is read during a valid command write sequence. the accerr ?g will also be set if any of the following events occur: 1. launching the sector erase abort command while a sector erase or sector modify operation is active which results in the early termination of the sector erase or sector modify operation (see section 4.4.2.5, ?ector erase abort command ). 2. the mcu enters stop mode and a command operation is in progress. the operation is aborted immediately and any pending command is purged (see section 4.5.2, ?top mode ). if the eeprom memory is read during execution of an algorithm (ccif = 0), the read operation will return invalid data and the accerr ?g will not be set. if the accerr ?g is set in the estat register, the user must clear the accerr ?g before starting another command write sequence (see section 4.3.2.6, ?eprom status register (estat) ). the pviol ?g will be set after the command is written to the ecmd register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. writing the program command if the address written in the command write sequence was in a protected area of the eeprom memory. 2. writing the sector erase command if the address written in the command write sequence was in a protected area of the eeprom memory. 3. writing the mass erase command to the eeprom memory while any eeprom protection is enabled. 4. writing the sector modify command if the address written in the command write sequence was in a protected area of the eeprom memory. if the pviol ?g is set in the estat register, the user must clear the pviol ?g before starting another command write sequence (see section 4.3.2.6, ?eprom status register (estat) ). 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 207 4.5 operating modes 4.5.1 wait mode if a command is active (ccif = 0) when the mcu enters the wait mode, the active command and any buffered command will be completed. the eeprom module can recover the mcu from wait mode if the cbeif and ccif interrupts are enabled (see section 4.8, ?nterrupts ). 4.5.2 stop mode if a command is active (ccif = 0) when the mcu enters the stop mode, the operation will be aborted and, if the operation is program, sector erase, mass erase, or sector modify, the eeprom array data being programmed or erased may be corrupted and the ccif and accerr ?gs will be set. if active, the high voltage circuitry to the eeprom memory will immediately be switched off when entering stop mode. upon exit from stop mode, the cbeif ?g is set and any buffered command will not be launched. the accerr ?g must be cleared before starting a command write sequence (see section 4.4.1.2, ?ommand write sequence ). note as active commands are immediately aborted when the mcu enters stop mode, it is strongly recommended that the user does not use the stop instruction during program, sector erase, mass erase, or sector modify operations. 4.5.3 background debug mode in background debug mode (bdm), the eprot register is writable. if the mcu is unsecured, then all eeprom commands listed in table 4-9 can be executed. if the mcu is secured and is in special single chip mode, the only command available to execute is mass erase. 4.6 eeprom module security the eeprom module does not provide any security information to the mcu. after each reset, the security state of the mcu is a function of information provided by the flash module (see the speci? ftx block guide). 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 208 freescale semiconductor 4.6.1 unsecuring the mcu in special single chip mode using bdm before the mcu can be unsecured in special single chip mode, the eeprom memory must be erased using the following method : reset the mcu into special single chip mode, delay while the erase test is performed by the bdm secure rom, send bdm commands to disable protection in the eeprom module, and execute a mass erase command write sequence to erase the eeprom memory. after the ccif ?g sets to indicate that the eeprom mass operation has completed and assuming that the flash memory has also been erased, reset the mcu into special single chip mode. the bdm secure rom will verify that the flash and eeprom memory are erased and will assert the unsec bit in the bdm status register. this bdm action will cause the mcu to override the flash security state and the mcu will be unsecured. once the mcu is unsecured, bdm commands will be enabled and the flash security byte may be programmed to the unsecure state. 4.7 resets 4.7.1 eeprom reset sequence on each reset, the eeprom module executes a reset sequence to hold cpu activity while loading the eprot register from the eeprom memory according to table 4-1 . 4.7.2 reset while eeprom command active if a reset occurs while any eeprom command is in progress, that command will be immediately aborted. the state of a word being programmed or the sector / block being erased is not guaranteed. 4.8 interrupts the eeprom module can generate an interrupt when all eeprom command operations have completed, when the eeprom address, data, and command buffers are empty. note vector addresses and their relative interrupt priority are determined at the mcu level. table 4-10. eeprom interrupt sources interrupt source interrupt flag local enable global (ccr) mask eeprom address, data, and command buffers empty cbeif (estat register) cbeie (ecnfg register) i bit all eeprom commands completed ccif (estat register) ccie (ecnfg register) i bit 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 209 4.8.1 description of eeprom interrupt operation the logic used for generating interrupts is shown in figure 4-24 . the eeprom module uses the cbeif and ccif ?gs in combination with the cbie and ccie enable bits to generate the eeprom command interrupt request. figure 4-24. eeprom interrupt implementation for a detailed description of the register bits, refer to section 4.3.2.4, ?eprom con?uration register (ecnfg) and section 4.3.2.6, ?eprom status register (estat) . eeprom command interrupt request cbeie cbeif ccie ccif 4 .com u datasheet
chapter 4 4 kbyte eeprom module (s12xeetx4kv2) MC9S12XHZ512 data sheet, rev. 1.02 210 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 211 chapter 5 xgate (s12xgatev2) 5.1 introduction the xgate module is a peripheral co-processor that allows autonomous data transfers between the mcus peripherals and the internal memories. it has a built in risc core that is able to pre-process the transferred data and perform complex communication protocols. the xgate module is intended to increase the mcus data throughput by lowering the s12x_cpus interrupt load. figure 5-1 gives an overview on the xgate architecture. this document describes the functionality of the xgate module, including: xgate registers ( section 5.3, ?emory map and register de?ition ) xgate risc core ( section 5.4.1, ?gate risc core ) hardware semaphores ( section 5.4.4, ?emaphores ) interrupt handling ( section 5.5, ?nterrupts ) debug features ( section 5.6, ?ebug mode ) security ( section 5.7, ?ecurity ) instruction set ( section 5.8, ?nstruction set ) 5.1.1 glossary of terms xgate request a service request from a peripheral module which is directed to the xgate by the s12x_int module (see figure 5-1 ). xgate channel the resources in the xgate module (i.e. channel id number, priority level, service request vector, interrupt flag) which are associated with a particular xgate request. xgate channel id a 7-bit identi?r associated with an xgate channel. in s12x designs valid channel ids range from $78 to $09. xgate channel interrupt an s12x_cpu interrupt that is triggered by a code sequence running on the xgate module. xgate software channel 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 212 freescale semiconductor special xgate channel that is not associated with any peripheral service request. a software channel is triggered by its software trigger bit which is implemented in the xgate module. xgate semaphore a set of hardware ?p-?ps that can be exclusively set by either the s12x_cpu or the xgate. (see 5.4.4/5-232 ) xgate thread a code sequence which is executed by the xgates risc core after receiving an xgate request. xgate debug mode a special mode in which the xgates risc core is halted for debug purposes. this mode enables the xgates debug features (see 5.6/5-234 ). xgate software error the xgate is able to detect a number of error conditions caused by erratic software (see 5.4.5/5-233 ). these error conditions will cause the xgate to seize program execution and ?g an interrupt to the s12x_cpu. word a 16 bit entity. byte an 8 bit entity. 5.1.2 features the xgate module includes these features: data movement between various targets (i.e flash, ram, and peripheral modules) data manipulation through built in risc core provides up to 112 xgate channels 104 hardware triggered channels 8 software triggered channels hardware semaphores which are shared between the s12x_cpu and the xgate module able to trigger s12x_cpu interrupts upon completion of an xgate transfer software error detection to catch erratic application code 5.1.3 modes of operation there are four run modes on s12x devices. run mode, wait mode, stop mode the xgate is able to operate in all of these three system modes. clock activity will be automatically stopped when the xgate module is idle. freeze mode (bdm active) 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 213 in freeze mode all clocks of the xgate module may be stopped, depending on the module configuration (see section 5.3.1.1, ?gate control register (xgmctl) ). 5.1.4 block diagram figure figure 5-1 shows a block diagram of the xgate. figure 5-1. xgate block diagram 5.2 external signal description the xgate module has no external pins. interrupts xgate requests risc core s12x_mmc xgate peripherals semaphores interrupt flags software triggers peripheral interrupts s12x_dbg data/code software triggers xgate s12x_int 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 214 freescale semiconductor 5.3 memory map and register de?ition this section provides a detailed description of address space and registers used by the xgate module. the memory map for the xgate module is given below in figure 5-2 .the address listed for each register is the sum of a base address and an address offset. the base address is de?ed at the soc level and the address offset is de?ed at the module level. reserved registers read zero. write accesses to the reserved registers have no effect. 5.3.1 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name 1514131211109876543210 0x0000 xgmctl r00000000 xge xgfrz xgdbg xgss xg fact 0 xg sweif xgie w xgem xg frzm xg dbgm xgssm xg factm xg sweifm xgiem 0x0002 xgmchid r 0 xgchid[6:0] w 0x0003 reserved r w 0x0004 reserved r w 0x0005 reserved r w 0x0006 xgvbr r xgvbr[15:1] 0 w = unimplemented or reserved figure 5-2. xgate register summary (sheet 1 of 3) 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 215 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 0x0008 xgif r0000000 xgif_78 xgf_77 xgif_76 xgif_75 xgif_74 xgif_73 xgif_72 xgif_71 xgif_70 w 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 0x000a xgif r xgif_6f xgif_6e xgif_6d xgif_6c xgif_6b xgif_6a xgif_69 xgif_68 xgf_67 xgif_66 xgif_65 xgif_64 xgif_63 xgif_62 xgif_61 xgif_60 w 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 0x000c xgif r xgif_5f xgif_5e xgif_5d xgif_5c xgif_5b xgif_5a xgif_59 xgif_58 xgf_57 xgif_56 xgif_55 xgif_54 xgif_53 xgif_52 xgif_51 xgif_50 w 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 0x000e xgif r xgif_4f xgif_4e xgif_4d xgif_4c xgif_4b xgif_4a xgif_49 xgif_48 xgf _47 xgif_46 xgif_45 xgif_44 xgif_43 xgif_42 xgif_41 xgif_40 w register name 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 0x0010 xgif r xgif_3f xgif_3e xgif_3d xgif_3c xgif_3b xgif_3a xgif_39 xgif_38 xgf _37 xgif_36 xgif_35 xgif_34 xgif_33 xgif_32 xgif_31 xgif_30 w 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 0x0012 xgif r xgif_2f xgif_2e xgif_2d xgif_2c xgif_2b xgif_2a xgif_29 xgif_28 xgf _27 xgif_26 xgif_25 xgif_24 xgif_23 xgif_22 xgif_21 xgif_20 w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x0014 xgif r xgif_1f xgif_1e xgif_1d xgif_1c xgif_1b xgif_1a xgif_19 xgif_18 xgf _17 xgif_16 xgif_15 xgif_14 xgif_13 xgif_12 xgif_11 xgif_10 w 1514131211109876543210 0x0016 xgif r xgif_0f xgif_0e xgif_0d xgif_0c xgif_0b xgif_0a xgif_09 0 0 0 0 0 0 0 0 0 w = unimplemented or reserved figure 5-2. xgate register summary (sheet 2 of 3) 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 216 freescale semiconductor 1514131211109876543210 0x0018 xgswtm r00000000 xgswt[7:0] w xgswtm[7:0] 0x001a xgsemm r00000000 xgsem[7:0] w xgsemm[7:0] 0x001c reserved r w 0x001d xgccr r 0000 xgn xgz xgv xgc w 0x001e xgpc r xgpc w 0x0020 reserved r w 0x0021 reserved r w 0x0022 xgr1 r xgr1 w 0x0024 xgr2 r xgr2 w 0x0026 xgr3 r xgr3 w 0x0028 xgr4 r xgr4 w 0x002a xgr5 r xgr5 w 0x002c xgr6 r xgr6 w 0x002e xgr7 r xgr7 w = unimplemented or reserved figure 5-2. xgate register summary (sheet 3 of 3) 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 217 5.3.1.1 xgate control register (xgmctl) all module level switches and flags are located in the module control register figure 5-3 . read: anytime write: anytime module base +0x00000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 xge xgfrz xgdbg xgss xgfact 0 xg sweif xgie w xgem xg frzm xg dbgm xg ssm xg factm xg sweifm xgiem reset 0 0 0 0 000000000000 = unimplemented or reserved figure 5-3. xgate control register (xgmctl) table 5-1. xgmctl field descriptions (sheet 1 of 3) field description 15 xgem xge mask this bit controls the write access to the xge bit. the xge bit can only be set or cleared if a "1" is written to the xgem bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xge in the same bus cycle 1 enable write access to the xge in the same bus cycle 14 xgfrzm xgfrz mask this bit controls the write access to the xgfrz bit. the xgfrz bit can only be set or cleared if a "1" is written to the xgfrzm bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xgfrz in the same bus cycle 1 enable write access to the xgfrz in the same bus cycle 13 xgdbgm xgdbg mask this bit controls the write access to the xgdbg bit. the xgdbg bit can only be set or cleared if a "1" is written to the xgdbgm bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xgdbg in the same bus cycle 1 enable write access to the xgdbg in the same bus cycle 12 xgssm xgss mask this bit controls the write access to the xgss bit. the xgss bit can only be set or cleared if a "1" is written to the xgssm bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xgss in the same bus cycle 1 enable write access to the xgss in the same bus cycle 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 218 freescale semiconductor 11 xgfactm xgfact mask ?this bit controls the write access to the xgfact bit. the xgfact bit can only be set or cleared if a "1" is written to the xgfactm bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xgfact in the same bus cycle 1 enable write access to the xgfact in the same bus cycle 9 xgsweifm xgsweif mask this bit controls the write access to the xgsweif bit. the xgsweif bit can only be cleared if a "1" is written to the xgsweifm bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xgsweif in the same bus cycle 1 enable write access to the xgsweif in the same bus cycle 8 xgiem xgie mask this bit controls the write access to the xgie bit. the xgie bit can only be set or cleared if a "1" is written to the xgiem bit in the same register access. read: this bit will always read "0". write: 0 disable write access to the xgie in the same bus cycle 1 enable write access to the xgie in the same bus cycle 7 xge xgate module enable ?this bit enables the xgate module. if the xgate module is disabled, pending xgate requests will be ignored. the thread that is executed by the risc core while the xge bit is cleared will continue to run. read: 0 xgate module is disabled 1 xgate module is enabled write: 0 disable xgate module 1 enable xgate module 6 xgfrz halt xgate in freeze mode ?the xgfrz bit controls the xgate operation in freeze mode (bdm active). read: 0 risc core operates normally in freeze (bdm active) 1 risc core stops in freeze mode (bdm active) write: 0 don? stop risc core in freeze mode (bdm active) 1 stop risc core in freeze mode (bdm active) 5 xgdbg xgate debug mode this bit indicates that the xgate is in debug mode (see section 5.6, ?ebug mode ). debug mode can be entered by software breakpoints (brk instruction), tagged or forced breakpoints (see s12x_dbg section ), or by writing a "1" to this bit. read: 0 risc core is not in debug mode 1 risc core is in debug mode write: 0 leave debug mode 1 enter debug mode note: freeze mode and software error interrupts have no effect on the xgdbg bit. table 5-1. xgmctl field descriptions (sheet 2 of 3) field description 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 219 4 xgss xgate single step this bit forces the execution of a single instruction if the xgate is in debug mode and no software error has occurred (xgsweif cleared). read: 0 no single step in progress 1 single step in progress write 0 no effect 1 execute a single risc instruction note: invoking a single step will cause the xgate to temporarily leave debug mode until the instruction has been executed. 3 xgfact fake xgate activity this bit forces the xgate to ?g activity to the mcu even when it is idle. when it is set the mcu will never enter system stop mode which assures that peripheral modules will be clocked during xgate idle periods read: 0 xgate will only ?g activity if it is not idle or in debug mode. 1 xgate will always signal activity to the mcu. write: 0 only ?g activity if not idle or in debug mode. 1 always signal xgate activity. 1 xgsweif xgate software error interrupt flag this bit signals a pending software error interrupt. it is set if the risc core detects an error condition (see section 5.4.5, ?oftware error detection ). the risc core is stopped while this bit is set. clearing this bit will terminate the current thread and cause the xgate to become idle. read: 0 software error interrupt is not pending 1 software error interrupt is pending if xgie is set write: 0 no effect 1 clears the xgsweif bit 0 xgie xgate interrupt enable ?this bit acts as a global interrupt enable for the xgate module read: 0 all xgate interrupts disabled 1 all xgate interrupts enabled write: 0 disable all xgate interrupts 1 enable all xgate interrupts table 5-1. xgmctl field descriptions (sheet 3 of 3) field description 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 220 freescale semiconductor 5.3.1.2 xgate channel id register (xgchid) the xgate channel id register ( figure 5-4 ) shows the identi?r of the xgate channel that is currently active. this register will read ?00 if the xgate module is idle. in debug mode this register can be used to start and terminate threads (see section 5.6.1, ?ebug features ). read: anytime write: in debug mode 5.3.1.3 xgate vector base address register (xgvbr) the vector base address register ( figure 5-5 and figure 5-6 ) determines the location of the xgate vector block. read: anytime write: only if the module is disabled (xge = 0) and idle (xgchid = $00)) module base +0x0002 76543210 r 0 xgchid[6:0] w reset 0 0 0 00000 = unimplemented or reserved figure 5-4. xgate channel id register (xgchid) table 5-2. xgchid field descriptions field description 6? xgchid[6:0] request identi?r ?id of the currently active channel module base +0x0006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgvbr[15:1] 0 w reset 0 0 0 0 000000000000 = unimplemented or reserved figure 5-5. xgate vector base address register (xgvbr) table 5-3. xgvbr field descriptions field description 15? xbvbr[15:1] vector base address ?the xgvbr register holds the start address of the vector block in the xgate memory map. 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 221 5.3.1.4 xgate channel interrupt flag vector (xgif) the interrupt ?g vector ( figure 5-6 ) provides access to the interrupt ?gs bits of each channel. each ?g may be cleared by writing a "1" to its bit location. read: anytime module base +0x0008 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 r0000000 xgif_78 xgf_77 xgif_76 xgif_75 xgif_74 xgif_73 xgif_72 xgif_71 xgif_70 w reset 0 0 0 0 000000000000 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 r xgif_6f xgif_6e xgif_6d xgif_6c xgif_6b xgif_6a xgif_69 xgif_68 xgf_67 xgif_66 xgif_65 xgif_64 xgif_63 xgif_62 xgif_61 xgif_60 w reset 0 0 0 0 000000000000 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 r xgif_5f xgif_5e xgif_5d xgif_5c xgif_5b xgif_5a xgif_59 xgif_58 xgf_57 xgif_56 xgif_55 xgif_54 xgif_53 xgif_52 xgif_51 xgif_50 w reset 0 0 0 0 000000000000 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 r xgif_4f xgif_4e xgif_4d xgif_4c xgif_4b xgif_4a xgif_49 xgif_48 xgf _47 xgif_46 xgif_45 xgif_44 xgif_43 xgif_42 xgif_41 xgif_40 w reset 0 0 0 0 000000000000 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 r xgif_3f xgif_3e xgif_3d xgif_3c xgif_3b xgif_3a xgif_39 xgif_38 xgf _37 xgif_36 xgif_35 xgif_34 xgif_33 xgif_32 xgif_31 xgif_30 w reset 0 0 0 0 000000000000 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 r xgif_2f xgif_2e xgif_2d xgif_2c xgif_2b xgif_2a xgif_29 xgif_28 xgf _27 xgif_26 xgif_25 xgif_24 xgif_23 xgif_22 xgif_21 xgif_20 w reset 0 0 0 0 000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r xgif_1f xgif_1e xgif_1d xgif_1c xgif_1b xgif_1a xgif_19 xgif_18 xgf _17 xgif_16 xgif_15 xgif_14 xgif_13 xgif_12 xgif_11 xgif_10 w reset 0 0 0 0 000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgif_0f xgif_0e xgif_0d xgif_0c xgif_0b xgif_0a xgif_09 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 000000000000 = unimplemented or reserved figure 5-6. xgate channel interrupt flag vector (xgif) 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 222 freescale semiconductor write: anytime note suggested mnemonics for accessing the interrupt ?g vector on a word basis are: xgif_7f_70 (xgif[127:112]), xgif_6f_60 (xgif[111:96]), xgif_5f_50 (xgif[95:80]), xgif_4f_40 (xgif[79:64]), xgif_3f_30 (xgif[63:48]), xgif_2f_20 (xgif[47:32]), xgif_1f_10 (xgif[31:16]), xgif_0f_00 (xgif[15:0]) table 5-4. xgiv field descriptions field description 127? xgif[78:9] channel interrupt flags ?these bits signal pending channel interrupts. they can only be set by the risc core. each ?g can be cleared by writing a "1" to its bit location. unimplemented interrupt ?gs will always read "0". refer to section ?nterrupts?of the soc guide for a list of implemented interrupts. read: 0 channel interrupt is not pending 1 channel interrupt is pending if xgie is set write: 0 no effect 1 clears the interrupt ?g 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 223 5.3.1.5 xgate software trigger register (xgswt) the eight software triggers of the xgate module can be set and cleared through the xgate software trigger register ( figure 5-7 ). the upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. these bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle. read: anytime write: anytime note the xgate channel ids that are associated with the eight software triggers are determined on chip integration level. (see section ?nterrupts of the soc guide ) xgate software triggers work like any peripheral interrupt. they can be used as xgate requests as well as s12x_cpu interrupts. the target of the software trigger must be selected in the s12x_int module. module base +0x00018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 xgswt[7:0] w xgswtm[7:0] reset 0 0 0 0 000000000000 figure 5-7. xgate software trigger register (xgswt) table 5-5. xgswt field descriptions field description 15? xgswtm[7:0] software trigger mask these bits control the write access to the xgswt bits. each xgswt bit can only be written if a "1" is written to the corresponding xgswtm bit in the same access. read: these bits will always read "0". write: 0 disable write access to the xgswt in the same bus cycle 1 enable write access to the corresponding xgswt bit in the same bus cycle 7? xgswt[7:0] software trigger bits ?these bits act as interrupt ?gs that are able to trigger xgate software channels. they can only be set and cleared by software. read: 0 no software trigger pending 1 software trigger pending if the xgie bit is set write: 0 clear software trigger 1 set software trigger 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 224 freescale semiconductor 5.3.1.6 xgate semaphore register (xgsem) the xgate provides a set of eight hardware semaphores that can be shared between the s12x_cpu and the xgate risc core. each semaphore can either be unlocked, locked by the s12x_cpu or locked by the risc core. the risc core is able to lock and unlock a semaphore through its ssem and csem instructions. the s12x_cpu has access to the semaphores through the xgate semaphore register ( figure 5-8 ). refer to section section 5.4.4, ?emaphores for details. read: anytime write: anytime (see section 5.4.4, ?emaphores ) module base +0x0001a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r00000000 xgsem[7:0] w xgsemm[7:0] reset 0 0 0 0 000000000000 figure 5-8. xgate semaphore register (xgsem) table 5-6. xgsem field descriptions field description 15? xgsemm[7:0] semaphore mask ?these bits control the write access to the xgsem bits. read: these bits will always read "0". write: 0 disable write access to the xgsem in the same bus cycle 1 enable write access to the xgsem in the same bus cycle 7? xgsem[7:0] semaphore bits these bits indicate whether a semaphore is locked by the s12x_cpu. a semaphore can be attempted to be set by writing a "1" to the xgsem bit and to the corresponding xgsemm bit in the same write access. only unlocked semaphores can be set. a semaphore can be cleared by writing a "0" to the xgsem bit and a "1" to the corresponding xgsemm bit in the same write access. read: 0 semaphore is unlocked or locked by the risc core 1 semaphore is locked by the s12x_cpu write: 0 clear semaphore if it was locked by the s12x_cpu 1 attempt to lock semaphore by the s12x_cpu 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 225 5.3.1.7 xgate condition code register (xgccr) the xgccr register ( figure 5-9 ) provides access to the risc cores condition code register. read: in debug mode if unsecured write: in debug mode if unsecured module base +0x001d 76543210 r0000 xgn xgz xgv xgc w reset 0 0 0 00000 = unimplemented or reserved figure 5-9. xgate condition code register (xgccr) table 5-7. xgccr field descriptions field description 3 xgn sign flag ?the risc cores sign ?g 2 xgz zero flag ?the risc cores zero ?g 1 xgv over?w flag ?the risc cores over?w ?g 0 xgc carry flag ?the risc cores carry ?g 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 226 freescale semiconductor 5.3.1.8 xgate program counter register (xgpc) the xgpc register ( figure 5-10 ) provides access to the risc cores program counter. read: in debug mode if unsecured write: in debug mode if unsecured 5.3.1.9 xgate register 1 (xgr1) the xgr1 register ( figure 5-12 ) provides access to the risc cores register 1. read: in debug mode if unsecured write: in debug mode if unsecured module base +0x0001e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgpc w reset 0 0 0 0 000000000000 figure 5-10. xgate program counter register (xgpc) figure 5-11. table 5-8. xgpc field descriptions field description 15? xgpc[15:0] program counter ?the risc cores program counter module base +0x00022 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr1 w reset 0 0 0 0 000000000000 figure 5-12. xgate register 1 (xgr1) table 5-9. xgr1 field descriptions field description 15? xgr1[15:0] xgate register 1 ?the risc cores register 1 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 227 5.3.1.10 xgate register 2 (xgr2) the xgr2 register ( figure 5-13 ) provides access to the risc cores register 2. read: in debug mode if unsecured write: in debug mode if unsecured 5.3.1.11 xgate register 3 (xgr3) the xgr3 register ( figure 5-14 ) provides access to the risc cores register 3. read: in debug mode if unsecured write: in debug mode if unsecured module base +0x00024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr2 w reset 0 0 0 0 000000000000 figure 5-13. xgate register 2 (xgr2) table 5-10. xgr2 field descriptions field description 15? xgr2[15:0] xgate register 2 ?the risc cores register 2 module base +0x00026 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr3 w reset 0 0 0 0 000000000000 figure 5-14. xgate register 3 (xgr3) table 5-11. xgr3 field descriptions field description 15? xgr3[15:0] xgate register 3 ?the risc cores register 3 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 228 freescale semiconductor 5.3.1.12 xgate register 4 (xgr4) the xgr4 register ( figure 5-15 ) provides access to the risc cores register 4. read: in debug mode if unsecured write: in debug mode if unsecured 5.3.1.13 xgate register 5 (xgr5) the xgr5 register ( figure 5-16 ) provides access to the risc cores register 5. read: in debug mode if unsecured write: in debug mode if unsecured module base +0x00028 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr4 w reset 0 0 0 0 000000000000 figure 5-15. xgate register 4 (xgr4) table 5-12. xgr4 field descriptions field description 15? xgr4[15:0] xgate register 4 ?the risc cores register 4 module base +0x0002a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr5 w reset 0 0 0 0 000000000000 figure 5-16. xgate register 5 (xgr5) table 5-13. xgr5 field descriptions field description 15? xgr5[15:0] xgate register 5 ?the risc cores register 5 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 229 5.3.1.14 xgate register 6 (xgr6) the xgr6 register ( figure 5-17 ) provides access to the risc cores register 6. read: in debug mode if unsecured write: in debug mode if unsecured 5.3.1.15 xgate register 7 (xgr7) the xgr7 register ( figure 5-18 ) provides access to the risc cores register 7. read: in debug mode if unsecured write: in debug mode if unsecured module base +0x0002c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr6 w reset 0 0 0 0 000000000000 figure 5-17. xgate register 6 (xgr6) table 5-14. xgr6 field descriptions field description 15? xgr6[15:0] xgate register 6 ?the risc cores register 6 module base +0x0002e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r xgr7 w reset 0 0 0 0 000000000000 figure 5-18. xgate register 7 (xgr7) table 5-15. xgr7 field descriptions field description 15? xgr7[15:0] xgate register 7 ?the risc cores register 7 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 230 freescale semiconductor 5.4 functional description the core of the xgate module is a risc processor which is able to access the mcus internal memories and peripherals (see figure 5-1 ). the risc processor always remains in an idle state until it is triggered by an xgate request. then it executes a code sequence that is associated with the request and optionally triggers an interrupt to the s12x_cpu upon completion. code sequences are not interruptible. a new xgate request can only be serviced when the previous sequence is ?ished and the risc core becomes idle. the xgate module also provides a set of hardware semaphores which are necessary to ensure data consistency whenever ram locations or peripherals are shared with the s12x_cpu. the following sections describe the components of the xgate module in further detail. 5.4.1 xgate risc core the risc core is a 16 bit processor with an instruction set that is well suited for data transfers, bit manipulations, and simple arithmetic operations (see section 5.8, ?nstruction set ). it is able to access the mcus internal memories and peripherals without blocking these resources from the s12x_cpu 1 . whenever the s12x_cpu and the risc core access the same resource, the risc core will be stalled until the resource becomes available again 1 . the xgate offers a high access rate to the mcus internal ram. depending on the bus load, the risc core can perform up to two ram accesses per s12x_cpu bus cycle. bus accesses to peripheral registers or ?sh are slower. a transfer rate of one bus access per s12x_cpu cycle can not be exceeded. the xgate module is intended to execute short interrupt service routines that are triggered by peripheral modules or by software. 5.4.2 programmers model figure 5-19. programmers model 1. with the exception of prr registers (see section ?12x_mmc?. r7 r6 r5 r4 r3 r2 r1 r0 = 0 vc register block program counter condition code register 15 15 15 15 15 15 15 15 0 0 0 0 0 0 0 0 1 0 (variable pointer) pc 15 0 nz 3 2 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 231 the programmers model of the xgate risc core is shown in figure 5-19 . the processor offers a set of seven general purpose registers (r1 - r7), which serve as accumulators and index registers. an additional eighth register (r0) is tied to the value ?0000? register r1 has an additional functionality. it is preloaded with the initial variable pointer of the channels service request vector (see figure 5-20 ). the initial content of the remaining general purpose registers is unde?ed. the 16 bit program counter allows the addressing of a 64 kbyte address space. the condition code register contains four bits: the sign bit (s), the zero ?g (z), the over?w ?g (v), and the carry bit (c). the initial content of the condition code register is unde?ed. 5.4.3 memory map the xgates risc core is able to access an address space of 64k bytes. the allocation of memory blocks within this address space is determined on chip level. refer to the s12x_mmc section for a detailed information. the xgate vector block assigns a start address and a variable pointer to each xgate channel. its position in the xgate memory map can be adjusted through the xgvbr register (see section 5.3.1.3, ?gate vector base address register (xgvbr) ). figure 5-20 shows the layout of the vector block. each vector consists of two 16 bit words. the ?st contains the start address of the service routine. this value will be loaded into the program counter before a service routine is executed. the second word is a pointer to the service routines variable space. this value will be loaded into register r1 before a service routine is executed. figure 5-20. xgate vector block +$0000 unused +$0024 +$0028 +$002c +$0030 +$01e0 code variables code variables xgvbr channel $0a initial program counter channel $0a initial variable pointer channel $09 initial program counter channel $09 initial variable pointer channel $0b initial program counter channel $0b initial variable pointer channel $0c initial program counter channel $0c initial variable pointer channel $78 initial program counter channel $78 initial variable pointer 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 232 freescale semiconductor 5.4.4 semaphores the xgate module offers a set of eight hardware semaphores. these semaphores provide a mechanism to protect system resources that are shared between two concurrent threads of program execution; one thread running on the s12x_cpu and one running on the xgate risc core. each semaphore can only be in one of the three states: ?nlocked? ?ocked by s12x_cpu? and ?ocked by xgate? the s12x_cpu can check and change a semaphores state through the xgate semaphore register (xgsem, see section 5.3.1.6, ?gate semaphore register (xgsem) ). the risc core does this through its ssem and csem instructions. figure 5-21 illustrates the valid state transitions. figure 5-21. semaphore state transitions unlocked locked by s12x_cpu locked by xgate csem instruction %0 ? xgsem csem instruction ssem instruction %1 ? xgsem ssem instruction %0 ? xgsem %1 ? xgsem csem instruction %0 ? xgsem %1 ? xgsem ssem instruction or %1 ? xgsem and ssem instr. 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 233 figure 5-22 gives an example of the typical usage of the xgate hardware semaphores. two concurrent threads are running on the system. one is running on the s12x_cpu and the other is running on the risc core. they both have a critical section of code that accesses the same system resource. to guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown. figure 5-22. algorithm for locking and releasing semaphores 5.4.5 software error detection the xgate module will immediately terminate program execution after detecting an error condition caused by erratic application code. there are three error conditions: execution of an illegal opcode illegal vector or opcode fetches illegal load or store accesses all opcodes which are not listed in section section 5.8, ?nstruction set are illegal opcodes. illegal vector and opcode fetches as well as illegal load and store accesses are de?ed on chip level. refer to the s12x_mmc section for a detailed information. ssem xgsem %1? xgsem ? %0 bcc? %1 ? xgsem x csem ......... ......... ......... ......... critical code sequence critical code sequence s12x_cpu xgate 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 234 freescale semiconductor 5.5 interrupts 5.5.1 incoming interrupt requests xgate threads are triggered by interrupt requests which are routed to the xgate module (see s12x_int section). only a subset of the mcus interrupt requests can be routed to the xgate. which speci? interrupt requests these are and which channel id they are assigned to is documented in section ?nterrupts?of the soc guide . 5.5.2 outgoing interrupt requests there are three types of interrupt requests which can be triggered by the xgate module: 5. channel interrupts for each xgate channel there is an associated interrupt ?g in the xgate interrupt ?g vector (xgif, see section 5.3.1.4, ?gate channel interrupt flag vector (xgif) ). these ?gs can be set through the "sif" instruction by the risc core. they are typically used to ?g an interrupt to the s12x_cpu when the xgate has completed one of its tasks. 6. software triggers software triggers are interrupt ?gs, which can be set and cleared by software (see section 5.3.1.5, ?gate software trigger register (xgswt) ). they are typically used to trigger xgate tasks by the s12x_cpu software. however these interrupts can also be routed to the s12x_cpu (see s12x_int section ) and triggered by the xgate software. 7. software error interrupt the software error interrupt signals to the s12x_cpu the detection of an error condition in the xgate application code (see section 5.4.5, ?oftware error detection ). all xgate interrupts can be disabled by the xgie bit in the xgate module control register (xgmctl, see section 5.3.1.1, ?gate control register (xgmctl) ). 5.6 debug mode the xgate debug mode is a feature to allow debugging of application code. 5.6.1 debug features in debug mode the risc core will be halted and the following debug features will be enabled: read and write accesses to risc core registers (xgccr, xgpc, xgr1?gr7) 1 all risc core registers can be modified. leaving debug mode will cause the risc core to continue program execution with the modified register values. 1. only possible if mcu is unsecured 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 235 single stepping writing a "1" to the xgss bit will call the risc core to execute a single instruction. all risc core registers will be updated accordingly. write accesses to the xgchid register three operations can be performed by writing to the xgchid register: change of channel id if a non-zero value is written to the xgchid while a thread is active (xgchid $00), then the current channel id will be changed without any in?ence on the program counter or the other risc core registers. start of a thread if a non-zero value is written to the xgchid while the xgate is idle (xgchid = $00), then the thread that is associated with the new channel id will be executed upon leaving debug mode. termination of a thread if zero is written to the xgchid while a thread is active (xgchid $00), then the current thread will be terminated and the xgate will become idle. 5.6.2 entering debug mode debug mode can be entered in four ways: 1. setting xgdbg to "1" writing a "1" to xgdbg and xgdbgm in the same write access causes the xgate to enter debug mode upon completion of the current instruction. note after writing to the xgdbg bit the xgate will not immediately enter debug mode. depending on the instruction that is executed at this time there may be a delay of several clock cycles. the xgdbg will read "0" until debug mode is entered. 2. software breakpoints xgate programs which are stored in the internal ram allow the use of software breakpoints. a software breakpoint is set by replacing an instruction of the program code with the "brk" instruction. as soon as the program execution reaches the "brk" instruction, the xgate enters debug mode. additionally a software breakpoint request is sent to the s12x_dbg module (see section 4.9 of the s12x_dbg section ). upon entering debug mode, the program counter will point to the "brk" instruction. the other risc core registers will hold the result of the previous instruction. to resume program execution, the "brk" instruction must be replaced by the original instruction before leaving debug mode. 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 236 freescale semiconductor 3. tagged breakpoints the s12x_dbg module is able to place tags on fetched opcodes. the xgate is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the s12x_dbg section ). upon entering debug mode, the program counter will point to the tagged instruction. the other risc core registers will hold the result of the previous instruction. 4. forced breakpoints forced breakpoints are triggered by the s12x_dbg module (see section 4.9 of the s12x_dbg section ). when a forced breakpoint occurs, the xgate will enter debug mode upon completion of the current instruction. 5.6.3 leaving debug mode debug mode can only be left by setting the xgdbg bit to "0". if a thread is active (xgchid has not been cleared in debug mode), program execution will resume at the value of xgpc. 5.7 security in order to protect xgate application code on secured s12x devices, a few restrictions in the debug features have been made. these are: registers xgccr, xgpc, and xgr1?gr7 will read zero on a secured device registers xgccr, xgpc, and xgr1?gr7 can not be written on a secured device single stepping is not possible on a secured device 5.8 instruction set 5.8.1 addressing modes for the ease of implementation the architecture is a strict load/store risc machine, which means all operations must have one of the eight general purpose registers r0 ?r7 as their source as well their destination. all word accesses must work with a word aligned address, that is a[0] = 0! 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 237 5.8.1.1 naming conventions rd destination register, allowed range is r0?7 rd.l low byte of the destination register, bits [7:0] rd.h high byte of the destination register, bits [15:8] rs, rs1, rs2 source register, allowed range is r0?7 rs.l, rs1.l, rs2.l low byte of the source register, bits [7:0] rs.h, rs1.h, rs2.h high byte of the source register, bits[15:8] rb base register for indexed addressing modes, allowed range is r0?7 ri offset register for indexed addressing modes with register offset, allowed range is r0?7 ri+ offset register for indexed addressing modes with register offset and post-increment, allowed range is r0?7 (r0+ is equivalent to r0) ?i offset register for indexed addressing modes with register offset and pre-decrement, allowed range is r0?7 (?0 is equivalent to r0) note even though register r1 is intended to be used as a pointer to the variable segment, it may be used as a general purpose data register as well. selecting r0 as destination register will discard the result of the instruction. only the condition code register will be updated 5.8.1.2 inherent addressing mode (inh) instructions that use this addressing mode either have no operands or all operands are in internal xgate registers:. examples brk rts 5.8.1.3 immediate 3-bit wide (imm3) operands for immediate mode instructions are included in the instruction stream and are fetched into the instruction queue along with the rest of the 16 bit instruction. the ??symbol is used to indicate an immediate addressing mode operand. this address mode is used for semaphore instructions. examples: csem #1 ; unlock semaphore 1 ssem #3 ; lock semaphore 3 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 238 freescale semiconductor 5.8.1.4 immediate 4 bit wide (imm4) the 4 bit wide immediate addressing mode is supported by all shift instructions. rd = rd ? imm4 examples: lsl r4,#1 ; r4 = r4 << 1; shift register r4 by 1 bit to the left lsr r4,#3 ; r4 = r4 >> 3; shift register r4 by 3 bits to the right 5.8.1.5 immediate 8 bit wide (imm8) the 8 bit wide immediate addressing mode is supported by four major commands (add, sub, ld, cmp). rd = rd ? imm8 examples: addl r1,#1 ; adds an 8 bit value to register r1 subl r2,#2 ; subtracts an 8 bit value from register r2 ldh r3,#3 ; loads an 8 bit immediate into the high byte of register r3 cmpl r4,#4 ; compares the low byte of register r4 with an immediate value 5.8.1.6 immediate 16 bit wide (imm16) the 16 bit wide immediate addressing mode is a construct to simplify assembler code. instructions which offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode. rd = rd ? imm16 examples: ldw r4,#$1234 ; translated to ldl r4,#$34; ldh r4,#$12 add r4,#$5678 ; translated to addl r4,#$78; addh r4,#$56 5.8.1.7 monadic addressing (mon) in this addressing mode only one operand is explicitly given. this operand can either be the source ( f (rd)), the target (rd = f ()), or both source and target of the operation (rd = f (rd)). examples: jal r1 ; pc = r1, r1 = pc+2 sif r2 ; trigger irq associated with the channel number in r2.l 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 239 5.8.1.8 dyadic addressing (dya) in this mode the result of an operation between two registers is stored in one of the registers used as operands. rd = rd ? rs is the general register to register format, with register rd being the ?st operand and rs the second. rd and rs can be any of the 8 general purpose registers r0 ?r7. if r0 is used as the destination register, only the condition code ?gs are updated. this addressing mode is used only for shift operations with a variable shift value examples: lsl r4,r5 ; r4 = r4 << r5 lsr r4,r5 ; r4 = r4 >> r5 5.8.1.9 triadic addressing (tri) in this mode the result of an operation between two or three registers is stored into a third one. rd = rs1 ? rs2 is the general format used in the order rd, rs1, rs1. rd, rs1, rs2 can be any of the 8 general purpose registers r0 r7. if r0 is used as the destination register rd, only the condition code ?gs are updated. this addressing mode is used for all arithmetic and logical operations. examples: adc r5,r6,r7 ; r5 = r6 + r7 + carry sub r5,r6,r7 ; r5 = r6 - r7 5.8.1.10 relative addressing 9-bit wide (rel9) a 9-bit signed word address offset is included in the instruction word. this addressing mode is used for conditional branch instructions. examples: bcc rel9 ; pc = pc + 2 + (rel9 << 1) beq rel9 ; pc = pc + 2 + (rel9 << 1) 5.8.1.11 relative addressing 10-bit wide (rel10) an 11-bit signed word address offset is included in the instruction word. this addressing mode is used for the unconditional branch instruction. examples: bra rel10 ; pc = pc + 2 + (rel10 << 1) 5.8.1.12 index register plus immediate offset (ido5) (rs, #offset5) provides an unsigned offset from the base register. examples: ldb r4,(r1,#offset) ; loads a byte from r1+offset into r4 stw r4,(r1,#offset) ; stores r4 as a word to r1+offset 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 240 freescale semiconductor 5.8.1.13 index register plus register offset (idr) for load and store instructions (rs, ri) provides a variable offset in a register. examples: ldb r4,(r1,r2) ; loads a byte from r1+r2 into r4 stw r4,(r1,r2) ; stores r4 as a word to r1+r2 5.8.1.14 index register plus register offset with post-increment (idr+) [rs, ri+] provides a variable offset in a register, which is incremented after accessing the memory. in case of a byte access the index register will be incremented by one. in case of a word access it will be incremented by two. examples: ldb r4,(r1,r2+) ; loads a byte from r1+r2 into r4, r2+=1 stw r4,(r1,r2+) ; stores r4 as a word to r1+r2, r2+=2 5.8.1.15 index register plus register offset with pre-decrement (?dr) [rs, -ri] provides a variable offset in a register, which is decremented before accessing the memory. in case of a byte access the index register will be decremented by one. in case of a word access it will be decremented by two. examples: ldb r4,(r1,-r2) ; r2 -=1, loads a byte from r1+r2 into r4 stw r4,(r1,-r2) ; r2 -=2, stores r4 as a word to r1+r2 5.8.2 instruction summary and usage 5.8.2.1 load & store instructions any register can be loaded either with an immediate or from the address space using indexed addressing modes. ldl rd,#imm8 ; loads an immediate 8 bit value to the lower byte of rd ldw rd,(rb,ri) ; loads data using rb+ri as effective address ldb rd,(rb, ri+) ; loads data using rb+ri as effective address ; followed by an increment of ri depending on ; the size of the operation the same set of modes is available for the store instructions stb rs,(rb, ri) ; stores data using rb+ri as effective address stw rs,(rb, ri+) ; stores data using rb+ri as effective address ; followed by an increment of ri depending on ; the size of the operation. 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 241 5.8.2.2 logic and arithmetic instructions all logic and arithmetic instructions support the 8 bit immediate addressing mode (imm8: rd = rd ? #imm8) and the triadic addressing mode (tri: rd = rs1 ? rs2). all arithmetic is considered as signed, sign, over?w, zero and carry ?g will be updated. the carry will not be affected for logical operations. addl r2,#1 ; increment r2 andh r4,#$fe ; r4.h = r4.h & $fe, clear lower bit of higher byte add r3,r4,r5 ; r3 = r4 + r5 sub r3,r4,r5 ; r3 = r4 - r5 and r3,r4,r5 ; r3 = r4 & r5 logical and on the whole word or r3,r4,r5 ; r3 = r4 | r5 5.8.2.3 register ?register transfers this group comprises transfers from and to some special registers tfr r3,ccr ; transfers the condition code register to the low byte of ; register r3 branch instructions the branch offset is +255 words or -256 words counted from the beginning of the next instruction. since instructions have a xed 16 bit width, the branch offsets are word aligned by shifting the offset value by 2. beq label ; if z flag = 1 branch to label an unconditional branch allows a +511 words or -512 words branch distance. bra label 5.8.2.4 shift instructions shift operations allow the use of a 4 bit wide immediate value to identify a shift width within a 16 bit word. for shift operations a value of 0 does not shift at all, while a value of 15 shifts the register rd by 15 bits. in a second form the shift value is contained in the bits 3:0 of the register rs. examples: lsl r4,#1 ; r4 = r4 << 1; shift register r4 by 1 bit to the left lsr r4,#3 ; r4 = r4 >> 3; shift register r4 by 3 bits to the right asr r4,r2 ; r4 = r4 >> r2;arithmetic shift register r4 right by the amount ; of bits contained in r2[3:0]. 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 242 freescale semiconductor 5.8.2.5 bit field operations this addressing mode is used to identify the position and size of a bit ?ld for insertion or extraction. the width and offset are coded in the lower byte of the source register 2, rs2. the content of the upper byte is ignored. an offset of 0 denotes the right most position and a width of 0 denotes 1 bit. these instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word. figure 5-23. bit field addressing bfext r3,r4,r5 ; r5: w4 bits offset o4, will be extracted from r4 into r3 5.8.2.6 special instructions for dma usage the xgate offers a number of additional instructions for ?g manipulation, program ?w control and debugging: 1. sif: set a channel interrupt flag 2. ssem: test and set a hardware semaphore 3. csem: clear a hardware semaphore 4. brk: software breakpoint 5. nop: no operation 6. rts: terminate the current thread w4 o4 15 0 2 5 w4=3, o4=2 15 0 3 bit field extract bit field insert rs2 rs1 rd 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 243 5.8.3 cycle notation table 5-16 show the xgate access detail notation. each code letter equals one xgate cycle. each letter implies additional wait cycles if memories or peripherals are not accessible. memories or peripherals are not accessible if they are blocked by the s12x_cpu. in addition to this peripherals are only accessible every other xgate cycle. uppercase letters denote 16 bit operations. lowercase letters denote 8 bit operations. the xgate is able to perform two bus or wait cycles per s12x_cpu cycle. 5.8.4 thread execution when the risc core is triggered by an interrupt request (see figure 5-1 ) it ?st executes a vector fetch sequence which performs three bus accesses: 1. a v -cycle to fetch the initial content of the program counter. 2. a v -cycle to fetch the initial content of the data segment pointer (r1). 3. a p -cycle to load the initial opcode. afterwards a sequence of instructions (thread) is executed which is terminated by an "rts" instruction. if further interrupt requests are pending after a thread has been terminated, a new vector fetch will be performed. otherwise the risc core will idle until a new interrupt request is received. a thread can not be interrupted by an interrupt request. 5.8.5 instruction glossary this section describes the xgate instruction set in alphabetical order. table 5-16. access detail notation v vector fetch: always an aligned word read, lasts for at least one risc core cycle p program word fetch: always an aligned word read, lasts for at least one risc core cycle r 8 bit data read: lasts for at least one risc core cycle r 16 bit data read: lasts for at least one risc core cycle w 8 bit data write: lasts for at least one risc core cycle w 16 bit data write: lasts for at least one risc core cycle a alignment cycle: no read or write, lasts for zero or one risc core cycles f free cycle: no read or write, lasts for one risc core cycles special cases pp/p branch: pp if branch taken, p if not 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 244 freescale semiconductor operation rs1 + rs2 + c ? rd adds the content of register rs1, the content of register rs2 and the value of the carry bit using binary addition and stores the result in the destination register rd. the zero flag is also carried forward from the previous operation allowing 32 and more bit additions. example: adc r6,r2,r2 adc r7,r3,r3 ; r7:r6 = r5:r4 + r3:r2 bcc ; conditional branch on 32 bit addition ccr effects code and cpu cycles adc add with carry adc nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000 and z was set before this operation; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs1[15] & rs2[15] & rd[15] new | rs1[15] & rs2[15] & rd[15] new c: set if there is a carry from bit 15 of the result; cleared otherwise. rs1[15] & rs2[15] | rs1[15] & rd[15] new | rs2[15] & rd[15] new source form address mode machine code cycles adc rd, rs1, rs2 tri 0 0 0 1 1 rd rs1 rs2 1 1 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 245 operation rs1 + rs2 ? rd rd + imm16 ? rd (translates to addl rd, #imm16[7:0]; addh rd, #[15:8]) performs a 16 bit addition and stores the result in the destination register rd. ccr effects code and cpu cycles add add without carry add nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs1[15] & rs2[15] & rd[15] new | rs1[15] & rs2[15] & rd[15] new refer to addh instruction for #imm16 operations. c: set if there is a carry from bit 15 of the result; cleared otherwise. rs1[15] & rs2[15] | rs1[15] & rd[15] new | rs2[15] & rd[15] new refer to addh instruction for #imm16 operations. source form address mode machine code cycles add rd, rs1, rs2 tri 0 0 0 1 1 rd rs1 rs2 1 0 p add rd, #imm16 imm8 1 1 1 0 0 rd imm16[7:0] p imm8 1 1 1 0 1 rd imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 246 freescale semiconductor operation rd + imm8:$00 ? rd adds the content of high byte of register rd and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register rd. this instruction can be used after an addl for a 16 bit immediate addition. example: addl r2,#lowbyte addh r2,#highbyte ; r2 = r2 + 16 bit immediate ccr effects code and cpu cycles addh add immediate 8 bit constant (high byte) addh nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old & imm8[7] & rd[15] new | rd[15] old & imm8[7] & rd[15] new c: set if there is a carry from the bit 15 of the result; cleared otherwise. rd[15] old & imm8[7] | rd[15] old & rd[15] new | imm8[7] & rd[15] new source form address mode machine code cycles addh rd, #imm8 imm8 1 1 1 0 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 247 operation rd + $00:imm8 ? rd adds the content of register rd and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register rd. this instruction must be used ?st for a 16 bit immediate addition in conjunction with the addh instruction. ccr effects code and cpu cycles addl add immediate 8 bit constant (low byte) addl nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the 8 bit operation; cleared otherwise. rd[15] old & rd[15] new c: set if there is a carry from the bit 15 of the result; cleared otherwise. rd[15] old & rd[15] new source form address mode machine code cycles addl rd, #imm8 imm8 1 1 1 0 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 248 freescale semiconductor operation rs1 & rs2 ? rd rd & imm16 ? rd (translates to andl rd, #imm16[7:0]; andh rd, #imm16[15:8]) performs a bit wise logical and of two 16 bit values and stores the result in the destination register rd. remark: there is no complement to the bith and bitl functions. this can be imitated by using r0 as a destination register. and r0, rs1, rs2 performs a bit wise test without storing a result. ccr effects code and cpu cycles and logical and and nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. refer to andh instruction for #imm16 operations. v: 0; cleared. c: not affected. source form address mode machine code cycles and rd, rs1, rs2 tri 0 0 0 1 0 rd rs1 rs2 0 0 p and rd, #imm16 imm8 1 0 0 0 0 rd imm16[7:0] p imm8 1 0 0 0 1 rd imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 249 operation rd.h & imm8 ? rd.h performs a bit wise logical and between the high byte of register rd and an immediate 8 bit constant and stores the result in the destination register rd.h. the low byte of rd is not affected. ccr effects code and cpu cycles andh logical and immediate 8 bit constant (high byte) andh nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles andh rd, #imm8 imm8 1 0 0 0 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 250 freescale semiconductor operation rd.l & imm8 ? rd.l performs a bit wise logical and between the low byte of register rd and an immediate 8 bit constant and stores the result in the destination register rd.l. the high byte of rd is not affected. ccr effects code and cpu cycles andl logical and immediate 8 bit constant (low byte) andl nzvc ?? 0 n: set if bit 7 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles andl rd, #imm8 imm8 1 0 0 0 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 251 operation n = rs or imm4 shifts the bits in register rd n positions to the right. the higher n bits of the register rd become ?led with the sign bit (rd[15]). the carry ?g will be updated to the bit contained in rd[n-1] before the shift for n > 0. n can range from 0 to 16. in immediate address mode, n is determined by the operand imm4. n is considered to be 16 in imm4 is equal to 0. in dyadic address mode, n is determined by the content of rs. n is considered to be 16 if the content of rs is greater than 15. ccr effects code and cpu cycles asr arithmetic shift right asr nzvc ?? 0 ? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old ^ rd[15] new c: set if n > 0 and rd[n-1] = 1; if n = 0 unaffected. source form address mode machine code cycles asr rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 0 0 1 p asr rd, rs dya 0 0 0 0 1 rd rs 1 0 0 0 1 p b15 rd c n 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 252 freescale semiconductor operation if c = 0, then pc + $0002 + (rel9 << 1) ? pc tests the carry ?g and branches if c = 0. ccr effects code and cpu cycles bcc branch if carry cleared (same as bhs) bcc nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bcc rel9 rel9 0 0 1 0 0 0 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 253 operation if c = 1, then pc + $0002 + (rel9 << 1) ? pc tests the carry ?g and branches if c = 1. ccr effects code and cpu cycles bcs branch if carry set (same as blo) bcs nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bcs rel9 rel9 0 0 1 0 0 0 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 254 freescale semiconductor operation if z = 1, then pc + $0002 + (rel9 << 1) ? pc tests the zero ?g and branches if z = 1. ccr effects code and cpu cycles beq branch if equal beq nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles beq rel9 rel9 0 0 1 0 0 1 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 255 operation rs1[( o + w ): o ] ? rd[ w :0]; 0 ? rd[15:( w +1)] w = (rs2[7:4]) o = (rs2[3:0]) extracts w+1 bits from register rs1 starting at position o and writes them right aligned into register rd. the remaining bits in rd will be cleared. if (o+w) > 15 only bits [15:o] get extracted. ccr effects code and cpu cycles bfext bit field extract bfext nzvc 0 ? 0 ? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles bfext rd, rs1, rs2 tri 0 1 1 0 0 rd rs1 rs2 1 1 p w4 o4 15 0 2 5 w4=3, o4=2 15 0 3 bit field extract rs2 rs1 rd 0 15 0 3 74 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 256 freescale semiconductor operation firstone (rs) ? rd; searches the ?st ??in register rs (from msb to lsb) and writes the bit position into the destination register rd. the upper bits of rd are cleared. in case the content of rs is equal to $0000, rd will be cleared and the carry ?g will be set. this is used to distinguish a ??in position 0 versus no ??in the whole rs register at all. ccr effects code and cpu cycles bffo bit field find first one bffo nzvc 0 ? 0 ? n: 0; cleared. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: set if rs = $0000 1 ; cleared otherwise. 1 before executing the instruction source form address mode machine code cycles bffo rd, rs dya 0 0 0 0 1 rd rs 1 0 0 0 0 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 257 operation rs1[ w : 0 ] ? rd[( w+o ):o]; w = (rs2[7:4]) o = (rs2[3:0]) extracts w+1 bits from register rs1 starting at position 0 and writes them into register rd starting at position o . the remaining bits in rd are not affected. if (o+w) > 15 the upper bits are ignored. using r0 as a rs1, this command can be used to clear bits. ccr effects code and cpu cycles bfins bit field insert bfins nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles bfins rd, rs1, rs2 tri 0 1 1 0 1 rd rs1 rs2 1 1 p w4 o4 15 0 2 5 w4=3, o4=2 15 0 3 bit field insert rs2 rd rs1 15 0 3 74 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 258 freescale semiconductor operation !rs1[ w : 0 ] ? rd[ w +o:o]; w = (rs2[7:4]) o = (rs2[3:0]) extracts w+1 bits from register rs1 starting at position 0, inverts them and writes into register rd starting at position o . the remaining bits in rd are not affected. if (o+w) > 15 the upper bits are ignored. using r0 as a rs1, this command can be used to set bits. ccr effects code and cpu cycles bfinsi bit field insert and invert bfinsi nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles bfinsi rd, rs1, rs2 tri 0 1 1 1 0 rd rs1 rs2 1 1 p w4 o4 15 0 2 5 w4=3, o4=2 15 0 3 inverted bit field insert rs2 rd rs1 15 0 3 74 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 259 operation !(rs1[ w : 0 ] ^ rd[w+o:o]) ? rd[ w +o:o]; w = (rs2[7:4]) o = (rs2[3:0]) extracts w+1 bits from register rs1 starting at position 0, performs an xnor with rd[w+o:o] and writes the bits back io rd. the remaining bits in rd are not affected. if (o+w) > 15 the upper bits are ignored. using r0 as a rs1, this command can be used to toggle bits. ccr effects code and cpu cycles bfinsx bit field insert and xnor bfinsx nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles bfinsx rd, rs1, rs2 tri 0 1 1 1 1 rd rs1 rs2 1 1 p w4 o4 15 0 2 5 w4=3, o4=2 15 0 3 bit field insert xnor rs2 rd rs1 15 0 3 74 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 260 freescale semiconductor operation if n ^ v = 0, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare signed numbers. branch if rs1 rs2: sub r0,rs1,rs2 bge rel9 ccr effects code and cpu cycles bge branch if greater than or equal to zero bge nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bge rel9 rel9 0 0 1 1 0 1 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 261 operation if z | (n ^ v) = 0, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare signed numbers. branch if rs1 > rs2: sub r0,rs1,rs2 bge rel9 ccr effects code and cpu cycles bgt branch if greater than zero bgt nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bgt rel9 rel9 0 0 1 1 1 0 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 262 freescale semiconductor operation if c | z = 0, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare unsigned numbers. branch if rs1 > rs2: sub r0,rs1,rs2 bhi rel9 ccr effects code and cpu cycles bhi branch if higher bhi nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bhi rel9 rel9 0 0 1 1 0 0 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 263 operation if c = 0, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare unsigned numbers. branch if rs1 rs2: sub r0,rs1,rs2 bhs rel9 ccr effects code and cpu cycles bhs branch if higher or same (same as bcc) bhs nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bhs rel9 rel9 0 0 1 0 0 0 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 264 freescale semiconductor operation rd.h & imm8 ? none performs a bit wise logical and between the high byte of register rd and an immediate 8 bit constant. only the condition code ?gs get updated, but no result is written back ccr effects code and cpu cycles bith bit test immediate 8 bit constant (high byte) bith nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles bith rd, #imm8 imm8 1 0 0 1 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 265 operation rd.l & imm8 ? none performs a bit wise logical and between the low byte of register rd and an immediate 8 bit constant. only the condition code ?gs get updated, but no result is written back . ccr effects code and cpu cycles bitl bit test immediate 8 bit constant (low byte) bitl nzvc ?? 0 n: set if bit 7 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles bitl rd, #imm8 imm8 1 0 0 1 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 266 freescale semiconductor operation if z | (n ^ v) = 1, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare signed numbers. branch if rs1 rs2: sub r0,rs1,rs2 ble rel9 ccr effects code and cpu cycles ble branch if less or equal to zero ble nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles ble rel9 rel9 0 0 1 1 1 0 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 267 operation if c = 1, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare unsigned numbers. branch if rs1 < rs2: sub r0,rs1,rs2 blo rel9 ccr effects code and cpu cycles blo branch if carry set (same as bcs) blo nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles blo rel9 rel9 0 0 1 0 0 0 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 268 freescale semiconductor operation if c | z = 1, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare unsigned numbers. branch if rs1 rs2: sub r0,rs1,rs2 bls rel9 ccr effects code and cpu cycles bls branch if lower or same bls nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bls rel9 rel9 0 0 1 1 0 0 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 269 operation if n ^ v = 1, then pc + $0002 + (rel9 << 1) ? pc branch instruction to compare signed numbers. branch if rs1 < rs2: sub r0,rs1,rs2 blt rel9 ccr effects code and cpu cycles blt branch if lower than zero blt nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles blt rel9 rel9 0 0 1 1 0 1 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 270 freescale semiconductor operation if n = 1, then pc + $0002 + (rel9 << 1) ? pc tests the sign ?g and branches if n = 1. ccr effects code and cpu cycles bmi branch if minus bmi nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bmi rel9 rel9 0 0 1 0 1 0 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 271 operation if z = 0, then pc + $0002 + (rel9 << 1) ? pc tests the zero ?g and branches if z = 0. ccr effects code and cpu cycles bne branch if not equal bne nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bne rel9 rel9 0 0 1 0 0 1 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 272 freescale semiconductor operation if n = 0, then pc + $0002 + (rel9 << 1) ? pc tests the sign ?g and branches if n = 0. ccr effects code and cpu cycles bpl branch if plus bpl nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bpl rel9 rel9 0 0 1 0 1 0 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 273 operation pc + $0002 + (rel10 << 1) ? pc branches always ccr effects code and cpu cycles bra branch always bra nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bra rel10 rel10 0 0 1 1 1 1 rel10 pp 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 274 freescale semiconductor operation put xgate into debug mode (see section 5.6.2, ?ntering debug mode )and signals a software breakpoint to the s12x_dbg module (see section 4.9 of the s12x_dbg section ). note it is not possible to single step over a brk instruction. this instruction does not advance the program counter. ccr effects code and cpu cycles brk break brk nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles brk inh 0000000000000000 paff 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 275 operation if v = 0, then pc + $0002 + (rel9 << 1) ? pc tests the over?w ?g and branches if v = 0. ccr effects code and cpu cycles bvc branch if overflow cleared bvc nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bvc rel9 rel9 0 0 1 0 1 1 0 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 276 freescale semiconductor operation if v = 1, then pc + $0002 + (rel9 << 1) ? pc tests the over?w ?g and branches if v = 1. ccr effects code and cpu cycles bvs branch if overflow set bvs nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles bvs rel9 rel9 0 0 1 0 1 1 1 rel9 pp/p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 277 operation rs2 ?rs1 ? none (translates to sub r0, rs1, rs2) rd imm16 ? none (translates to cmpl rd, #imm16[7:0]; cpch rd, #imm16[15:8]) subtracts two 16 bit values and discards the result. ccr effects code and cpu cycles cmp compare cmp nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs1[15] & rs2[15] & result[15] | rs1[15] & rs2[15] & result[15] rd[15] & imm16[15] & result[15] | rd[15] & imm16[15] & result[15] c: set if there is a carry from the bit 15 of the result; cleared otherwise. rs1[15] & rs2[15] | rs1[15] & result[15] | rs2[15] & result[15] rd[15] & imm16[15] | rd[15] & result[15] | imm16[15] & result[15] source form address mode machine code cycles cmp rs1, rs2 tri 0 0 0 1 1 0 0 0 rs1 rs2 0 0 p cmp rs, #imm16 imm8 1 1 0 1 0 rs imm16[7:0] p imm8 1 1 0 1 1 rs imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 278 freescale semiconductor operation rs.l ?imm8 ? none, only condition code ?gs get updated subtracts the 8 bit constant imm8 contained in the instruction code from the low byte of the source register rs.l using binary subtraction and updates the condition code register accordingly. remark: there is no equivalent operation using triadic addressing. comparing the values of two registers can be performed by using the subtract instruction with r0 as destination register. ccr effects code and cpu cycles cmpl compare immediate 8 bit constant (low byte) cmpl nzvc ???? n: set if bit 7 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: set if a twos complement over?w resulted from the 8 bit operation; cleared otherwise. rs[7] & imm8[7] & result[7] | rs[7] & imm8[7] & result[7] c: set if there is a carry from the bit 7 to bit 8 of the result; cleared otherwise. rs[7] & imm8[7] | rs[7] & result[7] | imm8[7] & result[7] source form address mode machine code cycles cmpl rs, #imm8 imm8 1 1 0 1 0 rs imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 279 operation ~rs ? rd (translates to xnor rd, r0, rs) ~rd ? rd (translates to xnor rd, r0, rd) performs a ones complement on a general purpose register. ccr effects code and cpu cycles com one? complement com nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles com rd, rs tri 0 0 0 1 0 rd 0 0 0 rs 1 1 p com rd tri 0 0 0 1 0 rd 0 0 0 rd 1 1 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 280 freescale semiconductor operation rs2 ?rs1 - c ? none (translates to sbc r0, rs1, rs2) subtracts the carry bit and the content of register rs2 from the content of register rs1 using binary subtraction and discards the result. ccr effects code and cpu cycles cpc compare with carry cpc nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs1[15] & rs2[15] & result[15] | rs1[15] & rs2[15] & result[15] c: set if there is a carry from the bit 15 of the result; cleared otherwise. rs1[15] & rs2[15] | rs1[15] & result[15] | rs2[15] & result[15] source form address mode machine code cycles cpc rs1, rs2 tri 0 0 0 1 1 0 0 0 rs1 rs2 0 1 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 281 operation rs.h - imm8 - c ? none, only condition code ?gs get updated subtracts the carry bit and the 8 bit constant imm8 contained in the instruction code from the high byte of the source register rd using binary subtraction and updates the condition code register accordingly. the carry bit and zero bits are taken into account to allow a 16 bit compare in the form of cmpl r2,#lowbyte cpch r2,#highbyte bcc ; branch condition remark: there is no equivalent operation using triadic addressing. comparing the values of two registers can be performed by using the subtract instruction with r0 as destination register. ccr effects code and cpu cycles cpch compare immediate 8 bit constant with carry (high byte) cpch nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $00 and z was set before this operation; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs[15] & imm8[7] & result[15] | rs[15] & imm8[7] & result[15] c: set if there is a carry from the bit 15 of the result; cleared otherwise. rs[15] & imm8[7] | rs[15] & result[15] | imm8[7] & result[15] source form address mode machine code cycles cpch rd, #imm8 imm8 1 1 0 1 1 rs imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 282 freescale semiconductor operation unlocks a semaphore that was locked by the risc core. in monadic address mode, bits rs[2:0] select the semaphore to be cleared. ccr effects code and cpu cycles csem clear semaphore csem nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles csem #imm3 imm3 00000 imm3 1 1110000 pa csem rs mon 00000 rs 11110001 pa 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 283 operation n = rs or imm4 shifts the bits in register rd n positions to the left. the lower n bits of the register rd become ?led with the carry ?g. the carry ?g will be updated to the bit contained in rd[16-n] before the shift for n > 0. n can range from 0 to 16. in immediate address mode, n is determined by the operand imm4. n is considered to be 16 in imm4 is equal to 0. in dyadic address mode, n is determined by the content of rs. n is considered to be 16 if the content of rs is greater than 15. ccr effects code and cpu cycles csl logical shift left with carry csl nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old ^ rd[15] new c: set if n > 0 and rd[16-n] = 1; if n = 0 unaffected. source form address mode machine code cycles csl rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 0 1 0 p csl rd, rs dya 0 0 0 0 1 rd rs 1 0 0 1 0 p c rd c c c n bits c n 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 284 freescale semiconductor operation n = rs or imm4 shifts the bits in register rd n positions to the right. the higher n bits of the register rd become ?led with the carry ?g. the carry ?g will be updated to the bit contained in rd[n-1] before the shift for n >0. n can range from 0 to 16. in immediate address mode, n is determined by the operand imm4. n is considered to be 16 in imm4 is equal to 0. in dyadic address mode, n is determined by the content of rs. n is considered to be 16 if the content of rs is greater than 15. ccr effects code and cpu cycles csr logical shift right with carry csr nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old ^ rd[15] new c: set if n > 0 and rd[n-1] = 1; if n = 0 unaffected. source form address mode machine code cycles csr rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 0 1 1 p csr rd, rs dya 0 0 0 0 1 rd rs 1 0 0 1 1 p c c rd c c n bits c n 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 285 operation pc + $0002 ? rd; rd ? pc jumps to the address stored in rd and saves the return address in rd. ccr effects code and cpu cycles jal jump and link jal nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles jal rd mon 00000 rd 11110110 pp 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 286 freescale semiconductor operation m[rb, #offs5 ? rd.l; $00 ? rd.h m[rb, ri ] ? rd.l; $00 ? rd.h m[rb, ri] ? rd.l; $00 ? rd.h; ri+1 ? ri; 1 ri-1 ? ri; m[rs, ri] ? rd.l; $00 ? rd.h loads a byte from memory into the low byte of register rd. the high byte is cleared. ccr effects code and cpu cycles ldb load byte from memory (low byte) ldb 1.if the same general purpose register is used as index (ri) and destination register (rd), the content of the register will not be incremented after the data move: m[rb, ri] ? rd.l; $00 ? rd.h nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles ldb rd, (rb, #offs5) ido5 0 1 0 0 0 rd rb offs5 pr ldb rd, (rs, ri) idr 0 1 1 0 0 rd rb ri 0 0 pr ldb rd, (rs, ri+) idr+ 0 1 1 0 0 rd rb ri 0 1 pr ldb rd, (rs, -ri) -idr 0 1 1 0 0 rd rb ri 1 0 pr 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 287 operation imm8 ? rd.h; loads an eight bit immediate constant into the high byte of register rd. the low byte is not affected. ccr effects code and cpu cycles ldh load immediate 8 bit constant (high byte) ldh nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles ldh rd, #imm8 imm8 1 1 1 1 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 288 freescale semiconductor operation imm8 ? rd.l; $00 ? rd.h loads an eight bit immediate constant into the low byte of register rd. the high byte is cleared. ccr effects code and cpu cycles ldl load immediate 8 bit constant (low byte) ldl nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles ldl rd, #imm8 imm8 1 1 1 1 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 289 operation m[rb, #offs5 ] ? rd m[rb, ri ] ? rd m[rb, ri] ? rd; ri+2 ? ri 1 ri-2 ? ri; m[rs, ri] ? rd imm16 ? rd (translates to ldl rd, #imm16[7:0]; ldh rd, #imm16[15:8]) loads a 16 bit value into the register rd. ccr effects code and cpu cycles ldw load word from memory ldw 1. if the same general purpose register is used as index (ri) and destination register (rd), the content of the register will not be incremented after the data move: m[rb, ri] ? rd nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles ldw rd, (rb, #offs5) ido5 0 1 0 0 1 rd rb offs5 pr ldw rd, (rb, ri) idr 0 1 1 0 1 rd rb ri 0 0 pr ldw rd, (rb, ri+) idr+ 0 1 1 0 1 rd rb ri 0 1 pr ldw rd, (rb, -ri) -idr 0 1 1 0 1 rd rb ri 1 0 pr ldw rd, #imm16 imm8 1 1 1 1 0 rd imm16[7:0] p imm8 1 1 1 1 1 rd imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 290 freescale semiconductor operation n = rs or imm4 shifts the bits in register rd n positions to the left. the lower n bits of the register rd become ?led with zeros. the carry ?g will be updated to the bit contained in rd[16-n] before the shift for n > 0. n can range from 0 to 16. in immediate address mode, n is determined by the operand imm4. n is considered to be 16 in imm4 is equal to 0. in dyadic address mode, n is determined by the content of rs. n is considered to be 16 if the content of rs is greater than 15. ccr effects code and cpu cycles lsl logical shift left lsl nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old ^ rd[15] new c: set if n > 0 and rd[16-n] = 1; if n = 0 unaffected. source form address mode machine code cycles lsl rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 1 0 0 p lsl rd, rs dya 0 0 0 0 1 rd rs 1 0 1 0 0 p 0 rd 0 0 0 n bits c n 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 291 operation n = rs or imm4 shifts the bits in register rd n positions to the right. the higher n bits of the register rd become ?led with zeros. the carry ?g will be updated to the bit contained in rd[n-1] before the shift for n > 0. n can range from 0 to 16. in immediate address mode, n is determined by the operand imm4. n is considered to be 16 in imm4 is equal to 0. in dyadic address mode, n is determined by the content of rs. n is considered to be 16 if the content of rs is greater than 15. ccr effects code and cpu cycles lsr logical shift right lsr nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old ^ rd[15] new c: set if n > 0 and rd[n-1] = 1; if n = 0 unaffected. source form address mode machine code cycles lsr rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 1 0 1 p lsr rd, rs dya 0 0 0 0 1 rd rs 1 0 1 0 1 p 0 rd 0 0 0 n bits c n 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 292 freescale semiconductor operation rs ? rd (translates to or rd, r0, rs) copies the content of rs to rd. ccr effects code and cpu cycles mov move register content mov nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles mov rd, rs tri 0 0 0 1 0 rd 0 0 0 rs 1 0 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 293 operation ?s ? rd (translates to sub rd, r0, rs) ?d ? rd (translates to sub rd, r0, rd) performs a twos complement on a general purpose register. ccr effects code and cpu cycles neg two? complement neg nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs[15] & rd[15] new c: set if there is a carry from the bit 15 of the result; cleared otherwise rs[15] | rd[15] new source form address mode machine code cycles neg rd, rs tri 0 0 0 1 1 rd 0 0 0 rs 0 0 p neg rd tri 0 0 0 1 1 rd 0 0 0 rd 0 0 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 294 freescale semiconductor operation no operation for one cycle. ccr effects code and cpu cycles nop no operation nop nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles nop inh 0000000100000000 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 295 operation rs1 | rs2 ? rd rd | imm16 ? rd (translates to orl rd, #imm16[7:0]; orh rd, #imm16[15:8] performs a bit wise logical or between two 16 bit values and stores the result in the destination register rd. ccr effects code and cpu cycles or logical or or nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. refer to orh instruction for #imm16 operations. v: 0; cleared. c: not affected. source form address mode machine code cycles or rd, rs1, rs2 tri 0 0 0 1 0 rd rs1 rs2 1 0 p or rd, #imm16 imm8 1 0 1 0 0 rd imm16[7:0] p imm8 1 0 1 0 1 rd imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 296 freescale semiconductor operation rd.h | imm8 ? rd.h performs a bit wise logical or between the high byte of register rd and an immediate 8 bit constant and stores the result in the destination register rd.h. the low byte of rd is not affected. ccr effects code and cpu cycles orh logical or immediate 8 bit constant (high byte) orh nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles orh rd, #imm8 imm8 1 0 1 0 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 297 operation rd.l | imm8 ? rd.l performs a bit wise logical or between the low byte of register rd and an immediate 8 bit constant and stores the result in the destination register rd.l. the high byte of rd is not affected. ccr effects code and cpu cycles orl logical or immediate 8 bit constant (low byte) orl nzvc ?? 0 n: set if bit 7 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles orl rd, #imm8 imm8 1 0 1 0 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 298 freescale semiconductor operation calculates the number of ones in the register rd. the carry ?g will be set if the number is odd, otherwise it will be cleared. ccr effects code and cpu cycles pa r calculate parity par nzvc 0 ? 0 ? n: 0; cleared. z: set if rd is $0000; cleared otherwise. v: 0; cleared. c: set if there the number of ones in the register rd is odd; cleared otherwise. source form address mode machine code cycles par, rd mon 0 0 0 0 0 rd 1 1 1 1 0 1 0 1 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 299 operation n = rs or imm4 rotates the bits in register rd n positions to the left. the lower n bits of the register rd are ?led with the upper n bits. two source forms are available. in the ?st form, the parameter n is contained in the instruction code as an immediate operand. in the second form, the parameter is contained in the lower bits of the source register rs[3:0]. all other bits in rs are ignored. if n is zero, no shift will take place and the register rd will be unaffected; however, the condition code ?gs will be updated. ccr effects code and cpu cycles rol rotate left rol nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles rol rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 1 1 0 p rol rd, rs dya 0 0 0 0 1 rd rs 1 0 1 1 0 p rd n bits 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 300 freescale semiconductor operation n = rs or imm4 rotates the bits in register rd n positions to the right. the upper n bits of the register rd are ?led with the lower n bits. two source forms are available. in the ?st form, the parameter n is contained in the instruction code as an immediate operand. in the second form, the parameter is contained in the lower bits of the source register rs[3:0]. all other bits in rs are ignored. if n is zero no shift will take place and the register rd will be unaffected; however, the condition code ?gs will be updated. ccr effects code and cpu cycles ror rotate right ror nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles ror rd, #imm4 imm4 0 0 0 0 1 rd imm4 1 1 1 1 p ror rd, rs dya 0 0 0 0 1 rd rs 1 0 1 1 1 p rd n bits 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 301 operation terminates the current thread of program execution and remains idle until a new thread is started by the hardware scheduler. ccr effects code and cpu cycles rts return to scheduler rts nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles rts inh 0000001000000000 pa 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 302 freescale semiconductor operation rs1 - rs2 - c ? rd subtracts the content of register rs2 and the value of the carry bit from the content of register rs1 using binary subtraction and stores the result in the destination register rd. also the zero ?g is carried forward from the previous operation allowing 32 and more bit subtractions. example: sub r6,r4,r2 sbc r7,r5,r3 ; r7:r6 = r5:r4 - r3:r2 bcc ; conditional branch on 32 bit subtraction ccr effects code and cpu cycles sbc subtract with carry sbc nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000 and z was set before this operation; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs1[15] & rs2[15] & rd[15] new | rs1[15] & rs2[15] & rd[15] new c: set if there is a carry from bit 15 of the result; cleared otherwise. rs1[15] & rs2[15] | rs1[15] & rd[15] new | rs2[15] & rd[15] new source form address mode machine code cycles sbc rd, rs1, rs2 tri 0 0 0 1 1 rd rs1 rs2 0 1 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 303 operation the result in rd is the 16 bit sign extended representation of the original twos complement number in the low byte of rd.l. ccr effects code and cpu cycles sex sign extend byte to word sex nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles sex rd mon 0 0 0 0 0 rd 1 1 1 1 0 1 0 0 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 304 freescale semiconductor operation sets the interrupt flag of an xgate channel. this instruction supports two source forms. if inherent address mode is used, then the interrupt flag of the current channel (xgchid) will be set. if the monadic address form is used, the interrupt ?g associated with the channel id number contained in rs[6:0] is set. the content of rs[15:7] is ignored. ccr effects code and cpu cycles sif set interrupt flag sif nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles sif inh 0000001100000000 pa sif rs mon 0 0 0 0 0 rs 1 1 1 1 0 1 1 1 pa 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 305 operation attempts to set a semaphore. the state of the semaphore will be stored in the carry-flag: 1 = semaphore is locked by the risc core 0 = semaphore is locked by the s12x_cpu in monadic address mode, bits rs[2:0] select the semaphore to be set. ccr effects code and cpu cycles ssem set semaphore ssem nzvc ? n: not affected. z: not affected. v: not affected. c: set if semaphore is locked by the risc core; cleared otherwise. source form address mode machine code cycles ssem #imm3 imm3 0 0 0 0 0 imm3 1 1 1 1 0 0 1 0 pa ssem rs mon 0 0 0 0 0 rs 1 1 1 1 0 0 1 1 pa 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 306 freescale semiconductor operation rs.l ? m[rb, #offs5 ] rs.l ? m[rb, ri ] rs.l ? m[rb, ri]; ri+1 ? ri; ri? ? ri; rs.l ? m[rb, ri] 1 stores the low byte of register rd to memory. ccr effects code and cpu cycles stb store byte to memory (low byte) stb 1. if the same general purpose register is used as index (ri) and source register (rs), the unmodi?d content of the source register is written to the memory: rs.l ? m[rb, rs-1]; rs-1 ? rs nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles stb rs, (rb, #offs5), ido5 0 1 0 1 0 rs rb offs5 pw stb rs, (rb, ri) idr 0 1 1 1 0 rs rb ri 0 0 pw stb rs, (rb, ri+) idr+ 0 1 1 1 0 rs rb ri 0 1 pw stb rs, (rb, -ri) -idr 0 1 1 1 0 rs rb ri 1 0 pw 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 307 operation rs ? m[rb, #offs5 ] rs ? m[rb, ri ] rs ? m[rb, ri]; ri+2 ? ri; ri? ? ri; rs ? m[rb, ri] 1 stores the content of register rs to memory. ccr effects code and cpu cycles stw store word to memory stw 1. if the same general purpose register is used as index (ri) and source register (rs), the unmodi?d content of the source register is written to the memory: rs ? m[rb, rs?]; rs? ? rs nzvc n: not affected. z: not affected. v: not affected. c: not affected. source form address mode machine code cycles stw rs, (rb, #offs5) ido5 0 1 0 1 1 rs rb offs5 pw stw rs, (rb, ri) idr 0 1 1 1 1 rs rb ri 0 0 pw stw rs, (rb, ri+) idr+ 0 1 1 1 1 rs rb ri 0 1 pw stw rs, (rb, -ri) -idr 0 1 1 1 1 rs rb ri 1 0 pw 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 308 freescale semiconductor operation rs1 ?rs2 ? rd rd ? imm16 ? rd (translates to subl rd, #imm16[7:0]; subh rd, #imm16{15:8]) subtracts two 16 bit values and stores the result in the destination register rd. ccr effects code and cpu cycles sub subtract without carry sub nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs1[15] & rs2[15] & rd[15] new | rs1[15] & rs2[15] & rd[15] new refer to subh instruction for #imm16 operations. c: set if there is a carry from the bit 15 of the result; cleared otherwise. rs1[15] & rs2[15] | rs1[15] & rd[15] new | rs2[15] & rd[15] new refer to subh instruction for #imm16 operations. source form address mode machine code cycles sub rd, rs1, rs2 tri 0 0 0 1 1 rd rs1 rs2 0 0 p sub rd, #imm16 imm8 1 1 0 0 0 rd imm16[7:0] p imm8 1 1 0 0 1 rd imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 309 operation rd ?imm8:$00 ? rd subtracts a signed immediate 8 bit constant from the content of high byte of register rd and using binary subtraction and stores the result in the high byte of destination register rd. this instruction can be used after an subl for a 16 bit immediate subtraction. example: subl r2,#lowbyte subh r2,#highbyte ; r2 = r2 - 16 bit immediate ccr effects code and cpu cycles subh subtract immediate 8 bit constant (high byte) subh nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rd[15] old & imm8[7] & rd[15] new | rd[15] old & imm8[7] & rd[15] new c: set if there is a carry from the bit 15 of the result; cleared otherwise. rd[15] old & imm8[7] | rd[15] old & rd[15] new | imm8[7] & rd[15] new source form address mode machine code cycles subh rd, #imm8 imm8 1 1 0 0 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 310 freescale semiconductor operation rd ?$00:imm8 ? rd subtracts an immediate 8 bit constant from the content of register rd using binary subtraction and stores the result in the destination register rd. ccr effects code and cpu cycles subl subtract immediate 8 bit constant (low byte) subl nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the 8 bit operation; cleared otherwise. rd[15] old & rd[15] new c: set if there is a carry from the bit 15 of the result; cleared otherwise. rd[15] old & rd[15] new source form address mode machine code cycles subl rd, #imm8 imm8 1 1 0 0 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 311 operation tfr rd,ccr: ccr ? rd[3:0]; 0 ? rd[15:4] tfr ccr,rd: rd[3:0] ? ccr tfr rd,pc: pc+4 ? rd transfers the content of one risc core register to another. the tfr rd,pc instruction can be used to implement relative subroutine calls. example: tfr r7,pc ;return address (retaddr) is stored in r7 bra subr ;relative branch to subroutine (subr) retaddr ... subr ... jal r7 ;jump to return address (retaddr) ccr effects code and cpu cycles tfr transfer from and to special registers tfr source form address mode machine code cycles tfr rd,ccr ccr ? rd mon 00000 rd 11111000 p tfr ccr,rs rs ? ccr mon 00000 rs 11111001 p tfr rd,pcpc+4 ? rd mon 00000 rd 11111010 p tfr rd,ccr, tfr rd,pc: tfr ccr,rs: nzvc n: not affected. z: not affected. v: not affected. c: not affected. nzvc ???? n: rs[3]. z: rs[2]. v: rs[1]. c: rs[0]. 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 312 freescale semiconductor operation rs ?0 ? none (translates to sub r0, rs, r0) subtracts zero from the content of register rs using binary subtraction and discards the result. ccr effects code and cpu cycles tst test register tst nzvc ???? n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. v: set if a twos complement over?w resulted from the operation; cleared otherwise. rs[15] & result[15] c: set if there is a carry from the bit 15 of the result; cleared otherwise. rs1[15] & result[15] source form address mode machine code cycles tst rs tri 0 0 0 1 1 0 0 0 rs1 0 0 0 0 0 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 313 operation ~(rs1 ^ rs2) ? rd ~(rd ^ imm16) ? rd (translates to xnor rd, #imm16{15:8]; xnor rd, #imm16[7:0]) performs a bit wise logical exclusive nor between two 16 bit values and stores the result in the destination register rd. remark: using r0 as a source registers will calculate the ones complement of the other source register. using r0 as both source operands will ?l rd with $ffff. ccr effects code and cpu cycles xnor logical exclusive nor xnor nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the result is $0000; cleared otherwise. refer to xnorh instruction for #imm16 operations. v: 0; cleared. c: not affected. source form address mode machine code cycles xnor rd, rs1, rs2 tri 0 0 0 1 0 rd rs1 rs2 1 1 p xnor rd, #imm16 imm8 1 0 1 1 0 rd imm16[7:0] p imm8 1 0 1 1 1 rd imm16[15:8] p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 314 freescale semiconductor operation ~(rd.h ^ imm8) ? rd.h performs a bit wise logical exclusive nor between the high byte of register rd and an immediate 8 bit constant and stores the result in the destination register rd.h. the low byte of rd is not affected. ccr effects code and cpu cycles xnorh logical exclusive nor immediate 8 bit constant (high byte) xnorh nzvc ?? 0 n: set if bit 15 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles xnorh rd, #imm8 imm8 1 0 1 1 1 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 315 operation ~(rd.l ^ imm8) ? rd.l performs a bit wise logical exclusive nor between the low byte of register rd and an immediate 8 bit constant and stores the result in the destination register rd.l. the high byte of rd is not affected. ccr effects code and cpu cycles xnorl logical exclusive nor immediate 8 bit constant (low byte) xnorl nzvc ?? 0 n: set if bit 7 of the result is set; cleared otherwise. z: set if the 8 bit result is $00; cleared otherwise. v: 0; cleared. c: not affected. source form address mode machine code cycles xnorl rd, #imm8 imm8 1 0 1 1 0 rd imm8 p 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 316 freescale semiconductor 5.8.6 instruction coding table 5-17 summarizes all xgate instructions in the order of their machine coding. table 5-17. instruction set summary (sheet 1 of 3) functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 return to scheduler and others brk 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nop 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 rts 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 sif 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 semaphore instructions csem imm3 0 0 0 0 0 imm3 11110000 csem rs 0 0 0 0 0 rs 11110001 ssem imm3 0 0 0 0 0 imm3 11110010 ssem rs 0 0 0 0 0 rs 11110011 single register instructions sex rd 0 0 0 0 0 rd 11110100 par rd 0 0 0 0 0 rd 11110101 jal rd 0 0 0 0 0 rd 11110110 sif rs 0 0 0 0 0 rs 11110111 special move instructions tfr rd,ccr 0 0 0 0 0 rd 11111000 tfr ccr,rs 0 0 0 0 0 rs 11111001 tfr rd,pc 0 0 0 0 0 rd 11111010 shift instructions dyadic bffo rd, rs 0 0 0 0 1 rd rs 1 0 0 0 0 asr rd, rs 0 0 0 0 1 rd rs 1 0 0 0 1 csl rd, rs 0 0 0 0 1 rd rs 1 0 0 1 0 csr rd, rs 0 0 0 0 1 rd rs 1 0 0 1 1 lsl rd, rs 0 0 0 0 1 rd rs 1 0 1 0 0 lsr rd, rs 0 0 0 0 1 rd rs 1 0 1 0 1 rol rd, rs 0 0 0 0 1 rd rs 1 0 1 1 0 ror rd, rs 0 0 0 0 1 rd rs 1 0 1 1 1 shift instructions immediate asr rd, #imm4 0 0 0 0 1 rd imm4 1 0 0 1 csl rd, #imm4 0 0 0 0 1 rd imm4 1 0 1 0 csr rd, #imm4 0 0 0 0 1 rd imm4 1 0 1 1 lsl rd, #imm4 0 0 0 0 1 rd imm4 1 1 0 0 lsr rd, #imm4 0 0 0 0 1 rd imm4 1 1 0 1 rol rd, #imm4 0 0 0 0 1 rd imm4 1 1 1 0 ror rd, #imm4 0 0 0 0 1 rd imm4 1 1 1 1 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 317 logical triadic and rd, rs1, rs2 00010 rd rs1 rs2 00 or rd, rs1, rs2 00010 rd rs1 rs2 10 xnor rd, rs1, rs2 00010 rd rs1 rs2 11 arithmetic triadic for compare use sub r0,rs1,rs2 sub rd, rs1, rs2 0 0 0 1 1 rd rs1 rs2 0 0 sbc rd, rs1, rs2 0 0 0 1 1 rd rs1 rs2 0 1 add rd, rs1, rs2 0 0 0 1 1 rd rs1 rs2 1 0 adc rd, rs1, rs2 0 0 0 1 1 rd rs1 rs2 1 1 branches bcc rel9 0 0 1 0 0 0 0 rel9 bcs rel9 0 0 1 0 0 0 1 rel9 bne rel9 0 0 1 0 0 1 0 rel9 beq rel9 0 0 1 0 0 1 1 rel9 bpl rel9 0 0 1 0 1 0 0 rel9 bmi rel9 0 0 1 0 1 0 1 rel9 bvc rel9 0 0 1 0 1 1 0 rel9 bvs rel9 0 0 1 0 1 1 1 rel9 bhi rel9 0 0 1 1 0 0 0 rel9 bls rel9 0 0 1 1 0 0 1 rel9 bge rel9 0 0 1 1 0 1 0 rel9 blt rel9 0 0 1 1 0 1 1 rel9 bgt rel9 0 0 1 1 1 0 0 rel9 ble rel9 0 0 1 1 1 0 1 rel9 bra rel10 0 0 1 1 1 1 rel10 load and store instructions ldb rd, (rb, #offs5) 0 1 0 0 0 rd rb offs5 ldw rd, (rb, #offs5) 0 1 0 0 1 rd rb offs5 stb rs, (rb, #offs5) 0 1 0 1 0 rs rb offs5 stw rs, (rb, #offs5) 0 1 0 1 1 rs rb offs5 ldb rd, (rb, ri) 0 1 1 0 0 rd rb ri 0 0 ldw rd, (rb, ri) 0 1 1 0 1 rd rb ri 0 0 stb rs, (rb, ri) 0 1 1 1 0 rs rb ri 0 0 stw rs, (rb, ri) 0 1 1 1 1 rs rb ri 0 0 ldb rd, (rb, ri+) 0 1 1 0 0 rd rb ri 0 1 ldw rd, (rb, ri+) 0 1 1 0 1 rd rb ri 0 1 stb rs, (rb, ri+) 0 1 1 1 0 rs rb ri 0 1 stw rs, (rb, ri+) 0 1 1 1 1 rs rb ri 0 1 ldb rd, (rb, ?i) 0 1 1 0 0 rd rb ri 1 0 ldw rd, (rb, ?i) 0 1 1 0 1 rd rb ri 1 0 stb rs, (rb, ?i) 0 1 1 1 0 rs rb ri 1 0 stw rs, (rb, ?i) 0 1 1 1 1 rs rb ri 1 0 bit field instructions bfext rd, rs1, rs2 0 1 1 0 0 rd rs1 rs2 1 1 bfins rd, rs1, rs2 0 1 1 0 1 rd rs1 rs2 1 1 bfinsi rd, rs1, rs2 0 1 1 1 0 rd rs1 rs2 1 1 bfinsx rd, rs1, rs2 0 1 1 1 1 rd rs1 rs2 1 1 logic immediate instructions andl rd, #imm8 1 0 0 0 0 rd imm8 table 5-17. instruction set summary (sheet 2 of 3) functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 318 freescale semiconductor andh rd, #imm8 1 0 0 0 1 rd imm8 bitl rd, #imm8 1 0 0 1 0 rd imm8 bith rd, #imm8 1 0 0 1 1 rd imm8 orl rd, #imm8 1 0 1 0 0 rd imm8 orh rd, #imm8 1 0 1 0 1 rd imm8 xnorl rd, #imm8 1 0 1 1 0 rd imm8 xnorh rd, #imm8 1 0 1 1 1 rd imm8 arithmetic immediate instructions subl rd, #imm8 1 1 0 0 0 rd imm8 subh rd, #imm8 1 1 0 0 1 rd imm8 cmpl rs, #imm8 1 1 0 1 0 rs imm8 cpch rs, #imm8 1 1 0 1 1 rs imm8 addl rd, #imm8 1 1 1 0 0 rd imm8 addh rd, #imm8 1 1 1 0 1 rd imm8 ldl rd, #imm8 1 1 1 1 0 rd imm8 ldh rd, #imm8 1 1 1 1 1 rd imm8 table 5-17. instruction set summary (sheet 3 of 3) functionality 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 319 5.9 initialization and application information 5.9.1 initialization the recommended initialization of the xgate is as follows: 1. clear the xge bit to suppress any incoming service requests. 2. make sure that no thread is running on the xgate. this can be done in several ways: a) poll the xgchid register until it reads $00. also poll xgdbg and xgsweif to make sure that the xgate has not been stopped. b) enter debug mode by setting the xgdbg bit. clear the xgchid register. clear the xgdbg bit. the recommended method is a). 3. set the xgvbr register to the lowest address of the xgate vector space. 4. clear all channel id ?gs. 5. copy xgate vectors and code into the ram. 6. initialize the s12x_int module. 7. enable the xgate by setting the xge bit. the following code example implements the xgate initialization sequence. 5.9.2 code example (transmit "hello world!" on sci) cpu s12x ;########################################### ;# symbols # ;########################################### sci_regs equ $00c8 ;sci register space scibdh equ sci_regs+$00 ;sci baud rate register scibdl equ sci_regs+$00 ;sci baud rate register scicr2 equ sci_regs+$03 ;sci control register 2 scisr1 equ sci_regs+$04 ;sci status register 1 scidrl equ sci_regs+$07 ;sci control register 2 tie equ $80 ;tie bit mask te equ $08 ;te bit mask re equ $04 ;re bit mask sci_vec equ $d6 ;sci vector number int_regs equ $0120 ;s12x_int register space int_cfaddr equ int_regs+$07 ;interrupt configuration address register int_cfdata equ int_regs+$08 ;interrupt configuration data registers rqst equ $80 ;rqst bit mask xgate_regs equ $0380 ;xgate register space xgmctl equ xgate_regs+$00 ;xgate module control register xgmctl_clear equ $fa02 ;clear all xgmctl bits xgmctl_enable equ $8282 ;enable xgate xgchid equ xgate_regs+$02 ;xgate channel id register xgvbr equ xgate_regs+$06 ;xgate isp select register xgif equ xgate_regs+$08 ;xgate interrupt flag vector 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 320 freescale semiconductor xgswt equ xgate_regs+$18 ;xgate software trigger register xgsem equ xgate_regs+$1a ;xgate semaphore register rpage equ $0016 ram_size equ 32*$400 ;32k ram ram_start equ $1000 ram_start_xg equ $10000-ram_size ram_start_glob equ $100000-ram_size xgate_vectors equ ram_start xgate_vectors_xg equ ram_start_xg xgate_data equ ram_start+(4*128) xgate_data_xg equ ram_start_xg+(4*128) xgate_code equ xgate_data+(xgate_code_flash-xgate_data_flash) xgate_code_xg equ xgate_data_xg+(xgate_code_flash-xgate_data_flash) bus_freq_hz equ 40000000 ;########################################### ;# s12xe vector table # ;########################################### org $ff10 ;non-maskable interrupts dw dummy_isr dummy_isr dummy_isr dummy_isr org $fff4 ;non-maskable interrupts dw dummy_isr dummy_isr dummy_isr ;########################################### ;# disable cop # ;########################################### org $ff0e dw $fffe org $c000 start_of_code ;########################################### ;# initialize s12xe core # ;########################################### sei movb #(ram_start_glob>>12), rpage;set ram page ;########################################### ;# initialize sci # ;########################################### init_sci movw #(bus_freq_hz/(16*9600)), scibdh;set baud rate movb #(tie|te), scicr2;enable tx buffer empty interrupt ;########################################### ;# initialize s12x_int # ;########################################### init_int movb #(sci_vec&$f0), int_cfaddr ;switch sci interrupts to xgate movb #rqst|$01, int_cfdata+((sci_vec&$0f)>>1) 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 321 ;########################################### ;# initialize xgate # ;########################################### init_xgate movw #xgmctl_clear , xgmctl;clear all xgmctl bits init_xgate_busy_loop tst xgchid ;wait until current thread is finished bne init_xgate_busy_loop ldx #xgif ;clear all channel interrupt flags ldd #$ffff std 2,x+ std 2,x+ std 2,x+ std 2,x+ std 2,x+ std 2,x+ std 2,x+ std 2,x+ movw #xgate_vectors_xg, xgvbr;set vector base register movw #$ff00, xgswt ;clear all software triggers ;########################################### ;# initialize xgate vector table # ;########################################### ldaa #128 ;build xgate vector table ldy #xgate_vectors init_xgate_vectab_loop movw #xgate_dummy_isr_xg, 4,y+ dbne a, init_xgate_vectab_loop movw #xgate_code_xg, ram_start+(2*sci_vec) movw #xgate_data_xg, ram_start+(2*sci_vec)+2 ;########################################### ;# copy xgate code # ;########################################### copy_xgate_code ldx #xgate_data_flash copy_xgate_code_loop movw 2,x+, 2,y+ movw 2,x+, 2,y+ movw 2,x+, 2,y+ movw 2,x+, 2,y+ cpx #xgate_code_flash_end bls copy_xgate_code_loop ;########################################### ;# start xgate # ;########################################### start_xgate movw #xgmctl_enable, xgmctl;enable xgate bra * ;########################################### ;# dummy interrupt service routine # ;########################################### dummy_isr rti cpu xgate 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 322 freescale semiconductor ;########################################### ;# xgate data # ;########################################### align 1 xgate_data_flash equ * xgate_data_sci equ *-xgate_data_flash dw sci_regs ;pointer to sci register space xgate_data_idx equ *-xgate_data_flash db xgate_data_msg ;string pointer xgate_data_msg equ *-xgate_data_flash fcc "hello world! ;ascii string db $0d ;cr ;########################################### ;# xgate code # ;########################################### align 1 xgate_code_flash ldw r2,(r1,#xgate_data_sci);sci -> r2 ldb r3,(r1,#xgate_data_idx);msg -> r3 ldb r4,(r1,r3+) ;curr. char -> r4 stb r3,(r1,#xgate_data_idx);r3 -> idx ldb r0,(r2,#(scisr1-sci_regs));initiate sci transmit stb r4,(r2,#(scidrl-sci_regs));initiate sci transmit cmpl r4,#$0d beq xgate_code_done rts xgate_code_done ldl r4,#$00 ;disable sci interrupts stb r4,(r2,#(scicr2-sci_regs)) ldl r3,#xgate_data_msg;reset r3 stb r3,(r1,#xgate_data_idx) xgate_code_flash_end rts xgate_dummy_isr_xg equ (xgate_code_flash_end-xgate_code_flash)+xgate_code_xg 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 323 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 324 freescale semiconductor 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 325 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 326 freescale semiconductor 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 327 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 328 freescale semiconductor 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 329 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 330 freescale semiconductor 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 331 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 332 freescale semiconductor 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 333 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 334 freescale semiconductor 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 335 4 .com u datasheet
chapter 5 xgate (s12xgatev2) MC9S12XHZ512 data sheet, rev. 1.02 336 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 337 chapter 6 security (s12x9secv2) 6.1 introduction this speci?ation describes the function of the security mechanism in the s12x chip family (s12x9secv2). 6.1.1 features the user must be reminded that part of the security must lie with the application code. an extreme example would be application code that dumps the contents of the internal memory. this would defeat the purpose of security. at the same time, the user may also wish to put a backdoor in the application program. an example of this is the user downloads a security key through the sci, which allows access to a programming routine that updates parameters stored in another section of the flash memory. the security features of the s12x chip family (in secure mode) are: protect the contents of non-volatile memories (flash, eeprom) execution of nvm commands is restricted disable access to internal memory via background debug module (bdm) disable access to internal flash/eeprom in expanded modes disable debugging features for cpu and xgate table 6-1 gives an overview over availability of security relevant features in unsecure and secure modes. 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 338 freescale semiconductor 6.1.2 modes of operation 6.1.3 securing the microcontroller once the user has programmed the flash and eeprom, the chip can be secured by programming the security bits located in the options/security byte in the flash memory array. these non-volatile bits will keep the device secured through reset and power-down. the options/security byte is located at address 0xff0f (= global address 0x7f_ff0f) in the flash memory array. this byte can be erased and programmed like any other flash location. two bits of this byte are used for security (sec[1:0]). on devices which have a memory page window, the flash options/security byte is also available at address 0xbf0f by selecting page 0x3f with the ppage register. the contents of this byte are copied into the flash security register (fsec) during a reset sequence. table 6-1. features availability in unsecure and secure modes unsecure mode secure mode ns ss nx es ex st ns ss nx es ex st flash array access ??? 1 1 availability of flash arrays in the memory map depends on romctl/eromctl pins and/or the state of the romon/eromon bits in the mmcctl1 register. please refer to the s12x_mmc block guide for detailed information. ? 1 ? 1 ? 1 ?? eeprom array access ???????? nvm commands ? 2 2 restricted nvm command set only. please refer to the ftx/eetx block guides for detailed information. ?? 2 ? 2 ? 2 ?? 2 ? 2 ? 2 ? 2 ? 2 ? 2 bdm ?????? ? 3 3 bdm hardware commands restricted to peripheral registers only. dbg module trace ?????? xgate debugging ?????? external bus interface ???? ???? internal status visible multiplexed on external bus ?? ?? internal accesses visible on external bus ? ? 76543210 0xff0f keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 figure 6-1. flash options/security byte 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 339 the meaning of the bits keyen[1:0] is shown in table 6-2 . please refer to section 6.1.5.1, ?nsecuring the mcu using the backdoor key access for more information. the meaning of the security bits sec[1:0] is shown in table 6-3 . for security reasons, the state of device security is controlled by two bits. to put the device in unsecured mode, these bits must be programmed to sec[1:0] = ?0? all other combinations put the device in a secured mode. the recommended value to put the device in secured state is the inverse of the unsecured state, i.e. sec[1:0] = ?1? note please refer to the flash block guide (ftx) for actual security con?uration (in section ?lash module security?. 6.1.4 operation of the secured microcontroller by securing the device, unauthorized access to the eeprom and flash memory contents can be prevented. however, it must be understood that the security of the eeprom and flash memory contents also depends on the design of the application program. for example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the eeprom and flash memory contents even when the microcontroller is in the secure state. in this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. secured operation has the following effects on the microcontroller: table 6-2. backdoor key access enable bits keyen[1:0] backdoor key access enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) table 6-3. security bits sec[1:0] security state 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured) 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 340 freescale semiconductor 6.1.4.1 normal single chip mode (ns) background debug module (bdm) operation is completely disabled. execution of flash and eeprom commands is restricted. please refer to the nvm block guide (ftx) for details. tracing code execution using the dbg module is disabled. debugging xgate code (breakpoints, single-stepping) is disabled. 6.1.4.2 special single chip mode (ss) bdm ?mware commands are disabled. bdm hardware commands are restricted to the register space. execution of flash and eeprom commands is restricted. please refer to the nvm block guide (ftx) for details. tracing code execution using the dbg module is disabled. debugging xgate code (breakpoints, single-stepping) is disabled. special single chip mode means bdm is active after reset. the availability of bdm ?mware commands depends on the security state of the device. the bdm secure ?mware ?st performs a blank check of both the flash memory and the eeprom. if the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate flash memory location can be changed if the blank check fails, security will remain active, only the bdm hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. this will allow the bdm to be used to erase the eeprom and flash memory without giving access to their contents. after erasing both flash memory and eeprom, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to ?nsecured?state via bdm. while the bdm is executing the blank check, the bdm interface is completely blocked, which means that all bdm commands are temporarily blocked. 6.1.4.3 expanded modes (nx, es, ex, and st) bdm operation is completely disabled. internal flash memory and eeprom are disabled. execution of flash and eeprom commands is restricted. please refer to the nvm block guide (ftx) for details. tracing code execution using the dbg module is disabled. debugging xgate code (breakpoints, single-stepping) is disabled. 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 341 6.1.5 unsecuring the microcontroller unsecuring the microcontroller can be done by three different methods: 1. backdoor key access 2. reprogramming the security bits 3. complete memory erase (special modes) 6.1.5.1 unsecuring the mcu using the backdoor key access in normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. this method requires that: the backdoor key at 0xff00?xff07 (= global addresses 0x7f_ff00?x7f_ff07) has been programmed to a valid value. the keyen[1:0] bits within the flash options/security byte select ?nabled? in single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. the backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). it is not possible to download the backdoor keys using background debug mode. the backdoor key access method allows debugging of a secured microcontroller without having to erase the flash. this is particularly useful for failure analysis. note no word of the backdoor key is allowed to have the value 0x0000 or 0xffff. 6.1.5.2 backdoor key access sequence these are the necessary steps for a successful backdoor key access sequence: 1. set the keyacc bit in the flash con?uration register fcnfg. 2. write the ?st 16-bit word of the backdoor key to 0xff00 (0x7f_ff00). 3. write the second 16-bit word of the backdoor key to 0xff02 (0x7f_ff02). 4. write the third 16-bit word of the backdoor key to 0xff04 (0x7f_ff04). 5. write the fourth 16-bit word of the backdoor key to 0xff06 (0x7f_ff06). 6. clear the keyacc bit in the flash con?uration register fcnfg. note flash cannot be read while keyacc is set. therefore the code for the backdoor key access sequence must execute from ram. 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 342 freescale semiconductor if all four 16-bit words match the flash contents at 0xff00?xff07 (0x7f_ff00?x7f_ff07), the microcontroller will be unsecured and the security bits sec[1:0] in the flash security register fsec will be forced to the unsecured state (?0?. the contents of the flash options/security byte are not changed by this procedure, and so the microcontroller will revert to the secure state after the next reset unless further action is taken as detailed below. if any of the four 16-bit words does not match the flash contents at 0xff00?xff07 (0x7f_ff00?x7f_ff07), the microcontroller will remain secured. 6.1.6 reprogramming the security bits in normal single chip mode (ns), security can also be disabled by erasing and reprogramming the security bits within flash options/security byte to the unsecured value. because the erase operation will erase the entire sector from 0xfe00?xffff (0x7f_fe00?x7f_ffff), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. the application software can only erase and program the flash options/security byte if the flash sector containing the flash options/security byte is not protected (see flash protection). thus flash protection is a useful means of preventing this method. the microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. this method requires that: the application software previously programmed into the microcontroller has been designed to have the capability to erase and program the flash options/security byte, or security is ?st disabled using the backdoor key method, allowing bdm to be used to issue commands to erase and program the flash options/security byte. the flash sector containing the flash options/security byte is not protected. 6.1.7 complete memory erase (special modes) the microcontroller can be unsecured in special modes by erasing the entire eeprom and flash memory contents. when a secure microcontroller is reset into special single chip mode (ss), the bdm ?mware veri?s whether the eeprom and flash memory are erased. if any eeprom or flash memory address is not erased, only bdm hardware commands are enabled. bdm hardware commands can then be used to write to the eeprom and flash registers to mass erase the eeprom and all flash memory blocks. when next reset into special single chip mode, the bdm ?mware will again verify whether all eeprom and flash memory are erased, and this being the case, will enable all bdm commands, allowing the flash options/security byte to be programmed to the unsecured value. the security bits sec[1:0] in the flash security register will indicate the unsecure state following the next reset. 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 343 special single chip erase and unsecure sequence: 1. reset into special single chip mode. 2. write an appropriate value to the eclkdiv register for correct timing. 3. write 0xff to the eprot register to disable protection. 4. write 0x30 to the estat register to clear the pviol and accerr bits. 5. write 0x0000 to the edata register (0x011a?x011b). 6. write 0x0000 to the eaddr register (0x0118?x0119). 7. write 0x41 (mass erase) to the ecmd register. 8. write 0x80 to the estat register to clear cbeif. 9. write an appropriate value to the fclkdiv register for correct timing. 10. write 0x00 to the fcnfg register to select flash block 0. 11. write 0x10 to the ftstmod register (0x0102) to set the wrall bit, so the following writes affect all flash blocks. 12. write 0xff to the fprot register to disable protection. 13. write 0x30 to the fstat register to clear the pviol and accerr bits. 14. write 0x0000 to the fdata register (0x010a?x010b). 15. write 0x0000 to the faddr register (0x0108?x0109). 16. write 0x41 (mass erase) to the fcmd register. 17. write 0x80 to the fstat register to clear cbeif. 18. wait until all ccif ?gs are set. 19. reset back into special single chip mode. 20. write an appropriate value to the fclkdiv register for correct timing. 21. write 0x00 to the fcnfg register to select flash block 0. 22. write 0xff to the fprot register to disable protection. 23. write 0xffbe to flash address 0xff0e. 24. write 0x20 (program) to the fcmd register. 25. write 0x80 to the fstat register to clear cbeif. 26. wait until the ccif ?g in fstat is are set. 27. reset into any mode. 4 .com u datasheet
chapter 6 security (s12x9secv2) MC9S12XHZ512 data sheet, rev. 1.02 344 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 345 chapter 7 clocks and reset generator (crgv6) 7.1 introduction this speci?ation describes the function of the clocks and reset generator (crg). 7.1.1 features the main features of this block are: phase locked loop (pll) frequency multiplier reference divider automatic bandwidth control mode for low-jitter operation automatic frequency lock detector interrupt request on entry or exit from locked condition self clock mode in absence of reference clock system clock generator clock quality check user selectable fast wake-up from stop in self-clock mode for power saving and immediate program execution clock switch for either oscillator or pll based system clocks computer operating properly (cop) watchdog timer with time-out clear window system reset generation from the following possible sources: power on reset low voltage reset illegal address reset cop reset loss of clock reset external pin reset real-time interrupt (rti) 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 346 freescale semiconductor 7.1.2 modes of operation this subsection lists and brie? describes all operating modes supported by the crg. run mode all functional parts of the crg are running during normal run mode. if rti or cop functionality is required, the individual bits of the associated rate select registers (copctl, rtictl) have to be set to a nonzero value. wait mode in this mode, the pll can be disabled automatically depending on the pllsel bit in the clksel register. stop mode depending on the setting of the pstp bit, stop mode can be differentiated between full stop mode (pstp = 0) and pseudo stop mode (pstp = 1). full stop mode the oscillator is disabled and thus all system and core clocks are stopped. the cop and the rti remain frozen. pseudo stop mode the oscillator continues to run and most of the system and core clocks are stopped. if the respective enable bits are set, the cop and rti will continue to run, or else they remain frozen. self clock mode self clock mode will be entered if the clock monitor enable bit (cme) and the self clock mode enable bit (scme) are both asserted and the clock monitor in the oscillator block detects a loss of clock. as soon as self clock mode is entered, the crg starts to perform a clock quality check. self clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). self clock mode should be used for safety purposes only. it provides reduced functionality to the mcu in case a loss of clock is causing severe system conditions. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 347 7.1.3 block diagram figure 7-1 shows a block diagram of the crg. figure 7-1. crg block diagram crg registers clock and reset cop reset rti pll xfc v ddpll v sspll oscillator extal xtal control bus clock system reset oscillator clock pllclk oscclk core clock cm fail clock quality checker reset generator xclks power on reset low voltage reset cop timeout real time interrupt pll lock interrupt self clock mode interrupt voltage regulator s12x_mmc illegal address reset clock monitor 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 348 freescale semiconductor 7.2 external signal description this section lists and describes the signals that connect off chip. 7.2.1 v ddpll and v sspll ?operating and ground voltage pins these pins provide operating voltage (v ddpll ) and ground (v sspll ) for the pll circuitry. this allows the supply voltage to the pll to be independently bypassed. even if pll usage is not required, v ddpll and v sspll must be connected to properly. 7.2.2 xfc ?external loop filter pin a passive external loop ?ter must be placed on the xfc pin. the ?ter is a second-order, low-pass ?ter that eliminates the vco input ripple. the value of the external ?ter network and the reference frequency determines the speed of the corrections and the stability of the pll. refer to the device speci?ation for calculation of pll loop filter (xfc) components . if pll usage is not required, the xfc pin must be tied to v ddpll . figure 7-2. pll loop filter connections 7.2.3 reset ?reset pin reset is an active low bidirectional reset pin. as an input. it initializes the mcu asynchronously to a known start-up state. as an open-drain output, it indicates that a system reset (internal to the mcu) has been triggered. 7.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the crg. mcu xfc r s c s v ddpll c p 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 349 7.3.1 module memory map table 7-1 gives an overview on all crg registers. note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. table 7-1. crg memory map address offset use access 0x_00 crg synthesizer register (synr) r/w 0x_01 crg reference divider register (refdv) r/w 0x_02 crg test flags register (ctflg) 1 1 ctflg is intended for factory test purposes only. r/w 0x_03 crg flags register (crgflg) r/w 0x_04 crg interrupt enable register (crgint) r/w 0x_05 crg clock select register (clksel) r/w 0x_06 crg pll control register (pllctl) r/w 0x_07 crg rti control register (rtictl) r/w 0x_08 crg cop control register (copctl) r/w 0x_09 crg force and bypass test register (forbyp) 2 2 forbyp is intended for factory test purposes only. r/w 0x_0a crg test control register (ctctl) 3 3 ctctl is intended for factory test purposes only. r/w 0x_0b crg cop arm/timer reset (armcop) r/w 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 350 freescale semiconductor 7.3.2 register descriptions this section describes in address order all the crg registers and their individual bits. register name bit 7 6 5 4 3 2 1 bit 0 synr r 0 0 syn5 syn4 syn3 syn2 syn1 syn0 w refdv r 0 0 refdv5 refdv4 refdv3 refdv2 refdv1 refdv0 w ctflg r 00000000 w crgflg r rtif porf lvrf lockif lock track scmif scm w crgint r rtie ilaf 0 lockie 00 scmie 0 w clksel r pllsel pstp 00 pllwai 0 rtiwai copwai w pllctl r cme pllon auto acq fstwkp pre pce scme w rtictl r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w copctl r wcop rsbck 000 cr2 cr1 cr0 w wrtmask forbyp r 00000000 w ctctl r 10000000 w armcop r 00000000 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 = unimplemented or reserved figure 7-3. s12crgv6 register summary 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 351 7.3.2.1 crg synthesizer register (synr) the synr register controls the multiplication factor of the pll. if the pll is on, the count in the loop divider (synr) register effectively multiplies up the pll clock (pllclk) from the reference frequency by 2 x (synr + 1). pllclk will not be below the minimum vco frequency (f scm ). note if pll is selected (pllsel=1), bus clock = pllclk / 2 bus clock must not exceed the maximum operating system frequency. read: anytime write: anytime except if pllsel = 1 note write to this register initializes the lock detector bit and the track detector bit. 7.3.2.2 crg reference divider register (refdv) the refdv register provides a ?er granularity for the pll multiplier steps. the count in the reference divider divides oscclk frequency by refdv + 1. read: anytime write: anytime except when pllsel = 1 note write to this register initializes the lock detector bit and the track detector bit. 76543210 r0 0 syn5 syn4 syn3 syn2 syn1 syn0 w reset 0 0 0 00000 = unimplemented or reserved figure 7-4. crg synthesizer register (synr) 76543210 r0 0 refdv5 refdv4 refdv3 refdv2 refdv1 refdv0 w reset 0 0 0 00000 = unimplemented or reserved figure 7-5. crg reference divider register (refdv) pllclk 2xoscclkx synr 1 + () refdv 1 + () ----------------------------------- - = 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 352 freescale semiconductor 7.3.2.3 reserved register (ctflg) this register is reserved for factory testing of the crg module and is not available in normal modes. read: always reads 0x_00 in normal modes write: unimplemented in normal modes note writing to this register when in special mode can alter the crg fucntionality. 7.3.2.4 crg flags register (crgflg) this register provides crg status bits and ?gs. read: anytime write: refer to each bit for individual write conditions 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 7-6. reserved register (ctflg) 76543210 r rtif porf lvrf lockif lock track scmif scm w reset 0 12 00000 1. porf is set to 1 when a power on reset occurs. unaffected by system reset. 2. lvrf is set to 1 when a low-voltage reset occurs. unaffected by system reset. = unimplemented or reserved figure 7-7. crg flags register (crgflg) table 7-2. crgflg field descriptions field description 7 rtif real time interrupt flag rtif is set to 1 at the end of the rti period. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (rtie = 1), rtif causes an interrupt request. 0 rti time-out has not yet occurred. 1 rti time-out has occurred. 6 porf power on reset flag porf is set to 1 when a power on reset occurs. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 power on reset has not occurred. 1 power on reset has occurred. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 353 5 lvrf low voltage reset flag if low voltage reset feature is not available (see device speci?ation) lvrf always reads 0. lvrf is set to 1 when a low voltage reset occurs. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 low voltage reset has not occurred. 1 low voltage reset has occurred. 4 lockif pll lock interrupt flag ?lockif is set to 1 when lock status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect.if enabled (lockie = 1), lockif causes an interrupt request. 0 no change in lock bit. 1 lock bit has changed. 3 lock lock status bit lock re?cts the current state of pll lock condition. this bit is cleared in self clock mode. writes have no effect. 0 pll vco is not within the desired tolerance of the target frequency. 1 pll vco is within the desired tolerance of the target frequency. 2 track track status bit ?track re?cts the current state of pll track condition. this bit is cleared in self clock mode. writes have no effect. 0 acquisition mode status. 1tracking mode status. 1 scmif self clock mode interrupt flag ?scmif is set to 1 when scm status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (scmie = 1), scmif causes an interrupt request. 0 no change in scm bit. 1 scm bit has changed. 0 scm self clock mode status bit ?scm re?cts the current clocking mode. writes have no effect. 0 mcu is operating normally with oscclk available. 1 mcu is operating in self clock mode with oscclk in an unknown state. all clocks are derived from pllclk running at its minimum frequency f scm . table 7-2. crgflg field descriptions (continued) field description 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 354 freescale semiconductor 7.3.2.5 crg interrupt enable register (crgint) this register enables crg interrupt requests. read: anytime write: anytime 76543210 r rtie ilaf 0 lockie 00 scmie 0 w reset 0 1 000000 1. ilaf is set to 1 when an illegal address reset occurs. unaffected by system reset. cleared by power on or low voltage reset. = unimplemented or reserved figure 7-8. crg interrupt enable register (crgint) table 7-3. crgint field descriptions field description 7 rtie real time interrupt enable bit 0 interrupt requests from rti are disabled. 1 interrupt will be requested whenever rtif is set. 6 ilaf illegal address reset flag ilaf is set to 1 when an illegal address reset occurs. refer to s12xmmc block guide for details. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 illegal address reset has not occurred. 1 illegal address reset has occurred. 4 lockie lock interrupt enable bit 0 lock interrupt requests are disabled. 1 interrupt will be requested whenever lockif is set. 1 scmie self clockmmode interrupt enable bit 0 scm interrupt requests are disabled. 1 interrupt will be requested whenever scmif is set. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 355 7.3.2.6 crg clock select register (clksel) this register controls crg clock selection. refer to figure 7-17 for more details on the effect of each bit. read: anytime write: refer to each bit for individual write conditions 76543210 r pllsel pstp 00 pllwai 0 rtiwai copwai w reset 0 0 0 00000 = unimplemented or reserved figure 7-9. crg clock select register (clksel) table 7-4. clksel field descriptions field description 7 pllsel pll select bit write anytime. writing a1 when lock = 0 and auto = 1, or track = 0 and auto = 0 has no effect this prevents the selection of an unstable pllclk as sysclk. pllsel bit is cleared when the mcu enters self clock mode, stop mode or wait mode with pllwai bit set. 0 system clocks are derived from oscclk (bus clock = oscclk / 2). 1 system clocks are derived from pllclk (bus clock = pllclk / 2). 6 pstp pseudo stop bit write: anytime this bit controls the functionality of the oscillator during stop mode. 0 oscillator is disabled in stop mode. 1 oscillator continues to run in stop mode (pseudo stop). note: pseudo stop mode allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption. 3 pllwai pll stops in wait mode bit write: anytime if pllwai is set, the crg will clear the pllsel bit before entering wait mode. the pllon bit remains set during wait mode, but the pll is powered down. upon exiting wait mode, the pllsel bit has to be set manually if pll clock is required. while the pllwai bit is set, the auto bit is set to 1 in order to allow the pll to automatically lock on the selected target frequency after exiting wait mode. 0 pll keeps running in wait mode. 1 pll stops in wait mode. 1 rtiwai rti stops in wait mode bit write: anytime 0 rti keeps running in wait mode. 1 rti stops and initializes the rti dividers whenever the part goes into wait mode. 0 copwai cop stops in wait mode bit normal modes: write once special modes: write anytime 0 cop keeps running in wait mode. 1 cop stops and initializes the cop counter whenever the part goes into wait mode. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 356 freescale semiconductor 7.3.2.7 crg pll control register (pllctl) this register controls the pll functionality. read: anytime write: refer to each bit for individual write conditions 76543210 r cme pllon auto acq fstwkp pre pce scme w reset 1 1 1 10001 figure 7-10. crg pll control register (pllctl) table 7-5. pllctl field descriptions field description 7 cme clock monitor enable bit ?cme enables the clock monitor. write anytime except when scm = 1. 0 clock monitor is disabled. 1 clock monitor is enabled. slow or stopped clocks will cause a clock monitor reset sequence or self clock mode. note: operating with cme = 0 will not detect any loss of clock. in case of poor clock quality, this could cause unpredictable operation of the mcu! note: in stop mode (pstp = 0) the clock monitor is disabled independently of the cme bit setting and any loss of external clock will not be detected. also after wake-up from stop mode (pstp = 0) with fast wake-up enabled (fstwkp = 1) the clock monitor is disabled independently of the cme bit setting and any loss of external clock will not be detected. 6 pllon phase lock loop on bit pllon turns on the pll circuitry. in self clock mode, the pll is turned on, but the pllon bit reads the last latched value. write anytime except when pllsel = 1. 0 pll is turned off. 1 pll is turned on. if auto bit is set, the pll will lock automatically. 5 auto automatic bandwidth control bit ?auto selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the vco is running. write anytime except when pllwai = 1, because pllwai sets the auto bit to 1. 0 automatic mode control is disabled and the pll is under software control, using acq bit. 1 automatic mode control is enabled and acq bit has no effect. 4 acq acquisition bit write anytime. if auto=1 this bit has no effect. 0 low bandwidth ?ter is selected. 1 high bandwidth ?ter is selected. 3 fstwkp fast wake-up from full stop bit ?fstwkp enables fast wake-up from full stop mode. write anytime. if self-clock mode is disabled (scme = 0) this bit has no effect. 0 fast wake-up from full stop mode is disabled. 1 fast wake-up from full stop mode is enabled. when waking up from full stop mode the system will immediately resume operation i self-clock mode (see section 7.4.1.4, ?lock quality checker ). the scmif ?g will not be set. the system will remain in self-clock mode with oscillator and clock monitor disabled until fstwkp bit is cleared. the clearing of fstwkp will start the oscillator, the clock monitor and the clock quality check. if the clock quality check is successful, the crg will switch all system clocks to oscclk. the scmif ?g will be set. see application examples in figure 7-23 and figure 7-24 . 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 357 7.3.2.8 crg rti control register (rtictl) this register selects the timeout period for the real time interrupt. read: anytime write: anytime note a write to this register initializes the rti counter. 2 pre rti enable during pseudo stop bit ?pre enables the rti during pseudo stop mode. write anytime. 0 rti stops running during pseudo stop mode. 1 rti continues running during pseudo stop mode. note: if the pre bit is cleared the rti dividers will go static while pseudo stop mode is active. the rti dividers will not initialize like in wait mode with rtiwai bit set. 1 pce cop enable during pseudo stop bit ?pce enables the cop during pseudo stop mode. write anytime. 0 cop stops running during pseudo stop mode 1 cop continues running during pseudo stop mode note: if the pce bit is cleared, the cop dividers will go static while pseudo stop mode is active. the cop dividers will not initialize like in wait mode with copwai bit set. 0 scme self clock mode enable bit normal modes: write once special modes: write anytime scme can not be cleared while operating in self clock mode (scm = 1). 0 detection of crystal clock failure causes clock monitor reset (see section 7.5.2, ?lock monitor reset ). 1 detection of crystal clock failure forces the mcu in self clock mode (see section 7.4.2.2, ?elf clock mode? . 76543210 r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w reset 0 0 0 00000 figure 7-11. crg rti control register (rtictl) table 7-6. rtictl field descriptions field description 7 rtdec decimal or binary divider select bit ?rtdec selects decimal or binary based prescaler values. 0 binary based divider value. see table 7-7 1 decimal based divider value. see table 7-8 6? rtr[6:4] real time interrupt prescale rate select bits these bits select the prescale rate for the rti. see table 7-7 and table 7-8 . 3? rtr[3:0] real time interrupt modulus counter select bits ?these bits select the modulus counter target value to provide additional granularity. table 7-7 and table 7-8 show all possible divide values selectable by the rtictl register. the source clock for the rti is oscclk. table 7-5. pllctl field descriptions (continued) field description 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 358 freescale semiconductor table 7-7. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( 1) off * 2 10 2 11 2 12 2 13 2 14 2 15 2 16 0001 ( 2) off 2x2 10 2x2 11 2x2 12 2x2 13 2x2 14 2x2 15 2x2 16 0010 ( 3) off 3x2 10 3x2 11 3x2 12 3x2 13 3x2 14 3x2 15 3x2 16 0011 ( 4) off 4x2 10 4x2 11 4x2 12 4x2 13 4x2 14 4x2 15 4x2 16 0100 ( 5) off 5x2 10 5x2 11 5x2 12 5x2 13 5x2 14 5x2 15 5x2 16 0101 ( 6) off 6x2 10 6x2 11 6x2 12 6x2 13 6x2 14 6x2 15 6x2 16 0110 ( 7) off 7x2 10 7x2 11 7x2 12 7x2 13 7x2 14 7x2 15 7x2 16 0111 ( 8) off 8x2 10 8x2 11 8x2 12 8x2 13 8x2 14 8x2 15 8x2 16 1000 ( 9) off 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 ( 10) off 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 ( 11) off 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 ( 12) off 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 ( 13) off 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 ( 14) off 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16 1110 ( 15) off 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 ( 16) off 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 * denotes the default value out of reset.this value should be used to disable the rti to ensure future backwards compatibility. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 359 table 7-8. rti frequency divide rates for rtdec = 1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 ) 0000 ( 1) 1x10 3 2x10 3 5x10 3 10x10 3 20x10 3 50x10 3 100x10 3 200x10 3 0001 ( 2) 2x10 3 4x10 3 10x10 3 20x10 3 40x10 3 100x10 3 200x10 3 400x10 3 0010 ( 3) 3x10 3 6x10 3 15x10 3 30x10 3 60x10 3 150x10 3 300x10 3 600x10 3 0011 ( 4) 4x10 3 8x10 3 20x10 3 40x10 3 80x10 3 200x10 3 400x10 3 800x10 3 0100 ( 5) 5x10 3 10x10 3 25x10 3 50x10 3 100x10 3 250x10 3 500x10 3 1x10 6 0101 ( 6) 6x10 3 12x10 3 30x10 3 60x10 3 120x10 3 300x10 3 600x10 3 1.2x10 6 0110 ( 7) 7x10 3 14x10 3 35x10 3 70x10 3 140x10 3 350x10 3 700x10 3 1.4x10 6 0111 ( 8) 8x10 3 16x10 3 40x10 3 80x10 3 160x10 3 400x10 3 800x10 3 1.6x10 6 1000 ( 9) 9x10 3 18x10 3 45x10 3 90x10 3 180x10 3 450x10 3 900x10 3 1.8x10 6 1001 ( 10) 10 x10 3 20x10 3 50x10 3 100x10 3 200x10 3 500x10 3 1x10 6 2x10 6 1010 ( 11) 11 x10 3 22x10 3 55x10 3 110x10 3 220x10 3 550x10 3 1.1x10 6 2.2x10 6 1011 ( 12) 12x10 3 24x10 3 60x10 3 120x10 3 240x10 3 600x10 3 1.2x10 6 2.4x10 6 1100 ( 13) 13x10 3 26x10 3 65x10 3 130x10 3 260x10 3 650x10 3 1.3x10 6 2.6x10 6 1101 ( 14) 14x10 3 28x10 3 70x10 3 140x10 3 280x10 3 700x10 3 1.4x10 6 2.8x10 6 1110 ( 15) 15x10 3 30x10 3 75x10 3 150x10 3 300x10 3 750x10 3 1.5x10 6 3x10 6 1111 ( 16) 16x10 3 32x10 3 80x10 3 160x10 3 320x10 3 800x10 3 1.6x10 6 3.2x10 6 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 360 freescale semiconductor 7.3.2.9 crg cop control register (copctl) this register controls the cop (computer operating properly) watchdog. read: anytime write: 1. rsbck: anytime in special modes; write to ??but not to ??in all other modes 2. wcop, cr2, cr1, cr0: anytime in special modes write once in all other modes writing cr[2:0] to ?00?has no effect, but counts for the ?rite once?condition. writing wcop to ??has no effect, but counts for the ?rite once?condition. the cop time-out period is restarted if one these two conditions is true: 1. writing a nonzero value to cr[2:0] (anytime in special modes, once in all other modes) with wrtmask = 0. or 2. changing rsbck bit from ??to ?? 76543210 r wcop rsbck 000 cr2 cr1 cr0 w wrtmask reset 1 0000 1. refer to device user guide (section: crg) for reset values of wcop, cr2, cr1, and cr0. = unimplemented or reserved figure 7-12. crg cop control register (copctl) table 7-9. copctl field descriptions field description 7 wcop window cop mode bit when set, a write to the armcop register must occur in the last 25% of the selected period. a write during the ?st 75% of the selected period will reset the part. as long as all writes occur during this window, 0x_55 can be written as often as desired. once 0x_aa is written after the 0x_55, the time-out logic restarts and the user must wait until the next window before writing to armcop. table 7-10 shows the duration of this window for the seven available cop rates. 0 normal cop operation 1 window cop operation 6 rsbck cop and rti stop in active bdm mode bit 0 allows the cop and rti to keep running in active bdm mode. 1 stops the cop and rti counters whenever the part is in active bdm mode. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 361 5 wrtmask write mask for wcop and cr[2:0] bit this write-only bit serves as a mask for the wcop and cr[2:0] bits while writing the copctl register. it is intended for bdm writing the rsbck without touching the contents of wcop and cr[2:0]. 0 write of wcop and cr[2:0] has an effect with this write of copctl 1 write of wcop and cr[2:0] has no effect with this write of copctl. (does not count for ?rite once?) 2? cr[1:0] cop watchdog timer rate select ?these bits select the cop time-out rate (see table 7-10 ). the cop time-out period is oscclk period divided by cr[2:0] value. writing a nonzero value to cr[2:0] enables the cop counter and starts the time-out period. a cop counter time-out causes a system reset. this can be avoided by periodically (before time-out) reinitializing the cop counter via the armcop register. while all of the following three conditions are true the cr[2:0], wcop bits are ignored and the cop operates at highest time-out period ( 2 24 cycles) in normal cop mode (window cop mode disabled): 1) cop is enabled (cr[2:0] is not 000) 2) bdm mode active 3) rsbck = 0 4) operation in emulation or special modes table 7-10. cop watchdog rates 1 1 oscclk cycles are referenced from the previous cop time-out reset (writing 0x_55/0x_aa to the armcop register) cr2 cr1 cr0 oscclk cycles to time-out 0 0 0 cop disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23 111 2 24 table 7-9. copctl field descriptions (continued) field description 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 362 freescale semiconductor 7.3.2.10 reserved register (forbyp) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special modes can alter the crgs functionality. read: always read 0x_00 except in special modes write: only in special modes 7.3.2.11 reserved register (ctctl) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special test modes can alter the crgs functionality. read: always read 0x_80 except in special modes write: only in special modes 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 7-13. reserved register (forbyp) 76543210 r10000000 w reset 0 0 0 00000 = unimplemented or reserved figure 7-14. reserved register (ctctl) 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 363 7.3.2.12 crg cop timer arm/reset register (armcop) this register is used to restart the cop time-out period. read: always reads 0x_00 write: anytime when the cop is disabled (cr[2:0] = ?00? writing to this register has no effect. when the cop is enabled by setting cr[2:0] nonzero, the following applies: writing any value other than 0x_55 or 0x_aa causes a cop reset. to restart the cop time-out period you must write 0x_55 followed by a write of 0x_aa. other instructions may be executed between these writes but the sequence (0x_55, 0x_aa) must be completed prior to cop end of time-out period to avoid a cop reset. sequences of 0x_55 writes or sequences of 0x_aa writes are allowed. when the wcop bit is set, 0x_55 and 0x_aa writes must be done in the last 25% of the selected time-out period; writing any value in the ?st 75% of the selected period will cause a cop reset. 76543210 r00000000 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0 0 0 00000 figure 7-15. armcop register diagram 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 364 freescale semiconductor 7.4 functional description 7.4.1 functional blocks 7.4.1.1 phase locked loop (pll) the pll is used to run the mcu from a different time base than the incoming oscclk. for increased ?xibility, oscclk can be divided in a range of 1 to 16 to generate the reference frequency. this offers a ?er multiplication granularity. the pll can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the synr register. caution although it is possible to set the two dividers to command a very high clock frequency, do not exceed the speci?d bus frequency limit for the mcu. if (pllsel = 1), bus clock = pllclk / 2 the pll is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. the pll can change between acquisition and tracking modes either automatically or manually. the vco has a minimum operating frequency, which corresponds to the self clock mode frequency f scm . figure 7-16. pll functional diagram pllclk 2 oscclk synr 1 + [] refdv 1 + [] ----------------------------------- - = reduced consumption oscillator extal xtal oscclk pllclk reference programmable divider pdet phase detector refdv <5:0> loop programmable divider syn <5:0> cpump vco lock loop filter xfc pin up down lock detector reference feedback v ddpll v ddpll /v sspll crystal monitor v ddpll /v sspll v dd /v ss supplied by: 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 365 7.4.1.1.1 pll operation the oscillator output clock signal (oscclk) is fed through the reference programmable divider and is divided in a range of 1 to 64 (refdv + 1) to output the reference clock. the vco output clock, (pllclk) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (synr + 1)] to output the feedback clock. figure 7-16 . the phase detector then compares the feedback clock, with the reference clock. correction pulses are generated based on the phase difference between the two signals. the loop ?ter then slightly alters the dc voltage on the external ?ter capacitor connected to xfc pin, based on the width and direction of the correction pulse. the ?ter can make fast or slow corrections depending on its mode, as described in the next subsection. the values of the external ?ter network and the reference frequency determine the speed of the corrections and the stability of the pll. the minimum vco frequency is reached with the xfc pin forced to v ddpll . this is the self clock mode frequency. 7.4.1.1.2 acquisition and tracking modes the lock detector compares the frequencies of the feedback clock, and the reference clock. therefore, the speed of the lock detector is directly proportional to the ?al reference frequency. the circuit determines the mode of the pll and the lock condition based on this comparison. the pll ?ter can be manually or automatically con?ured into one of two possible operating modes: acquisition mode in acquisition mode, the ?ter can make large frequency corrections to the vco. this mode is used at pll start-up or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the track status bit is cleared in the crgflg register. tracking mode in tracking mode, the ?ter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct and the track bit is set in the crgflg register. the pll can change the bandwidth or operational mode of the loop ?ter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode also is used to determine when the pll clock (pllclk) is safe to use as the source for the system and core clocks. if pll lock interrupt requests are enabled, the software can wait for an interrupt request and then check the lock bit. if interrupt requests are disabled, software can poll the lock bit continuously (during pll start-up, usually) or at periodic intervals. in either case, only when the lock bit is set, is the pllclk clock safe to use as the source for the system and core clocks. if the pll is selected as the source for the system and core clocks and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 366 freescale semiconductor the following conditions apply when the pll is in automatic bandwidth control mode (auto = 1): the track bit is a read-only indicator of the mode of the ?ter. the track bit is set when the vco frequency is within a certain tolerance, ? trk , and is clear when the vco frequency is out of a certain tolerance, ? unt . the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . interrupt requests can occur if enabled (lockie = 1) when the lock condition changes, toggling the lock bit. the pll can also operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below the maximum system frequency (f sys ) and require fast start-up. the following conditions apply when in manual mode: acq is a writable control bit that controls the mode of the ?ter. before turning on the pll in manual mode, the acq bit should be asserted to con?ure the ?ter in acquisition mode. after turning on the pll by setting the pllon bit software must wait a given time (t acq ) before entering tracking mode (acq = 0). after entering tracking mode software must wait a given time (t al ) before selecting the pllclk as the source for system and core clocks (pllsel = 1). 7.4.1.2 system clocks generator figure 7-17. system clocks generator oscillator phase lock loop extal xtal sysclk rti oscclk pllclk clock phase generator bus clock clock monitor 1 0 pllsel or scm 2 core clock cop oscillator = clock gate gating condition wait(rtiwai), stop( pstp, pre), rti enable wait(copwai), stop( pstp, pce), cop enable stop 1 0 scm clock stop 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 367 the clock generator creates the clocks used in the mcu (see figure 7-17 ). the gating condition placed on top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting of the respective con?uration bits. the peripheral modules use the bus clock. some peripheral modules also use the oscillator clock. the memory blocks use the bus clock. if the mcu enters self clock mode (see section 7.4.2.2, ?elf clock mode ) oscillator clock source is switched to pllclk running at its minimum frequency f scm . the bus clock is used to generate the clock visible at the eclk pin. the core clock signal is the clock for the cpu. the core clock is twice the bus clock as shown in figure 7-18 . but note that a cpu cycle corresponds to one bus clock. pll clock mode is selected with pllsel bit in the clksel registerr. when selected, the pll output clock drives sysclk for the main system including the cpu and peripherals. the pll cannot be turned off by clearing the pllon bit, if the pll clock is selected. when pllsel is changed, it takes a maximum of 4 oscclk plus 4 pllclk cycles to make the transition. during the transition, all clocks freeze and cpu activity ceases. figure 7-18. core clock and bus clock relationship 7.4.1.3 clock monitor (cm) if no oscclk edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. the crg then asserts self clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.the clock monitor function is enabled/disabled by the cme control bit. 7.4.1.4 clock quality checker the clock monitor performs a coarse check on the incoming clock signal. the clock quality checker provides a more accurate check in addition to the clock monitor. a clock quality check is triggered by any of the following events: power on reset ( por ) low voltage reset ( lvr ) wake-up from full stop mode ( exit full stop ) clock monitor fail indication ( cm fail ) a time window of 50,000 vco clock cycles 1 is called check window . 1. vco clock cycles are generated by the pll when running at minimum frequency f scm . core clock bus clock / eclk 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 368 freescale semiconductor a number greater equal than 4096 rising oscclk edges within a check window is called osc ok . note that osc ok immediately terminates the current check window . see figure 7-19 as an example. figure 7-19. check window example the sequence for clock quality check is shown in figure 7-20 . figure 7-20. sequence for clock quality check 12 49999 50000 vco clock check window 12345 4095 4096 3 oscclk osc ok check window osc ok ? scm active? switch to oscclk exit scm clock ok num = 50 num > 0 ? num=num? yes no yes scme=1 ? no enter scm scm active? yes clock monitor reset no yes no num = 0 yes no por exit full stop cm fail lvr yes no ? fstwkp = 0 no num = 0 enter scm yes scme = 1 & fstwkp = 1 ? 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 369 note remember that in parallel to additional actions caused by self clock mode or clock monitor reset 1 handling the clock quality checker continues to check the oscclk signal. the clock quality checker enables the pll and the voltage regulator (vreg) anytime a clock check has to be performed. an ongoing clock quality check could also cause a running pll (f scm ) and an active vreg during pseudo stop mode or wait mode. 7.4.1.5 computer operating properly watchdog (cop) the cop (free running watchdog timer) enables the user to check that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping the cop from timing out. if the cop times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see section 7.4.1.5, ?omputer operating properly watchdog (cop) ). the cop runs with a gated oscclk. three control bits in the copctl register allow selection of seven cop time-out periods. when cop is enabled, the program must write 0x_55 and 0x_aa (in this order) to the armcop register during the selected time-out period. once this is done, the cop time-out period is restarted. if the program fails to do this and the cop times out, the part will reset. also, if any value other than 0x_55 or 0x_aa is written, the part is immediately reset. windowed cop operation is enabled by setting wcop in the copctl register. in this mode, writes to the armcop register to clear the cop timer must occur in the last 25% of the selected time-out period. a premature write will immediately reset the part. if pce bit is set, the cop will continue to run in pseudo stop mode. 7.4.1.6 real time interrupt (rti) the rti can be used to generate a hardware interrupt at a ?ed periodic rate. if enabled (by setting rtie = 1), this interrupt will occur at the rate selected by the rtictl register. the rti runs with a gated oscclk. at the end of the rti time-out period the rtif ?g is set to 1 and a new rti time-out period starts immediately. a write to the rtictl register restarts the rti time-out period. if the pre bit is set, the rti will continue to run in pseudo stop mode. 7.4.2 operating modes 7.4.2.1 normal mode the crg block behaves as described within this speci?ation in all normal modes. 1. a clock monitor reset will always set the scme bit to logical 1. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 370 freescale semiconductor 7.4.2.2 self clock mode the vco has a minimum operating frequency, f scm . if the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the vco running at minimum operating frequency; this mode of operation is called self clock mode. this requires cme = 1 and scme = 1. if the mcu was clocked by the pll clock prior to entering self clock mode, the pllsel bit will be cleared. if the external clock signal has stabilized again, the crg will automatically select oscclk to be the system clock and return to normal mode. section 7.4.1.4, ?lock quality checker for more information on entering and leaving self clock mode. note in order to detect a potential clock loss the cme bit should be always enabled (cme = 1)! if cme bit is disabled and the mcu is con?ured to run on pll clock (pllclk), a loss of external clock (oscclk) will not be detected and will cause the system clock to drift towards the vcos minimum frequency f scm . as soon as the external clock is available again the system clock ramps up to its pll target frequency. if the mcu is running on external clock any loss of clock will cause the system to go static. 7.4.3 low power options this section summarizes the low power options available in the crg. 7.4.3.1 run mode the rti can be stopped by setting the associated rate select bits to 0. the cop can be stopped by setting the associated rate select bits to 0. 7.4.3.2 wait mode the wai instruction puts the mcu in a low power consumption stand-by mode depending on setting of the individual bits in the clksel register. all individual wait mode con?uration bits can be superposed. this provides enhanced granularity in reducing the level of power consumption during wait mode. table 7-11 lists the individual con?uration bits and the parts of the mcu that are affected in wait mode . after executing the wai instruction the core requests the crg to switch mcu into wait mode. the crg then checks whether the pllwai bit is asserted ( figure 7-21 ). depending on the con?uration, the crg switches the system and core clocks to oscclk by clearing the pllsel bit and disables the pll. as soon as all clocks are switched off wait mode is active. table 7-11. mcu con?uration during wait mode pllwai rtiwai copwai pll stopped rti stopped cop stopped 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 371 figure 7-21. wait mode entry/exit sequence enter wait mode pllwai=1 ? exit wait w. cmreset exit wait w. ext.reset exit wait mode enter scm exit wait mode cpu reqs wait mode. clear pllsel, disable pll cme=1 ? int ? cm fail ? scme=1 ? scmie=1 ? continue w. normal op no no no no no yes yes yes yes yes no yes wait mode left due to external reset generate scm interrupt (wakeup from wait) scm=1 ? enter scm no yes 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 372 freescale semiconductor there are four different scenarios for the crg to restart the mcu from wait mode: external reset clock monitor reset cop reset any interrupt if the mcu gets an external reset or cop reset during wait mode active, the crg asynchronously restores all con?uration bits in the register space to its default settings and starts the reset generator. after completing the reset sequence processing begins by fetching the normal or cop reset vector. wait mode is left and the mcu is in run mode again. if the clock monitor is enabled (cme = 1) the mcu is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. if the scme bit is not asserted the crg generates a clock monitor fail reset (cmreset). the crgs behavior for cmreset is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. if the scme bit is asserted the crg generates a scm interrupt if enabled (scmie = 1). after generating the interrupt the crg enters self-clock mode and starts the clock quality checker ( section 7.4.1.4, ?lock quality checker ). then the mcu continues with normal operation.if the scm interrupt is blocked by scmie = 0, the scmif ?g will be asserted and clock quality checks will be performed but the mcu will not wake-up from wait-mode. if any other interrupt source (e.g., rti) triggers exit from wait mode, the mcu immediately continues with normal operation. if the pll has been powered-down during wait mode, the pllsel bit is cleared and the mcu runs on oscclk after leaving wait mode. the software must manually set the pllsel bit again, in order to switch system and core clocks to the pllclk. if wait mode is entered from self-clock mode the crg will continue to check the clock quality until clock check is successful. the pll and voltage regulator (vreg) will remain enabled. table 7-12 summarizes the outcome of a clock loss while in wait mode. 7.4.3.3 system stop mode all clocks are stopped in stop mode, dependent of the setting of the pce, pre, and pstp bit. the oscillator is disabled in stop mode unless the pstp bit is set. all counters and dividers remain frozen but do not initialize. if the pre or pce bits are set, the rti or cop continues to run in pseudo stop mode. in addition to disabling system and core clocks the crg requests other functional units of the mcu (e.g., voltage-regulator) to enter their individual power saving modes (if available). this is the main difference between pseudo stop mode and wait mode. if the pllsel bit is still set when entering stop mode, the crg will switch the system and core clocks to oscclk by clearing the pllsel bit. then the crg disables the pll, disables the core clock and ?ally disables the remaining system clocks. as soon as all clocks are switched off, stop mode is active. if pseudo stop mode (pstp = 1) is entered from self-clock mode, the crg will continue to check the clock quality until clock check is successful. the pll and the voltage regulator (vreg) will remain enabled. if full stop mode (pstp = 0) is entered from self-clock mode, an ongoing clock quality check will be stopped. a complete timeout window check will be started when stop mode is left again. wake-up from stop mode also depends on the setting of the pstp bit. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 373 table 7-12. outcome of clock loss in wait mode cme scme scmie crg actions 0x x clock failure --> no action, clock loss not detected. 10 x clock failure --> crg performs clock monitor reset immediately 11 0 clock failure --> scenario 1: oscclk recovers prior to exiting wait mode. ?mcu remains in wait mode, ?vreg enabled, ?pll enabled, ?scm activated, ?start clock quality check, ?set scmif interrupt ?g. some time later oscclk recovers. ?cm no longer indicates a failure, ?4096 oscclk cycles later clock quality check indicates clock o.k., ?scm deactivated, ?pll disabled depending on pllwai, ?vreg remains enabled (never gets disabled in wait mode) . ?mcu remains in wait mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ?exit wait mode using oscclk as system clock (sysclk), ?continue normal operation. or an external reset is applied. ?exit wait mode using oscclk as system clock, ?start reset sequence. scenario 2: oscclk does not recover prior to exiting wait mode. ?mcu remains in wait mode, ?vreg enabled, ?pll enabled, ?scm activated, ?start clock quality check, ?set scmif interrupt ?g, keep performing clock quality checks (could continue in?itely) while in wait mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ?exit wait mode in scm using pll clock (f scm ) as system clock, ?continue to perform additional clock quality checks until oscclk is o.k. again. or an external reset is applied. ?exit wait mode in scm using pll clock (f scm ) as system clock, ?start reset sequence, ?continue to perform additional clock quality checks until oscclkis o.k.again. 11 1 clock failure --> ?vreg enabled, ?pll enabled, ?scm activated, ?start clock quality check, ?scmif set. scmif generates self clock mode wakeup interrupt. ?exit wait mode in scm using pll clock (f scm ) as system clock, ?continue to perform a additional clock quality checks until oscclk is o.k. again. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 374 freescale semiconductor figure 7-22. stop mode entry/exit sequence exit stop w. cmreset exit stop mode enter scm exit stop mode core req? stop mode. clear pllsel, disable pll cme=1 ? int ? cm fail ? scme=1 ? scmie=1 ? continue w. normal op no no no no yes yes yes yes yes generate scm interrupt (wakeup from stop) enter stop mode exit stop w. ext.reset stop mode left due to external reset clock ok ? scme=1 ? enter scm yes no yes exit stop w. cmreset no no no pstp=1 ? int ? yes no yes exit stop mode exit stop mode scm=1 ? enter scm no yes yes no scme=1 & fstwkp=1 ? exit stop mode enter scm scmif not set! 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 375 7.4.3.3.1 wake-up from pseudo stop mode (pstp=1) wake-up from pseudo stop mode is the same as wake-up from wait mode. there are also four different scenarios for the crg to restart the mcu from pseudo stop mode: external reset clock monitor fail cop reset wake-up interrupt if the mcu gets an external reset or cop reset during pseudo stop mode active, the crg asynchronously restores all con?uration bits in the register space to its default settings and starts the reset generator. after completing the reset sequence processing begins by fetching the normal or cop reset vector. pseudo stop mode is left and the mcu is in run mode again. if the clock monitor is enabled (cme = 1), the mcu is able to leave pseudo stop mode when loss of oscillator/external clock is detected by a clock monitor fail. if the scme bit is not asserted the crg generates a clock monitor fail reset (cmreset). the crgs behavior for cmreset is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. if the scme bit is asserted the crg generates a scm interrupt if enabled (scmie = 1). after generating the interrupt the crg enters self-clock mode and starts the clock quality checker ( section 7.4.1.4, ?lock quality checker ). then the mcu continues with normal operation. if the scm interrupt is blocked by scmie=0, the scmif ?g will be asserted but the crg will not wake-up from pseudo stop mode. if any other interrupt source (e.g., rti) triggers exit from pseudo stop mode, the mcu immediately continues with normal operation. because the pll has been powered-down during stop mode, the pllsel bit is cleared and the mcu runs on oscclk after leaving stop mode. the software must set the pllsel bit again, in order to switch system and core clocks to the pllclk. table 7-13 summarizes the outcome of a clock loss while in pseudo stop mode. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 376 freescale semiconductor table 7-13. outcome of clock loss in pseudo stop mode cme scme scmie crg actions 0xx clock failure --> no action, clock loss not detected. 10x clock failure --> crg performs clock monitor reset immediately 110 clock monitor failure --> scenario 1: oscclk recovers prior to exiting pseudo stop mode. ?mcu remains in pseudo stop mode, ?vreg enabled, ?pll enabled, ?scm activated, ?start clock quality check, ?set scmif interrupt ?g. some time later oscclk recovers. ?cm no longer indicates a failure, ?4096 oscclk cycles later clock quality check indicates clock o.k., ?scm deactivated, ?pll disabled, ?vreg disabled. ?mcu remains in pseudo stop mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ?exit pseudo stop mode using oscclk as system clock (sysclk), ?continue normal operation. or an external reset is applied. ?exit pseudo stop mode using oscclk as system clock, ?start reset sequence. scenario 2: oscclk does not recover prior to exiting pseudo stop mode. ?mcu remains in pseudo stop mode, ?vreg enabled, ?pll enabled, ?scm activated, ?start clock quality check, ?set scmif interrupt ?g, ?keep performing clock quality checks (could continue in?itely) while in pseudo stop mode. s ome time later either a wakeup interrupt occurs (no scm interrupt) ?exit pseudo stop mode in scm using pll clock (f scm ) as system clock ?continue to perform additional clock quality checks until oscclk is o.k. again. or an external reset is applied. ?exit pseudo stop mode in scm using pll clock (f scm ) as system clock ?start reset sequence, ?continue to perform additional clock quality checks until oscclk is o.k.again. 111 clock failure --> ?vreg enabled, ?pll enabled, ?scm activated, ?start clock quality check, ?scmif set. scmif generates self clock mode wakeup interrupt. ?exit pseudo stop mode in scm using pll clock (f scm ) as system clock, ?continue to perform a additional clock quality checks until oscclk is o.k. again. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 377 7.4.3.3.2 wake-up from full stop (pstp = 0) the mcu requires an external interrupt or an external reset in order to wake-up from stop-mode. if the mcu gets an external reset during full stop mode active, the crg asynchronously restores all con?uration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see section 7.4.1.4, ?lock quality checker ). after completing the clock quality check the crg starts the reset generator. after completing the reset sequence processing begins by fetching the normal reset vector. full stop-mode is left and the mcu is in run mode again. if the mcu is woken-up by an interrupt and the fast wake-up feature is disabled (fstwkp = 0 or scme = 0), the crg will also perform a maximum of 50 clock check_window s (see section 7.4.1.4, ?lock quality checker ). if the clock quality check is successful, the crg will release all system and core clocks and will continue with normal operation. if all clock checks within the timeout-window are failing, the crg will switch to self-clock mode or generate a clock monitor reset (cmreset) depending on the setting of the scme bit. if the mcu is woken-up by an interrupt and the fast wake-up feature is enabled (fstwkp = 1 and scme = 1), the system will immediately resume operation in self-clock mode (see section 7.4.1.4, ?lock quality checker ). the scmif ?g will not be set. the system will remain in self-clock mode with oscillator disabled until fstwkp bit is cleared. the clearing of fstwkp will start the oscillator and the clock quality check. if the clock quality check is successful, the crg will switch all system clocks to oscillator clock. the scmif ?g will be set. see application examples in figure 7-23 and figure 7-24 . because the pll has been powered-down during stop-mode the pllsel bit is cleared and the mcu runs on oscclk after leaving stop-mode. the software must manually set the pllsel bit again, in order to switch system and core clocks to the pllclk. note in full stop mode or self-clock mode caused by the fast wake-up feature, the clock monitor and the oscillator are disabled. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 378 freescale semiconductor figure 7-23. fast wake-up from full stop mode: example 1 . figure 7-24. fast wake-up from full stop mode: example 2 oscillator clock pll clock core clock instruction stop irq service fstwkp=1 interrupt irq service interrupt interrupt stop stop irq service oscillator disabled power saving self-clock mode scme=1 cpu resumes program execution immediately oscillator clock pll clock core clock instruction clock quality check stop irq service fstwkp=1 irq interrupt fstwkp=0 scmie=1 freq. uncritical instructions freq. critical instr. possible osc startup oscillator disabled cpu resumes program execution immediately scm interrupt self-clock mode scme=1 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 379 7.5 resets this section describes how to reset the crg, and how the crg itself controls the reset of the mcu. it explains all special reset requirements. since the reset generator for the mcu is part of the crg, this section also describes all automatic actions that occur during or as a result of individual reset conditions. the reset values of registers and signals are provided in section 7.3, ?emory map and register de?ition . all reset sources are listed in table 7-14 . refer to mcu speci?ation for related vector addresses and priorities. 7.5.1 description of reset operation the reset sequence is initiated by any of the following events: low level is detected at the reset pin (external reset) power on is detected low voltage is detected illegal address reset is detected (see s12xmmc block guide for details) cop watchdog times out clock monitor failure is detected and self-clock mode was disabled (scme=0) upon detection of any reset event, an internal circuit drives the reset pin low for 128 sysclk cycles (see figure 7-25 ). since entry into reset is asynchronous, it does not require a running sysclk. however, the internal reset circuit of the crg cannot sequence out of current reset condition without a running sysclk. the number of 128 sysclk cycles might be increased by n = 3 to 6 additional sysclk cycles depending on the internal synchronization latency. after 128 + n sysclk cycles the reset pin is released. the reset generator of the crg waits for additional 64 sysclk cycles and then samples the reset pin to determine the originating source. table 7-15 shows which vector will be fetched. table 7-14. reset summary reset source local enable power on reset none low voltage reset none external reset none illegal address reset none clock monitor reset pllctl (cme = 1, scme = 0) cop watchdog reset copctl (cr[2:0] nonzero) 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 380 freescale semiconductor note external circuitry connected to the reset pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 sysclk cycles after the low drive is released. the internal reset of the mcu remains asserted while the reset generator completes the 192 sysclk long reset sequence. the reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 sysclk cycles. in case the reset pin is externally driven low for more than these 192 sysclk cycles (external reset), the internal reset remains asserted too. figure 7-25. reset timing table 7-15. reset vector selection sampled reset pin (64 cycles after release) clock monitor reset pending cop reset pending vector fetch 1 0 0 por / lvr / illegal address reset / external reset 1 1 x clock monitor reset 1 0 1 cop reset 0 x x por / lvr / illegal address reset / external reset with rise of reset pin ) ( ) ( ) ( ) sysclk 128 + n cycles 64 cycles with n being min 3 / max 6 cycles depending on internal synchronization delay crg drives reset pin low possibly sysclk not running possibly reset driven low externally ) ( ( reset reset pin released 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 381 7.5.2 clock monitor reset the crg generates a clock monitor reset in case all of the following conditions are true: clock monitor is enabled (cme = 1) loss of clock is detected self-clock mode is disabled (scme = 0). the reset event asynchronously forces the con?uration registers to their default settings (see section 7.3, ?emory map and register de?ition ). in detail the cme and the scme are reset to logical ? (which doesnt change the state of the cme bit, because it has already been set). as a consequence the crg immediately enters self clock mode and starts its internal reset sequence. in parallel the clock quality check starts. as soon as clock quality check indicates a valid oscillator clock the crg switches to oscclk and leaves self clock mode. since the clock quality checker is running in parallel to the reset generator, the crg may leave self clock mode while still completing the internal reset sequence. when the reset sequence is ?ished, the crg checks the internally latched state of the clock monitor fail circuit. if a clock monitor fail is indicated, processing begins by fetching the clock monitor reset vector. 7.5.3 computer operating properly watchdog (cop) reset when cop is enabled, the crg expects sequential write of 0x_55 and 0x_aa (in this order) to the armcop register during the selected time-out period. once this is done, the cop time-out period restarts. if the program fails to do this the crg will generate a reset. also, if any value other than 0x_55 or 0x_aa is written, the crg immediately generates a reset. in case windowed cop operation is enabled writes (0x_55 or 0x_aa) to the armcop register must occur in the last 25% of the selected time-out period. a premature write the crg will immediately generate a reset. as soon as the reset sequence is completed the reset generator checks the reset condition. if no clock monitor failure is indicated and the latched state of the cop timeout is true, processing begins by fetching the cop vector. 7.5.4 power on reset, low voltage reset the on-chip voltage regulator detects when v dd to the mcu has reached a certain level and asserts power on reset or low voltage reset or both. as soon as a power on reset or low voltage reset is triggered the crg performs a quality check on the incoming clock signal. as soon as clock quality check indicates a valid oscillator clock signal, the reset sequence starts using the oscillator clock. if after 50 check windows the clock quality check indicated a non-valid oscillator clock, the reset sequence starts using self-clock mode. figure 7-26 and figure 7-27 show the power-up sequence for cases when the reset pin is tied to v dd and when the reset pin is held low. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 382 freescale semiconductor figure 7-26. reset pin tied to v dd (by a pull-up resistor) figure 7-27. reset pin held low externally 7.6 interrupts the interrupts/reset vectors requested by the crg are listed in table 7-16 . refer to mcu speci?ation for related vector addresses and priorities. 7.6.1 real time interrupt the crg generates a real time interrupt when the selected interrupt time period elapses. rti interrupts are locally disabled by setting the rtie bit to 0. the real time interrupt ?g (rtif) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the rtif bit. the rti continues to run during pseudo stop mode if the pre bit is set to 1. this feature can be used for periodic wakeup from pseudo stop if the rti interrupt is enabled. table 7-16. crg interrupt vectors interrupt source ccr mask local enable real time interrupt i bit crgint (rtie) lock interrupt i bit crgint (lockie) scm interrupt i bit crgint (scmie) reset internal por 128 sysclk 64 sysclk internal reset clock quality check (no self-clock mode) ) ( ) ( ) ( clock quality check reset internal por internal reset 128 sysclk 64 sysclk (no self clock mode) ) ( ) ( ) ( 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 383 7.6.2 pll lock interrupt the crg generates a pll lock interrupt when the lock condition of the pll has changed, either from a locked state to an unlocked state or vice versa. lock interrupts are locally disabled by setting the lockie bit to 0. the pll lock interrupt ?g (lockif) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the lockif bit. 7.6.3 self clock mode interrupt the crg generates a self clock mode interrupt when the scm condition of the system has changed, either entered or exited self clock mode. scm conditions can only change if the self clock mode enable bit (scme) is set to 1. scm conditions are caused by a failing clock quality check after power on reset (por) or low voltage reset (lvr) or recovery from full stop mode (pstp = 0) or clock monitor failure. for details on the clock quality check refer to section 7.4.1.4, ?lock quality checker . if the clock monitor is enabled (cme = 1) a loss of external clock will also cause a scm condition (scme = 1). scm interrupts are locally disabled by setting the scmie bit to 0. the scm interrupt ?g (scmif) is set to1 when the scm condition has changed, and is cleared to 0 by writing a 1 to the scmif bit. 4 .com u datasheet
chapter 7 clocks and reset generator (crgv6) MC9S12XHZ512 data sheet, rev. 1.02 384 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 385 chapter 8 pierce oscillator (s12xosclcpv1) 8.1 introduction the pierce oscillator (xosc) module provides a robust, low-noise and low-power clock source. the module will be operated from the v ddpll supply rail (2.5 v nominal) and require the minimum number of external components. it is designed for optimal start-up margin with typical crystal oscillators. 8.1.1 features the xosc will contain circuitry to dynamically control current gain in the output amplitude. this ensures a signal with low harmonic distortion, low power and good noise immunity. high noise immunity due to input hysteresis low rf emissions with peak-to-peak swing limited dynamically transconductance (gm) sized for optimum start-up margin for typical oscillators dynamic gain control eliminates the need for external current limiting resistor integrated resistor eliminates the need for external bias resistor low power consumption: operates from 2.5 v (nominal) supply amplitude control limits power clock monitor 8.1.2 modes of operation two modes of operation exist: 1. loop controlled pierce oscillator 2. external square wave mode featuring also full swing pierce without internal feedback resistor 4 .com u datasheet
chapter 8 pierce oscillator (s12xosclcpv1) MC9S12XHZ512 data sheet, rev. 1.02 386 freescale semiconductor 8.1.3 block diagram figure 8-1 shows a block diagram of the xosc. figure 8-1. xosc block diagram 8.2 external signal description this section lists and describes the signals that connect off chip 8.2.1 v ddpll and v sspll ?operating and ground voltage pins theses pins provides operating voltage (v ddpll ) and ground (v sspll ) for the xosc circuitry. this allows the supply voltage to the xosc to be independently bypassed. 8.2.2 extal and xtal ?input and output pins these pins provide the interface for either a crystal or a cmos compatible clock to control the internal clock generator circuitry. extal is the external clock input or the input to the crystal oscillator ampli?r. xtal is the output of the crystal oscillator ampli?r. the mcu internal system clock is derived from the extal xtal gain control v ddpll = 2.5 v rf oscclk monitor_failure clock monitor peak detector 4 .com u datasheet
chapter 8 pierce oscillator (s12xosclcpv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 387 extal input frequency. in full stop mode (pstp = 0), the extal pin is pulled down by an internal resistor of typical 200 k ? . note freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. loop controlled circuit is not suited for overtone resonators and crystals. figure 8-2. loop controlled pierce oscillator connections (xclks = 0) note full swing pierce circuit is not suited for overtone resonators and crystals without a careful component selection. figure 8-3. full swing pierce oscillator connections (xclks = 1) figure 8-4. external clock connections (xclks = 1) mcu extal xtal v sspll crystal or ceramic resonator c2 c1 * r s can be zero (shorted) when use with higher frequency crystals. refer to manufacturer? data. mcu extal xtal rs* rb v sspll crystal or ceramic resonator c2 c1 mcu extal xtal not connected cmos compatible external oscillator (v ddpll level) 4 .com u datasheet
chapter 8 pierce oscillator (s12xosclcpv1) MC9S12XHZ512 data sheet, rev. 1.02 388 freescale semiconductor 8.2.3 xclks ?input signal the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used. refer to the device overview chapter for polarity and sampling conditions of the xclks pin. table 8-1 lists the state coding of the sampled xclks signal. . 8.3 memory map and register de?ition the crg contains the registers and associated bits for controlling and monitoring the oscillator module. 8.4 functional description the xosc module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. the oscillator block has two external pins, extal and xtal. the oscillator input pin, extal, is intended to be connected to either a crystal or an external clock source. the selection of loop controlled pierce oscillator or full swing pierce oscillator/external clock depends on the xclks signal which is sampled during reset. the xtal pin is an output signal that provides crystal circuit feedback. a buffered extal signal becomes the internal clock. to improve noise immunity, the oscillator is powered by the v ddpll and v sspll power supply pins. 8.4.1 gain control a closed loop control system will be utilized whereby the ampli?r is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude. the output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer. electrical speci?ation details are provided in the electrical characteristics appendix. 8.4.2 clock monitor the clock monitor circuit is based on an internal rc time delay so that it can operate without any mcu clocks. if no oscclk edges are detected within this rc time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated.the clock monitor function is enabled/disabled by the cme control bit, described in the crg block description chapter. table 8-1. clock selection based on xclks xclks description 0 loop controlled pierce oscillator selected 1 full swing pierce oscillator/external clock selected 4 .com u datasheet
chapter 8 pierce oscillator (s12xosclcpv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 389 8.4.3 wait mode operation during wait mode, xosc is not impacted. 8.4.4 stop mode operation xosc is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. during pseudo-stop mode, xosc is not impacted. 4 .com u datasheet
chapter 8 pierce oscillator (s12xosclcpv1) MC9S12XHZ512 data sheet, rev. 1.02 390 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 391 chapter 9 analog-to-digital converter (atd10b16cv4) 9.1 introduction the atd10b16c is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. refer to the electrical speci?ations chapter for atd accuracy. 9.1.1 features 8-/10-bit resolution ? s, 10-bit single conversion time sample buffer ampli?r programmable sample time left/right justi?d, signed/unsigned result data external trigger control conversion completion interrupt generation analog input multiplexer for 16 analog input channels analog/digital input pin multiplexing 1 to 16 conversion sequence lengths continuous conversion mode multiple channel scans con?urable external trigger functionality on any ad channel or any of four additional trigger inputs. the four additional trigger inputs can be chip external or internal. refer to device speci?ation for availability and connectivity con?urable location for channel wrap around (when converting multiple channels in a sequence) 9.1.2 modes of operation there is software programmable selection between performing single or continuous conversion on a single channel or multiple channels . 9.1.3 block diagram refer to figure 9-1 for a block diagram of the atd0b16c block. 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 392 freescale semiconductor figure 9-1. atd10b16c block diagram v ssa an8 atd10b16c analog mux mode and successive approximation register (sar) results atd 0 atd 1 atd 2 atd 3 atd 4 atd 5 atd 6 atd 7 and dac sample & hold 1 1 v dda v rl v rh sequence complete interrupt + - comparator clock prescaler bus clock atd clock atd 8 atd 9 atd 10 atd 11 atd 12 atd 13 atd 14 atd 15 an7 an6 an5 an4 an3 an2 an1 an0 an9 an10 an11 an12 an13 an14 an15 etrig0 (see device overview chapter for availability etrig1 etrig2 etrig3 and connectivity) timing control atddien atdctl1 portad trigger mux 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 393 9.2 external signal description this section lists all inputs to the atd10b16c block. 9.2.1 an x ( x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) analog input channel x pins this pin serves as the analog input channel x . it can also be con?ured as general-purpose digital input and/or external trigger for the atd conversion. 9.2.2 etrig3, etrig2, etrig1, etrig0 ?external trigger pins these inputs can be con?ured to serve as an external trigger for the atd conversion. refer to the device overview chapter for availability and connectivity of these inputs. 9.2.3 v rh ,v rl high reference voltage pin, low reference voltage pin v rh is the high reference voltage, v rl is the low reference voltage for atd conversion. 9.2.4 v dda , v ssa ?analog circuitry power supply pins these pins are the power supplies for the analog circuitry of the atd10b16cv4 block. 9.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the atd10b16c. 9.3.1 module memory map table 9-1 gives an overview of all atd10b16c registers 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 394 freescale semiconductor . note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. table 9-1. atd10b16cv4 memory map address offset use access 0x0000 atd control register 0 (atdctl0) r/w 0x0001 atd control register 1 (atdctl1) r/w 0x0002 atd control register 2 (atdctl2) r/w 0x0003 atd control register 3 (atdctl3) r/w 0x0004 atd control register 4 (atdctl4) r/w 0x0005 atd control register 5 (atdctl5) r/w 0x0006 atd status register 0 (atdstat0) r/w 0x0007 unimplemented 0x0008 atd test register 0 (atdtest0) 1 1 atdtest0 is intended for factory test purposes only. r 0x0009 atd test register 1 (atdtest1) r/w 0x000a atd status register 2 (atdstat2) r 0x000b atd status register 1 (atdstat1) r 0x000c atd input enable register 0 (atddien0) r/w 0x000d atd input enable register 1 (atddien1) r/w 0x000e port data register 0 (portad0) r 0x000f port data register 1 (portad1) r 0x0010, 0x0011 atd result register 0 (atddr0h, atddr0l) r/w 0x0012, 0x0013 atd result register 1 (atddr1h, atddr1l) r/w 0x0014, 0x0015 atd result register 2 (atddr2h, atddr2l) r/w 0x0016, 0x0017 atd result register 3 (atddr3h, atddr3l) r/w 0x0018, 0x0019 atd result register 4 (atddr4h, atddr4l) r/w 0x001a, 0x001b atd result register 5 (atddr5h, atddr5l) r/w 0x001c, 0x001d atd result register 6 (atddr6h, atddr6l) r/w 0x001e, 0x001f atd result register 7 (atddr7h, atddr7l) r/w 0x0020, 0x0021 atd result register 8 (atddr8h, atddr8l) r/w 0x0022, 0x0023 atd result register 9 (atddr9h, atddr9l) r/w 0x0024, 0x0025 atd result register 10 (atddr10h, atddr10l) r/w 0x0026, 0x0027 atd result register 11 (atddr11h, atddr11l) r/w 0x0028, 0x0029 atd result register 12 (atddr12h, atddr12l) r/w 0x002a, 0x002b atd result register 13 (atddr13h, atddr13l) r/w 0x002c, 0x002d atd result register 14 (atddr14h, atddr14l) r/w 0x002e, 0x002f atd result register 15 (atddr15h, atddr15l) r/w 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 395 9.3.2 register descriptions this section describes in address order all the atd10b16c registers and their individual bits. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 atdctl0 r0000 wrap3 wrap2 wrap1 wrap0 w 0x0001 atdctl1 r etrigsel 000 etrigch3 etrigch2 etrigch1 etrigch0 w 0x0002 atdctl2 r adpu affc awai etrigle etrigp etrige ascie ascif w 0x0003 atdctl3 r0 s8c s4c s2c s1c fifo frz1 frz0 w 0x0004 atdctl4 r sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w 0x0005 atdctl5 r djm dsgn scan mult cd cc cb ca w 0x0006 atdstat0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x0007 unimplemented r w 0x0008 atdtest0 r unimplemented w 0x0009 atdtest1 r unimplemented sc w 0x000a atdstat2 r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w 0x000b atdstat1 r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w 0x000c atddien0 r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w = unimplemented or reserved u = unaffected figure 9-2. atd register summary 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 396 freescale semiconductor 9.3.2.1 atd control register 0 (atdctl0) writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 0x000d atddien1 r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w 0x000e portad0 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w 0x000f portad1 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w r bit 9 msb bit 7 msb bit 8 bit 6 bit 7 bit 5 bit 6 bit 4 bit 5 bit 3 bit 4 bit 2 bit 3 bit 1 bit 2 bit 0 0x0010?x002f atddrxh atddrxl w r bit 1 u bit 0 u 0 0 0 0 0 0 0 0 0 0 0 0 w 76543210 r0000 wrap3 wrap2 wrap1 wrap0 w reset 0 0 0 01111 = unimplemented or reserved figure 9-3. atd control register 0 (atdctl0) table 9-2. atdctl0 field descriptions field description 3:0 wrap[3:0] wrap around channel select bits ?these bits determine the channel for wrap around when doing multi-channel conversions. the coding is summarized in table 9-3 . register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved u = unaffected figure 9-2. atd register summary (continued) 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 397 9.3.2.2 atd control register 1 (atdctl1) writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime table 9-3. multi-channel wrap around coding wrap3 wrap2 wrap1 wrap0 multiple channel conversions (mult = 1) wrap around to an0 after converting 0 0 0 0 reserved 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1 0 1 0 an10 1 0 1 1 an11 1 1 0 0 an12 1 1 0 1 an13 1 1 1 0 an14 1 1 1 1 an15 76543210 r etrigsel 000 etrigch3 etrigch2 etrigch1 etrigch0 w reset 0 0 0 01111 = unimplemented or reserved figure 9-4. atd control register 1 (atdctl1) table 9-4. atdctl1 field descriptions field description 7 etrigsel external trigger source select ?this bit selects the external trigger source to be either one of the ad channels or one of the etrig[3:0] inputs. see device speci?ation for availability and connectivity of etrig[3:0] inputs. if etrig[3:0] input option is not available, writing a 1 to etrisel only sets the bit but has no effect, that means one of the ad channels (selected by etrigch[3:0]) remains the source for external trigger. the coding is summarized in table 9-5 . 3:0 etrigch[3:0] external trigger channel select these bits select one of the ad channels or one of the etrig[3:0] inputs as source for the external trigger. the coding is summarized in table 9-5 . 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 398 freescale semiconductor 9.3.2.3 atd control register 2 (atdctl2) this register controls power down, interrupt and external trigger. writes to this register will abort current conversion sequence but will not start a new sequence. table 9-5. external trigger channel select coding etrigsel etrigch3 etrigch2 etrigch1 etrigch0 external trigger source 0 0 0 0 0 an0 0 0 0 0 1 an1 0 0 0 1 0 an2 0 0 0 1 1 an3 0 0 1 0 0 an4 0 0 1 0 1 an5 0 0 1 1 0 an6 0 0 1 1 1 an7 0 1 0 0 0 an8 0 1 0 0 1 an9 0 1 0 1 0 an10 0 1 0 1 1 an11 0 1 1 0 0 an12 0 1 1 0 1 an13 0 1 1 1 0 an14 0 1 1 1 1 an15 1 0 0 0 0 etrig0 1 1 only if etrig[3:0] input option is available (see device speci?ation), else etrisel is ignored, that means external trigger source remains on one of the ad channels selected by etrigch[3:0] 1 0 0 0 1 etrig1 1 1 0 0 1 0 etrig2 1 1 0 0 1 1 etrig3 1 1 0 1 x x reserved 1 1 x x x reserved 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 399 read: anytime write: anytime 76543210 r adpu affc awai etrigle etrigp etrige ascie ascif w reset 0 0 0 00000 = unimplemented or reserved figure 9-5. atd control register 2 (atdctl2) table 9-6. atdctl2 field descriptions field description 7 adpu atd power down this bit provides on/off control over the atd10b16c block allowing reduced mcu power consumption. because analog electronic is turned off when powered down, the atd requires a recovery time period after adpu bit is enabled. 0 power down atd 1 normal atd functionality 6 affc atd fast flag clear all 0 atd ?g clearing operates normally (read the status register atdstat1 before reading the result register to clear the associate ccf ?g). 1 changes all atd conversion complete ?gs to a fast clear sequence. any access to a result register will cause the associate ccf ?g to clear automatically. 5 awai atd power down in wait mode ?when entering wait mode this bit provides on/off control over the atd10b16c block allowing reduced mcu power. because analog electronic is turned off when powered down, the atd requires a recovery time period after exit from wait mode. 0 atd continues to run in wait mode 1 halt conversion and power down atd during wait mode after exiting wait mode with an interrupt conversion will resume. but due to the recovery time the result of this conversion should be ignored. 4 etrigle external trigger level/edge control ?this bit controls the sensitivity of the external trigger signal. see table 9-7 for details. 3 etrigp external trigger polarity ?this bit controls the polarity of the external trigger signal. see table 9-7 for details. 2 etrige external trigger mode enable ?this bit enables the external trigger on one of the ad channels or one of the etrig[3:0] inputs as described in table 9-5 . if external trigger source is one of the ad channels, the digital input buffer of this channel is enabled. the external trigger allows to synchronize the start of conversion with external events. 0 disable external trigger 1 enable external trigger 1 ascie atd sequence complete interrupt enable 0 atd sequence complete interrupt requests are disabled. 1 atd interrupt will be requested whenever ascif = 1 is set. 0 ascif atd sequence complete interrupt flag ?if ascie = 1 the ascif ?g equals the scf ?g (see section 9.3.2.7, ?td status register 0 (atdstat0) ), else ascif reads zero. writes have no effect. 0 no atd interrupt occurred 1 atd sequence complete interrupt pending 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 400 freescale semiconductor table 9-7. external trigger con?urations etrigle etrigp external trigger sensitivity 0 0 falling edge 0 1 ring edge 1 0 low level 1 1 high level 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 401 9.3.2.4 atd control register 3 (atdctl3) this register controls the conversion sequence length, fifo for results registers and behavior in freeze mode. writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 76543210 r0 s8c s4c s2c s1c fifo frz1 frz0 w reset 0 0 1 00000 = unimplemented or reserved figure 9-6. atd control register 3 (atdctl3) table 9-8. atdctl3 field descriptions field description 6 s8c conversion sequence length this bit controls the number of conversions per sequence. table 9-9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 5 s4c conversion sequence length this bit controls the number of conversions per sequence. table 9-9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 4 s2c conversion sequence length this bit controls the number of conversions per sequence. table 9-9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 3 s1c conversion sequence length this bit controls the number of conversions per sequence. table 9-9 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 402 freescale semiconductor 2 fifo result register fifo mode ?f this bit is zero (non-fifo mode), the a/d conversion results map into the result registers based on the conversion sequence; the result of the ?st conversion appears in the ?st result register, the second result in the second result register, and so on. if this bit is one (fifo mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. in a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ?e. the conversion counter value (cc3-0 in atdstat0) can be used to determine where in the result register ?e, the current conversion result will be placed. aborting a conversion or starting a new conversion by write to an atdctl register (atdctl5-0) clears the conversion counter even if fifo=1. so the ?st result of a new conversion sequence, started by writing to atdctl5, will always be place in the ?st result register (atdddr0). intended usage of fifo mode is continuos conversion (scan=1) or triggered conversion (etrig=1). finally, which result registers hold valid data can be tracked using the conversion complete ?gs. fast ?g clear mode may or may not be useful in a particular application to track valid data. 0 conversion results are placed in the corresponding result register up to the selected sequence length. 1 conversion results are placed in consecutive result registers (wrap around at end). 1:0 frz[1:0] background debug freeze enable when debugging an application, it is useful in many cases to have the atd pause when a breakpoint (freeze mode) is encountered. these 2 bits determine how the atd will respond to a breakpoint as shown in table 9-10 . leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. table 9-9. conversion sequence length coding s8c s4c s2c s1c number of conversions per sequence 0000 16 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 table 9-8. atdctl3 field descriptions (continued) field description 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 403 table 9-10. atd behavior in freeze mode (breakpoint) frz1 frz0 behavior in freeze mode 0 0 continue conversion 0 1 reserved 1 0 finish current conversion, then freeze 1 1 freeze immediately 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 404 freescale semiconductor 9.3.2.5 atd control register 4 (atdctl4) this register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the a/d conversion (i.e., 8-bits or 10-bits). writes to this register will abort current conversion sequence but will not start a new sequence. read: anytime write: anytime 76543210 r sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w reset 0 0 0 00101 figure 9-7. atd control register 4 (atdctl4) table 9-11. atdctl4 field descriptions field description 7 sres8 a/d resolution select ?this bit selects the resolution of a/d conversion results as either 8 or 10 bits. the a/d converter has an accuracy of 10 bits. however, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10 bit resolution 1 8 bit resolution 6:5 smp[1:0] sample time select ?hese two bits select the length of the second phase of the sample time in units of atd conversion clock cycles. note that the atd conversion clock period is itself a function of the prescaler value (bits prs4-0). the sample time consists of two phases. the ?st phase is two atd conversion clock cycles long and transfers the sample quickly (via the buffer ampli?r) onto the a/d machines storage node. the second phase attaches the external analog signal directly to the storage node for ?al charging and high accuracy. table 9-12 lists the lengths available for the second sample phase. 4:0 prs[4:0] atd clock prescaler ?these 5 bits are the binary value prescaler value prs. the atd conversion clock frequency is calculated as follows: note: the maximum atd conversion clock frequency is half the bus clock. the default (after reset) prescaler value is 5 which results in a default atd conversion clock frequency that is bus clock divided by 12. table 9-13 illustrates the divide-by operation and the appropriate range of the bus clock. table 9-12. sample time select smp1 smp0 length of 2nd phase of sample time 0 0 2 a/d conversion clock periods 0 1 4 a/d conversion clock periods 1 0 8 a/d conversion clock periods 1 1 16 a/d conversion clock periods atdclock busclock [] prs 1 + [] -------------------------------- 0.5 = 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 405 table 9-13. clock prescaler values prescale value total divisor value max. bus clock 1 1 maximum atd conversion clock frequency is 2 mhz. the maximum allowed bus clock frequency is shown in this column. min. bus clock 2 2 minimum atd conversion clock frequency is 500 khz. the minimum allowed bus clock frequency is shown in this column. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 divide by 2 divide by 4 divide by 6 divide by 8 divide by 10 divide by 12 divide by 14 divide by 16 divide by 18 divide by 20 divide by 22 divide by 24 divide by 26 divide by 28 divide by 30 divide by 32 divide by 34 divide by 36 divide by 38 divide by 40 divide by 42 divide by 44 divide by 46 divide by 48 divide by 50 divide by 52 divide by 54 divide by 56 divide by 58 divide by 60 divide by 62 divide by 64 4 mhz 8 mhz 12 mhz 16 mhz 20 mhz 24 mhz 28 mhz 32 mhz 36 mhz 40 mhz 44 mhz 48 mhz 52 mhz 56 mhz 60 mhz 64 mhz 68 mhz 72 mhz 76 mhz 80 mhz 84 mhz 88 mhz 92 mhz 96 mhz 100 mhz 104 mhz 108 mhz 112 mhz 116 mhz 120 mhz 124 mhz 128 mhz 1 mhz 2 mhz 3 mhz 4 mhz 5 mhz 6 mhz 7 mhz 8 mhz 9 mhz 10 mhz 11 mhz 12 mhz 13 mhz 14 mhz 15 mhz 16 mhz 17 mhz 18 mhz 19 mhz 20 mhz 21 mhz 22 mhz 23 mhz 24 mhz 25 mhz 26 mhz 27 mhz 28 mhz 29 mhz 30 mhz 31 mhz 32 mhz 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 406 freescale semiconductor 9.3.2.6 atd control register 5 (atdctl5) this register selects the type of conversion sequence and the analog input channels sampled. writes to this register will abort current conversion sequence and start a new conversion sequence. if external trigger is enabled (etrige = 1) an initial write to atdctl5 is required to allow starting of a conversion sequence which will then occur on each trigger event. start of conversion means the beginning of the sampling phase. read: anytime write: anytime 76543210 r djm dsgn scan mult cd cc cb ca w reset 0 0 0 00000 figure 9-8. atd control register 5 (atdctl5) table 9-14. atdctl5 field descriptions field description 7 djm result register data justi?ation this bit controls justi?ation of conversion data in the result registers. see section 9.3.2.16, ?td conversion result registers (atddrx) for details. 0 left justi?d data in the result registers. 1 right justi?d data in the result registers. 6 dsgn result register data signed or unsigned representation this bit selects between signed and unsigned conversion data representation in the result registers. signed data is represented as 2s complement. signed data is not available in right justi?ation. see 9.3.2.16 atd conversion result registers (atddrx) for details. 0 unsigned data representation in the result registers. 1 signed data representation in the result registers. table 9-15 summarizes the result data formats available and how they are set up using the control bits. table 9-16 illustrates the difference between the signed and unsigned, left justi?d output codes for an input signal range between 0 and 5.12 volts. 5 scan continuous conversion sequence mode this bit selects whether conversion sequences are performed continuously or only once. if external trigger is enabled (etrige=1) setting this bit has no effect, that means each trigger event starts a single conversion sequence. 0 single conversion sequence 1 continuous conversion sequences (scan mode) 4 mult multi-channel sample mode ?when mult is 0, the atd sequence controller samples only from the speci?d analog input channel for an entire conversion sequence. the analog channel is selected by channel selection code (control bits cd/cc/cb/ca located in atdctl5). when mult is 1, the atd sequence controller samples across channels. the number of channels sampled is determined by the sequence length value (s8c, s4c, s2c, s1c). the ?st analog channel examined is determined by channel selection code (cc, cb, ca control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to an0 (channel 0. 0 sample only one channel 1 sample across several channels 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 407 3:0 c[d:a} analog input channel select code ?these bits select the analog input channel(s) whose signals are sampled and converted to digital codes. table 9-17 lists the coding used to select the various analog input channels. in the case of single channel conversions (mult = 0), this selection code speci?d the channel to be examined. in the case of multiple channel conversions (mult = 1), this selection code represents the ?st channel to be examined in the conversion sequence. subsequent channels are determined by incrementing the channel selection code or wrapping around to an0 (after converting the channel de?ed by the wrap around channel select bits wrap[3:0] in atdctl0). in case starting with a channel number higher than the one de?ed by wrap[3:0] the ?st wrap around will be an15 to an0. table 9-15. available result data formats . sres8 djm dsgn result data formats description and bus bit mapping 1 1 1 0 0 0 0 0 1 0 0 1 0 1 x 0 1 x 8-bit / left justi?d / unsigned ?bits 15:8 8-bit / left justi?d / signed ?bits 15:8 8-bit / right justi?d / unsigned ?bits 7:0 10-bit / left justi?d / unsigned ?bits 15:6 10-bit / left justi?d / signed -?bits 15:6 10-bit / right justi?d / unsigned ?bits 9:0 table 9-16. left justi?d, signed and unsigned atd output codes. input signal v rl = 0 volts v rh = 5.12 volts signed 8-bit codes unsigned 8-bit codes signed 10-bit codes unsigned 10-bit codes 5.120 volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 7f 7f 7e 01 00 ff 81 80 ff ff fe 81 80 7f 01 00 7fc0 7f00 7e00 0100 0000 ff00 8100 8000 ffc0 ff00 fe00 8100 8000 7f00 0100 0000 table 9-14. atdctl5 field descriptions (continued) field description 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 408 freescale semiconductor table 9-17. analog input channel select coding cd cc cb ca analog input channel 0 0 0 0 an0 0 0 0 1 an1 0 0 1 0 an2 0 0 1 1 an3 0 1 0 0 an4 0 1 0 1 an5 0 1 1 0 an6 0 1 1 1 an7 1 0 0 0 an8 1 0 0 1 an9 1 0 1 0 an10 1 0 1 1 an11 1 1 0 0 an12 1 1 0 1 an13 1 1 1 0 an14 1 1 1 1 an15 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 409 9.3.2.7 atd status register 0 (atdstat0) this read-only register contains the sequence complete flag, overrun ?gs for external trigger and fifo mode, and the conversion counter. read: anytime write: anytime (no effect on cc[3:0]) 76543210 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w reset 0 0 0 00000 = unimplemented or reserved figure 9-9. atd status register 0 (atdstat0) table 9-18. atdstat0 field descriptions field description 7 scf sequence complete flag ?this ?g is set upon completion of a conversion sequence. if conversion sequences are continuously performed (scan = 1), the ?g is set after each one is completed. this ?g is cleared when one of the following occurs: write ??to scf write to atdctl5 (a new conversion sequence is started) if affc = 1 and read of a result register 0 conversion sequence not completed 1 conversion sequence has completed 5 etorf external trigger overrun flag ?hile in edge trigger mode (etrigle = 0), if additional active edges are detected while a conversion sequence is in process the overrun ?g is set. this ?g is cleared when one of the following occurs: write ??to etorf write to atdctl0,1,2,3,4 (a conversion sequence is aborted) write to atdctl5 (a new conversion sequence is started) 0 no external trigger over run error has occurred 1 external trigger over run error has occurred 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 410 freescale semiconductor 4 fifor fifo over run flag ?this bit indicates that a result register has been written to before its associated conversion complete ?g (ccf) has been cleared. this ?g is most useful when using the fifo mode because the ?g potentially indicates that result registers are out of sync with the input channels. however, it is also practical for non-fifo modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). this ?g is cleared when one of the following occurs: write ??to fifor start a new conversion sequence (write to atdctl5 or external trigger) 0 no over run has occurred 1 overrun condition exists (result register has been written while associated ccfx ?g remained set) 3:0 cc[3:0} conversion counter these 4 read-only bits are the binary value of the conversion counter. the conversion counter points to the result register that will receive the result of the current conversion. for example, cc3 = 0, cc2 = 1, cc1 = 1, cc0 = 0 indicates that the result of the current conversion will be in atd result register 6. if in non-fifo mode (fifo = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. if in fifo mode (fifo = 1) the register counter is not initialized. the conversion counters wraps around when its maximum value is reached. aborting a conversion or starting a new conversion by write to an atdctl register (atdctl5-0) clears the conversion counter even if fifo=1. table 9-18. atdstat0 field descriptions (continued) field description 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 411 9.3.2.8 reserved register 0 (atdtest0) read: anytime, returns unpredictable values write: anytime in special modes, unimplemented in normal modes note writing to this register when in special modes can alter functionality. 9.3.2.9 atd test register 1 (atdtest1) this register contains the sc bit used to enable special channel conversions. read: anytime, returns unpredictable values for bit 7 and bit 6 write: anytime note writing to this register when in special modes can alter functionality. 76543210 ruuuuuuuu w reset 1 0 0 00000 = unimplemented or reserved u = unaffected figure 9-10. reserved register 0 (atdtest0) 76543210 ruuuuuuu sc w reset 0 0 0 00000 = unimplemented or reserved u = unaffected figure 9-11. reserved register 1 (atdtest1) table 9-19. atdtest1 field descriptions field description 0 sc special channel conversion bit ?if this bit is set, then special channel conversion can be selected using cc, cb, and ca of atdctl5. table 9-20 lists the coding. 0 special channel conversions disabled 1 special channel conversions enabled 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 412 freescale semiconductor 9.3.2.10 atd status register 2 (atdstat2) this read-only register contains the conversion complete flags ccf15 to ccf8. read: anytime write: anytime, no effect table 9-20. special channel select coding sc cd cc cb ca analog input channel 1 0 0 x x reserved 101 0 0 v rh 101 0 1 v rl 101 1 0 (v rh +v rl ) / 2 1 0 1 1 1 reserved 1 1 x x x reserved 76543210 r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w reset 0 0 0 00000 = unimplemented or reserved figure 9-12. atd status register 2 (atdstat2) table 9-21. atdstat2 field descriptions field description 7:0 ccf[15:8] conversion complete flag bits ?a conversion complete ?g is set at the end of each conversion in a conversion sequence. the ?gs are associated with the conversion position in a sequence (and also the result register number). therefore, ccf8 is set when the ninth conversion in a sequence is complete and the result is available in result register atddr8; ccf9 is set when the tenth conversion in a sequence is complete and the result is available in atddr9, and so forth. a ?g ccfx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when one of the following occurs: write to atdctl5 (a new conversion sequence is started) if affc = 0 and read of atdstat2 followed by read of result register atddrx if affc = 1 and read of result register atddrx in case of a concurrent set and clear on ccfx: the clearing by method a) will overwrite the set. the clearing by methods b) or c) will be overwritten by the set. 0 conversion number x not completed 1 conversion number x has completed, result ready in atddrx 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 413 9.3.2.11 atd status register 1 (atdstat1) this read-only register contains the conversion complete flags ccf7 to ccf0 read: anytime write: anytime, no effect 76543210 r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w reset 0 0 0 00000 = unimplemented or reserved figure 9-13. atd status register 1 (atdstat1) table 9-22. atdstat1 field descriptions field description 7:0 ccf[7:0] conversion complete flag bits ?a conversion complete ?g is set at the end of each conversion in a conversion sequence. the ?gs are associated with the conversion position in a sequence (and also the result register number). therefore, ccf0 is set when the ?st conversion in a sequence is complete and the result is available in result register atddr0; ccf1 is set when the second conversion in a sequence is complete and the result is available in atddr1, and so forth. a ccf ?g is cleared when one of the following occurs: write to atdctl5 (a new conversion sequence is started) if affc = 0 and read of atdstat1 followed by read of result register atddrx if affc = 1 and read of result register atddrx in case of a concurrent set and clear on ccfx: the clearing by method a) will overwrite the set. the clearing by methods b) or c) will be overwritten by the set. conversion number x not completed conversion number x has completed, result ready in atddrx 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 414 freescale semiconductor 9.3.2.12 atd input enable register 0 (atddien0) read: anytime write: anytime 9.3.2.13 atd input enable register 1 (atddien1) read: anytime write: anytime 76543210 r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w reset 0 0 0 00000 figure 9-14. atd input enable register 0 (atddien0) table 9-23. atddien0 field descriptions field description 7:0 ien[15:8] atd digital input enable on channel bits ?this bit controls the digital input buffer from the analog input pin (anx) to ptadx data register. 0 disable digital input buffer to ptadx 1 enable digital input buffer to ptadx. note: setting this bit will enable the corresponding digital input buffer continuously. if this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. 76543210 r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w reset 0 0 0 00000 figure 9-15. atd input enable register 1 (atddien1) table 9-24. atddien1 field descriptions field description 7:0 ien[7:0] atd digital input enable on channel bits ?this bit controls the digital input buffer from the analog input pin (anx) to ptadx data register. 0 disable digital input buffer to ptadx 1 enable digital input buffer to ptadx. note: setting this bit will enable the corresponding digital input buffer continuously. if this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 415 9.3.2.14 port data register 0 (portad0) the data port associated with the atd is input-only. the port pins are shared with the analog a/d inputs an[15:8]. read: anytime write: anytime, no effect the a/d input channels may be used for general-purpose digital input. 76543210 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w reset 1 1 1 11111 pin function an15 an14 an13 an12 an11 an10 an9 an8 = unimplemented or reserved figure 9-16. port data register 0 (portad0) table 9-25. portad0 field descriptions field description 7:0 ptad[15:8] a/d channel x (anx) digital input bits ?if the digital input buffer on the anx pin is enabled (ienx = 1) or channel x is enabled as external trigger (etrige = 1, etrigch[3-0] = x, etrigsel = 0) read returns the logic level on anx pin (signal potentials not meeting v il or v ih speci?ations will have an indeterminate value)). if the digital input buffers are disabled (ienx = 0) and channel x is not enabled as external trigger, read returns a ?? reset sets all portad0 bits to ?? 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 416 freescale semiconductor 9.3.2.15 port data register 1 (portad1) the data port associated with the atd is input-only. the port pins are shared with the analog a/d inputs an7-0. read: anytime write: anytime, no effect the a/d input channels may be used for general-purpose digital input. 76543210 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w reset 1 1 1 11111 pin function an 7 an6 an5 an4 an3 an2 an1 an0 = unimplemented or reserved figure 9-17. port data register 1 (portad1) table 9-26. portad1 field descriptions field description 7:0 ptad[7:8] a/d channel x (anx) digital input bits ?if the digital input buffer on the anx pin is enabled (ienx=1) or channel x is enabled as external trigger (etrige = 1, etrigch[3-0] = x, etrigsel = 0) read returns the logic level on anx pin (signal potentials not meeting v il or v ih speci?ations will have an indeterminate value)). if the digital input buffers are disabled (ienx = 0) and channel x is not enabled as external trigger, read returns a ?? reset sets all portad1 bits to ?? 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 417 9.3.2.16 atd conversion result registers (atddrx) the a/d conversion results are stored in 16 read-only result registers. the result data is formatted in the result registers bases on two criteria. first there is left and right justi?ation; this selection is made using the djm control bit in atdctl5. second there is signed and unsigned data; this selection is made using the dsgn control bit in atdctl5. signed data is stored in 2s complement format and only exists in left justi?d format. signed data selected for right justi?d format is ignored. read: anytime write: anytime in special mode, unimplemented in normal modes 9.3.2.16.1 left justi?d result data 76543210 r (10-bit) r (8-bit) bit 9 msb bit 7 msb bit 8 bit 6 bit 7 bit 5 bit 6 bit 4 bit 5 bit 3 bit 4 bit 2 bit 3 bit 1 bit 2 bit 0 w reset 00000000 = unimplemented or reserved figure 9-18. left justi?d, atd conversion result register x, high byte (atddrxh) 76543210 r (10-bit) r (8-bit) bit 1 u bit 0 u 0 0 0 0 0 0 0 0 0 0 0 0 w reset 00000000 = unimplemented or reserved u = unaffected figure 9-19. left justi?d, atd conversion result register x, low byte (atddrxl) 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 418 freescale semiconductor 9.3.2.16.2 right justi?d result data 9.4 functional description the atd10b16c is structured in an analog and a digital sub-block. 9.4.1 analog sub-block the analog sub-block contains all analog electronics required to perform a single conversion. separate power supplies v dda and v ssa allow to isolate noise of other mcu circuitry from the analog sub-block. 9.4.1.1 sample and hold machine the sample and hold (s/h) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. the sample process uses a two stage approach. during the ?st stage, the sample ampli?r is used to quickly charge the storage node.the second stage connects the input directly to the storage node to complete the sample for high accuracy. when not sampling, the sample and hold machine disables its own clocks. the analog electronics continue drawing their quiescent current. the power down (adpu) bit must be set to disable both the digital clocks and the analog power consumption. the input analog signals are unipolar and must fall within the potential range of v ssa to vdda. 76543210 r (10-bit) r (8-bit) 0 0 0 0 0 0 0 0 0 0 0 0 bit 9 msb 0 bit 8 0 w reset 00000000 = unimplemented or reserved figure 9-20. right justi?d, atd conversion result register x, high byte (atddrxh) 76543210 r (10-bit) r (8-bit) bit 7 bit 7 msb bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 w reset 00000000 = unimplemented or reserved figure 9-21. right justi?d, atd conversion result register x, low byte (atddrxl) 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 419 9.4.1.2 analog input multiplexer the analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. 9.4.1.3 sample buffer ampli?r the sample ampli?r is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 9.4.1.4 analog-to-digital (a/d) machine the a/d machine performs analog to digital conversions. the resolution is program selectable at either 8 or 10 bits. the a/d machine uses a successive approximation architecture. it functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. by following a binary search algorithm, the a/d machine locates the approximating potential that is nearest to the sampled potential. when not converting the a/d machine disables its own clocks. the analog electronics continue drawing quiescent current. the power down (adpu) bit must be set to disable both the digital clocks and the analog power consumption. only analog input signals within the potential range of v rl to v rh (a/d reference potentials) will result in a non-railed digital output codes. 9.4.2 digital sub-block this subsection explains some of the digital features in more detail. see register descriptions for all details. 9.4.2.1 external trigger input the external trigger feature allows the user to synchronize atd conversions to the external environment events rather than relying on software to signal the atd module when atd conversions are to take place. the external trigger signal (out of reset atd channel 15, con?urable in atdctl1) is programmable to be edge or level sensitive with polarity control. table 9-27 gives a brief description of the different combinations of control bits and their effect on the external trigger function. during a conversion, if additional active edges are detected the overrun error ?g etorf is set. table 9-27. external trigger control bits etrigle etrigp etrige scan description x x 0 0 ignores external trigger. performs one conversion sequence and stops. x x 0 1 ignores external trigger. performs continuous conversion sequences. 0 0 1 x falling edge triggered. performs one conversion sequence per trigger. 0 1 1 x rising edge triggered. performs one conversion sequence per trigger. 1 0 1 x trigger active low. performs continuous conversions while trigger is active. 1 1 1 x trigger active high. performs continuous conversions while trigger is active. 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 420 freescale semiconductor in either level or edge triggered modes, the ?st conversion begins when the trigger is received. in both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. after etrige is enabled, conversions cannot be started by a write to atdctl5, but rather must be triggered externally. if the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. therefore, the ?g is not set. if the trigger remains asserted in level mode while a sequence is completing, another sequence will be triggered immediately. 9.4.2.2 general-purpose digital input port operation the input channel pins can be multiplexed between analog and digital data. as analog inputs, they are multiplexed and sampled to supply signals to the a/d converter. as digital inputs, they supply external input data that can be accessed through the digital port registers (portad0 & portad1) (input-only). the analog/digital multiplex operation is performed in the input pads. the input pad is always connected to the analog inputs of the atd10b16c. the input pad signal is buffered to the digital port registers. this buffer can be turned on or off with the atddien0 & atddien1 register. this is important so that the buffer does not draw excess current when analog potentials are presented at its input. 9.4.3 operation in low power modes the atd10b16c can be con?ured for lower mcu power consumption in three different ways: stop mode stop mode: this halts a/d conversion. exit from stop mode will resume a/d conversion, but due to the recovery time the result of this conversion should be ignored. entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. this halts any conversion sequence in progress. during recovery from stop mode, there must be a minimum delay for the stop recovery time t sr before initiating a new atd conversion sequence. wait mode wait mode with awai = 1: this halts a/d conversion. exit from wait mode will resume a/d conversion, but due to the recovery time the result of this conversion should be ignored. entering wait mode, the atd conversion either continues or halts for low power depending on the logical value of the await bit. freeze mode writing adpu = 0 (note that all atd registers remain accessible.): this aborts any a/d conversion in progress. in freeze mode, the atd10b16c will behave according to the logical values of the frz1 and frz0 bits. this is useful for debugging and emulation. note the reset value for the adpu bit is zero. therefore, when this module is reset, it is reset into the power down state. 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 421 9.5 resets at reset the atd10b16c is in a power down state. the reset state of each individual bit is listed within section 9.3, ?emory map and register de?ition , which details the registers and their bit ?lds. 9.6 interrupts the interrupt requested by the atd10b16c is listed in table 9-28 . refer to mcu speci?ation for related vector address and priority. see section 9.3.2, ?egister descriptions , for further details. table 9-28. atd interrupt vectors interrupt source ccr mask local enable sequence complete interrupt i bit ascie in atdctl2 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 422 freescale semiconductor 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 423 4 .com u datasheet
chapter 9 analog-to-digital converter (atd10b16cv4) MC9S12XHZ512 data sheet, rev. 1.02 424 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 425 chapter 10 liquid crystal display (lcd32f4bv1) 10.1 introduction the lcd32f4bv1 driver module has 32 frontplane drivers and 4 backplane drivers so that a maximum of 128 lcd segments are controllable. each segment is controlled by a corresponding bit in the lcd ram. four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. the v 0 voltage is the lowest level of the output waveform and v 3 becomes the highest level. all frontplane and backplane pins can be multiplexed with other port functions. the lcd32f4bv1 driver system consists of five major sub-modules: timing and control ?consists of registers and control logic for frame clock generation, bias voltage level select, frame duty select, backplane select, and frontplane select/enable to produce the required frame frequency and voltage waveforms. lcd ram contains the data to be displayed on the lcd. data can be read from or written to the display ram at any time. frontplane drivers ?consists of 32 frontplane drivers. backplane drivers ?consists of 4 backplane drivers. voltage generator ?based on voltage applied to vlcd, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms. 10.1.1 features the lcd32f4bv1 includes these distinctive features: supports ve lcd operation modes 32 frontplane drivers 4 backplane drivers each frontplane has an enable bit respectively programmable frame clock generator programmable bias voltage level selector on-chip generation of 4 different output voltage levels 10.1.2 modes of operation the lcd32f4bv1 module supports ve operation modes with different numbers of backplanes and different biasing levels. during pseudo stop mode and wait mode the lcd operation can be suspended 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 426 freescale semiconductor under software control. depending on the state of internal bits, the lcd can operate normally or the lcd clock generation can be turned off and the lcd32f4bv1 module enters a power conservation state. this is a high level description only, detailed descriptions of operating modes are contained in section 10.4.2, ?peration in wait mode , section 10.4.3, ?peration in pseudo stop mode , and section 10.4.4, ?peration in stop mode . 10.1.3 block diagram figure 10-1 is a block diagram of the lcd32f4bv1 module. figure 10-1. lcd32f4bv1 block diagram lcd ram 16 bytes timing and control logic frontplane drivers voltage generator backplane drivers internal address/data/clocks v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 fp[31:0] vlcd bp[3:0] prescaler oscclk lcd clock 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 427 10.2 external signal description the lcd32f4bv1 module has a total of 37 external pins. 10.2.1 bp[3:0] ?analog backplane pins this output signal vector represents the analog backplane waveforms of the lcd32f4bv1 module and is connected directly to the corresponding pads. 10.2.2 fp[31:0] ?analog frontplane pins this output signal vector represents the analog frontplane waveforms of the lcd32f4bv1 module and is connected directly to the corresponding pads. 10.2.3 vlcd ?lcd supply voltage pin positive supply voltage for the lcd waveform generation. 10.3 memory map and register de?ition this section provides a detailed description of all memory and registers. 10.3.1 module memory map the memory map for the lcd32f4bv1 module is given in table 10-2 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the lcd32f4bv1 module and the address offset for each register. table 10-1. signal properties name port function reset state 4 backplane waveforms bp[3:0] backplane waveform signals that connect directly to the pads high impedance 32 frontplane waveforms fp[31:0] frontplane waveform signals that connect directly to the pads high impedance lcd voltage vlcd lcd supply voltage 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 428 freescale semiconductor table 10-2. lcd32f4bv1 memory map address offset use access 0x0000 lcd control register 0 (lcdcr0) read/write 0x0001 lcd control register 1 (lcdcr1) read/write 0x0002 lcd frontplane enable register 0 (fpenr0) read/write 0x0003 lcd frontplane enable register 1 (fpenr1) read/write 0x0004 lcd frontplane enable register 2 (fpenr2) read/write 0x0005 lcd frontplane enable register 3 (fpenr3) read/write 0x0006 unimplemented 0x0007 unimplemented 0x0008 lcdram (location 0) read/write 0x0009 lcdram (location 1) read/write 0x000a lcdram (location 2) read/write 0x000b lcdram (location 3) read/write 0x000c lcdram (location 4) read/write 0x000d lcdram (location 5) read/write 0x000e lcdram (location 6) read/write 0x000f lcdram (location 7) read/write 0x0010 lcdram (location 8) read/write 0x0011 lcdram (location 9) read/write 0x0012 lcdram (location 10) read/write 0x0013 lcdram (location 11) read/write 0x0014 lcdram (location 12) read/write 0x0015 lcdram (location 13) read/write 0x0016 lcdram (location 14) read/write 0x0017 lcdram (location 15) read/write 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 429 10.3.2 register descriptions this section consists of register descriptions. each description includes a standard register diagram. details of register bit and field function follow the register diagrams, in bit order. 10.3.2.1 lcd control register 0 (lcdcr0) read: anytime write: lcden anytime. to avoid segment flicker the clock prescaler bits, the bias select bit and the duty select bits must not be changed when the lcd is enabled. 76543210 r lcden 0 lclk2 lclk1 lclk0 bias duty1 duty0 w reset 0 0 0 00000 = unimplemented or reserved figure 10-2. lcd control register 0 (lcdcr0) table 10-3. lcdcr0 field descriptions field description 7 lcden lcd32f4bv1 driver system enable ?the lcden bit starts the lcd waveform generator. 0 all frontplane and backplane pins are disabled. in addition, the lcd32f4bv1 system is disabled and all lcd waveform generation clocks are stopped. 1 lcd driver system is enabled. all fp[31:0] pins with fp[31:0]en set, will output an lcd driver waveform the bp[3:0] pins will output an lcd32f4bv1 driver waveform based on the settings of duty0 and duty1. 5:3 lclk[2:0] lcd clock prescaler the lcd clock prescaler bits determine the oscclk divider value to produce the lcd clock frequency. for detailed description of the correlation between lcd clock prescaler bits and the divider value please refer to table 10-7 . 2 bias bias voltage level select ?this bit selects the bias voltage levels during various lcd operating modes, as shown in table 10-8 . 1:0 duty[1:0] lcd duty select ?the duty1 and duty0 bits select the duty (multiplex mode) of the lcd32f4bv1 driver system, as shown in table 10-8 . 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 430 freescale semiconductor 10.3.2.2 lcd control register 1 (lcdcr1) read: anytime write: anytime 10.3.2.3 lcd frontplane enable register 0? (fpenr0?penr3) 76543210 r 0 0 0 0 0 0 lcdswai lcdrpstp w reset 0 0 0 00000 unimplemented or reserved figure 10-3. lcd control register 1 (lcdcr1) table 10-4. lcdcr1 field descriptions field description 1 lcdswai lcd stop in wait mode ?this bit controls the lcd operation while in wait mode. 0 lcd operates normally in wait mode. 1 stop lcd32f4bv1 driver system when in wait mode. 0 lcdrpstp lcd run in pseudo stop mode ?this bit controls the lcd operation while in pseudo stop mode. 0 stop lcd32f4bv1 driver system when in pseudo stop mode. 1 lcd operates normally in pseudo stop mode. 76543210 r fp7en fp6en fp5en fp4en fp3en fp2en fp1en fp0en w reset 0 0 0 00000 figure 10-4. lcd frontplane enable register 0 (fpenr0) 76543210 r fp15en fp14en fp13en fp12en fp11en fp10en fp9en fp8en w reset 0 0 0 00000 figure 10-5. lcd frontplane enable register 1 (fpenr1) 76543210 r fp23en fp22en fp21en fp20en fp19en fp18en fp17en fp16en w reset 0 0 0 00000 figure 10-6. lcd frontplane enable register 2 (fpenr2) 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 431 these bits enable the frontplane output waveform on the corresponding frontplane pin when lcden = 1. read: anytime write: anytime 10.3.2.4 lcd ram (lcdram) the lcd ram consists of 16 bytes. after reset the lcd ram contents will be indeterminate (i), as indicated by figure 10-8 . 76543210 r fp31en fp30en fp29en fp28en fp27en fp26en fp25en fp24en w reset 0 0 0 00000 figure 10-7. lcd frontplane enable register 3 (fpenr3) table 10-5. fpenr0?penr3 field descriptions field description 31:0 fp[31:0]en frontplane output enable ?the fp[31:0]en bit enables the frontplane driver outputs. if lcden = 0, these bits have no effect on the state of the i/o pins. it is recommended to set fp[31:0]en bits before lcden is set. 0 frontplane driver output disabled on fp[31:0]. 1 frontplane driver output enabled on fp[31:0]. 76543210 r fp1bp3 fp1bp2 fp1bp1 fp1bp0 fp0bp3 fp0bp2 fp0bp1 fp0bp0 lcdram w reset i i i i i i i i r fp3bp3 fp3bp2 fp3bp1 fp3bp0 fp2bp3 fp2bp2 fp2bp1 fp2bp0 lcdram w reset i i i i i i i i r fp5bp3 fp5bp2 fp5bp1 fp5bp0 fp4bp3 fp4bp2 fp4bp1 fp4bp0 lcdram w reset i i i i i i i i r fp7bp3 fp7bp2 fp7bp1 fp7bp0 fp6bp3 fp6bp2 fp6bp1 fp6bp0 lcdram w reset i i i i i i i i r fp9bp3 fp9bp2 fp9bp1 fp9bp0 fp8bp3 fp8bp2 fp8bp1 fp8bp0 lcdram w reset i i i i i i i i r fp11bp3 fp11bp2 fp11bp1 fp11bp0 fp10bp3 fp10bp2 fp10bp1 fp10bp0 lcdram w reset i i i i i i i i i = value is indeterminate figure 10-8. lcd ram (lcdram) 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 432 freescale semiconductor read: anytime write: anytime r fp13bp3 fp13bp2 fp13bp1 fp13bp0 fp12bp3 fp12bp2 fp12bp1 fp12bp0 lcdram w reset i i i i i i i i r fp15bp3 fp15bp2 fp15bp1 fp15bp0 fp14bp3 fp14bp2 fp14bp1 fp14bp0 lcdram w reset i i i i i i i i r fp17bp3 fp17bp2 fp17bp1 fp17bp0 fp16bp3 fp16bp2 fp16bp1 fp16bp0 lcdram w reset i i i i i i i i r fp19bp3 fp19bp2 fp19bp1 fp19bp0 fp18bp3 fp18bp2 fp18bp1 fp18bp0 lcdram w reset i i i i i i i i r fp21bp3 fp21bp2 fp21bp1 fp21bp0 fp20bp3 fp20bp2 fp20bp1 fp20bp0 lcdram w reset i i i i i i i i r fp23bp3 fp23bp2 fp23bp1 fp23bp0 fp22bp3 fp22bp2 fp22bp1 fp22bp0 lcdram w reset i i i i i i i i r fp25bp3 fp25bp2 fp25bp1 fp25bp0 fp24bp3 fp24bp2 fp24bp1 fp24bp0 lcdram w reset i i i i i i i i r fp27bp3 fp27bp2 fp27bp1 fp27bp0 fp26bp3 fp26bp2 fp26bp1 fp26bp0 lcdram w reset i i i i i i i i r fp29bp3 fp29bp2 fp29bp1 fp29bp0 fp28bp3 fp28bp2 fp28bp1 fp28bp0 lcdram w reset i i i i i i i i r fp31bp3 fp31bp2 fp31bp1 fp31bp0 fp30bp3 fp30bp2 fp30bp1 fp30bp0 lcdram w reset i i i i i i i i table 10-6. lcd ram field descriptions field description 31:0 3:0 fp[31:0] bp[3:0] lcd segment on the fp[31:0]bp[3:0] bit displays (turns on) the lcd segment connected between fp[31:0] and bp[3:0]. 0 lcd segment off 1 lcd segment on i = value is indeterminate figure 10-8. lcd ram (lcdram) (continued) 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 433 10.4 functional description this section provides a complete functional description of the lcd32f4bv1 block, detailing the operation of the design from the end user perspective in a number of subsections. 10.4.1 lcd driver description 10.4.1.1 frontplane, backplane, and lcd system during reset during a reset the following conditions exist: the lcd32f4bv1 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all backplanes are used. all frontplane enable bits, fp[31:0]en are cleared and the on/off control for the display, the lcden bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high impedance state. the mcu pin state during reset is defined by the port integration module (pim). 10.4.1.2 lcd clock and frame frequency the frequency of the oscillator clock (oscclk) and divider determine the lcd clock frequency. the divider is set by the lcd clock prescaler bits, lclk[2:0], in the lcd control register 0 (lcdcr0). table 10-7 shows the lcd clock and frame frequency for some multiplexed mode at oscclk = 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, and 0.5 mhz. for other combinations of oscclk and divider not shown in table 10-7 , the following formula may be used to calculate the lcd frame frequency for each multiplex mode: the possible divider values are shown in table 10-7 . table 10-7. lcd clock and frame frequency oscillator frequency in mhz lcd clock prescaler divider lcd clock frequency [hz] frame frequency [hz] lclk2 lclk1 lclk0 1/1 duty 1/2 duty 1/3 duty 1/4 duty oscclk = 0.5 0 0 0 0 0 1 1024 2048 488 244 488 244 244 122 163 81 122 61 oscclk = 1.0 0 0 0 1 1 0 2048 4096 488 244 488 244 244 122 163 81 122 61 oscclk = 2.0 0 0 1 1 0 1 4096 8192 488 244 488 244 244 122 163 81 122 61 oscclk = 4.0 0 1 1 0 1 0 8192 16384 488 244 488 244 244 122 163 81 122 61 oscclk = 8.0 1 1 0 0 0 1 16384 32768 488 244 488 244 244 122 163 81 122 61 oscclk = 16.0 1 1 1 1 0 1 65536 131072 244 122 244 122 122 61 81 40 61 31 lcd frame frequency (hz) oscclk (hz) divider ----------------------------------- - duty ? = 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 434 freescale semiconductor 10.4.1.3 lcd ram for a segment on the lcd to be displayed, data must be written to the lcd ram which is shown in section 10.3, ?emory map and register definition . the 128 bits in the lcd ram correspond to the 128 segments that are driven by the frontplane and backplane drivers. writing a 1 to a given location will result in the corresponding display segment being driven with a differential rms voltage necessary to turn the segment on when the lcden bit is set and the corresponding fp[31:0]en bit is set. writing a 0 to a given location will result in the corresponding display segment being driven with a differential rms voltage necessary to turn the segment off. the lcd ram is a dual port ram that interfaces with the internal address and data buses of the mcu. it is possible to read from lcd ram locations for scrolling purposes. when lcden = 0, the lcd ram can be used as on-chip ram. writing or reading of the lcden bit does not change the contents of the lcd ram. after a reset, the lcd ram contents will be indeterminate. 10.4.1.4 lcd driver system enable and frontplane enable sequencing if lcden = 0 (lcd32f4bv1 driver system disabled) and the frontplane enable bit, fp[31:0]en, is set, the frontplane driver waveform will not appear on the output until lcden is set. if lcden = 1 (lcd32f4bv1 driver system enabled), the frontplane driver waveform will appear on the output as soon as the corresponding frontplane enable bit, fp[31:0]en, in the registers fpenr0?penr3 is set. 10.4.1.5 lcd bias and modes of operation the lcd32f4bv1 driver has five modes of operation: 1/1 duty (1 backplane), 1/1 bias (2 voltage levels) 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels) 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) the voltage levels required for the different operating modes are generated internally based on vlcd. changing vlcd alters the differential rms voltage across the segments in the on and off states, thereby setting the display contrast. the backplane waveforms are continuous and repetitive every frame. they are fixed within each operating mode and are not affected by the data in the lcd ram. the frontplane waveforms generated are dependent on the state (on or off) of the lcd segments as defined in the lcd ram. the lcd32f4bv1 driver hardware uses the data in the lcd ram to construct the frontplane waveform to create a differential rms voltage necessary to turn the segment on or off. the lcd duty is decided by the duty1 and duty0 bits in the lcd control register 0 (lcdcr0). the number of bias voltage levels is determined by the bias bit in lcdcr0. table 10-8 summarizes the multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty). the backplane pins have their corresponding backplane waveform output bp[3:0] in high impedance state when in the off state as indicated in table 10-8 . in the off state the corresponding pins bp[3:0]can be used for other functionality, for example as general purpose i/o ports. 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 435 10.4.2 operation in wait mode the lcd32f4bv1 driver system operation during wait mode is controlled by the lcd stop in wait (lcdswai) bit in the lcd control register 1 (lcdcr1). if lcdswai is reset, the lcd32f4bv1 driver system continues to operate during wait mode. if lcdswai is set, the lcd32f4bv1 driver system is turned off during wait mode. in this case, the lcd waveform generation clocks are stopped and the lcd32f4bv1 drivers pull down to vssx those frontplane and backplane pins that were enabled before entering wait mode. the contents of the lcd ram and the lcd registers retain the values they had prior to entering wait mode. 10.4.3 operation in pseudo stop mode the lcd32f4bv1 driver system operation during pseudo stop mode is controlled by the lcd run in pseudo stop (lcdrpstp) bit in the lcd control register 1 (lcdcr1). if lcdrpstp is reset, the lcd32f4bv1 driver system is turned off during pseudo stop mode. in this case, the lcd waveform generation clocks are stopped and the lcd32f4bv1 drivers pull down to vssx those frontplane and backplane pins that were enabled before entering pseudo stop mode. if lcdrpstp is set, the lcd32f4bv1 driver system continues to operate during pseudo stop mode. the contents of the lcd ram and the lcd registers retain the values they had prior to entering pseudo stop mode. 10.4.4 operation in stop mode all lcd32f4bv1 driver system clocks are stopped, the lcd32f4bv1 driver system pulls down to vssx those frontplane and backplane pins that were enabled before entering stop mode. also, during stop mode, the contents of the lcd ram and the lcd registers retain the values they had prior to entering stop mode. as a result, after exiting from stop mode, the lcd32f4bv1 driver system clocks will run (if lcden = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode. 10.4.5 lcd waveform examples figure 10-9 through figure 10-13 show the timing examples of the lcd output waveforms for the available modes of operation. table 10-8. lcd duty and bias duty lcdcr0 register backplanes bias (bias = 0) bias (bias = 1) duty1 duty0 bp3 bp2 bp1 bp0 1/1 1/2 1/3 1/1 1/2 1/3 1/1 1/2 1/3 1/4 0 1 1 0 1 0 1 0 off off off bp3 off off bp2 bp2 off bp1 bp1 bp1 bp0 bp0 bp0 bp0 yes na na na na yes na na na na yes yes yes na na na na na na na na yes yes yes 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 436 freescale semiconductor 10.4.5.1 1/1 duty multiplexed with 1/1 bias mode duty = 1/1:duty1 = 0, duty0 = 1 bias = 1/1:bias = 0 or bias = 1 v 0 = v 1 = vssx, v 2 = v 3 = vlcd - bp1, bp2, and bp3 are not used, a maximum of 32 segments are displayed. figure 10-9. 1/1 duty and 1/1 bias 0 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (off) +vlcd -vlcd bp0-fpy (on) vlcd vssx fpx (xxx0) vlcd vssx fpy (xxx1) 1 frame 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 437 10.4.5.2 1/2 duty multiplexed with 1/2 bias mode duty = 1/2:duty1 = 1, duty0 = 0 bias = 1/2:bias = 0 v 0 = vssx, v 1 = v 2 = vlcd * 1/2, v 3 = vlcd - bp2 and bp3 are not used, a maximum of 64 segments are displayed. figure 10-10. 1/2 duty and 1/2 bias 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (off) 1 frame vlcd 1/2 vlcd vssx bp1 vlcd vssx fpx (xx10) vlcd vssx fpy (xx00) vlcd vssx fpz (xx11) +vlcd 1/2 -vlcd 1/2 0 +vlcd -vlcd bp1-fpx (on) +vlcd 1/2 -vlcd 1/2 0 +vlcd -vlcd bp0-fpy (off) +vlcd 1/2 -vlcd 1/2 0 +vlcd -vlcd bp0-fpz (on) +vlcd 1/2 -vlcd 1/2 vlcd 1/2 vlcd 1/2 vlcd 1/2 vlcd 1/2 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 438 freescale semiconductor 10.4.5.3 1/2 duty multiplexed with 1/3 bias mode duty = 1/2:duty1 = 1, duty0 = 0 bias = 1/3:bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - bp2 and bp3 are not used, a maximum of 64 segments are displayed. figure 10-11. 1/2 duty and 1/3 bias -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 vlcd 1/3 0 vlcd vssx bp0 -vlcd bp0-fpx (off) 1 frame vlcd 2/3 +vlcd 2/3 -vlcd 2/3 vlcd vssx bp1 vlcd 2/3 vlcd vssx fpx (xx10) vlcd 2/3 vlcd vssx fpy (xx00) vlcd 2/3 vlcd vssx fpz (xx11) vlcd 2/3 +vlcd 1/3 -vlcd 1/3 0 +vlcd -vlcd bp1-fpx (on) +vlcd 2/3 -vlcd 2/3 +vlcd 1/3 0 +vlcd -vlcd bp0-fpy (off) +vlcd 2/3 -vlcd 2/3 0 +vlcd -vlcd bp0-fpz (on) +vlcd 2/3 -vlcd 2/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 +vlcd 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 439 10.4.5.4 1/3 duty multiplexed with 1/3 bias mode duty = 1/3:duty1 = 1, duty0 = 1 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - bp3 is not used, a maximum of 96 segments are displayed. figure 10-12. 1/3 duty and 1/3 bias +vlcd 1/3 -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (off) 1 frame vlcd 2/3 +vlcd 2/3 -vlcd 2/3 vlcd vssx bp1 vlcd 2/3 vlcd vssx bp2 vlcd 2/3 0 +vlcd -vlcd bp1-fpx (on) +vlcd 2/3 -vlcd 2/3 vlcd vssx fpx (x010) vlcd 2/3 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 440 freescale semiconductor 10.4.5.5 1/4 duty multiplexed with 1/3 bias mode duty = 1/4:duty1 = 0, duty0 = 0 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - a maximum of 128 segments are displayed. figure 10-13. 1/4 duty and 1/3 bias +vlcd 1/3 -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (on) 1 frame vlcd 2/3 +vlcd 2/3 -vlcd 2/3 vlcd vssx bp1 vlcd 2/3 vlcd vssx bp2 vlcd 2/3 0 +vlcd -vlcd bp1-fpx (off) +vlcd 2/3 -vlcd 2/3 vlcd vssx fpx (1001) vlcd 2/3 vlcd vssx bp3 vlcd 2/3 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 441 10.5 resets the reset values of registers and signals are described in section 10.3, ?emory map and register definition . the behavior of the lcd32f4bv1 system during reset is described in section 10.4.1, ?cd driver description . 10.6 interrupts this module does not generate any interrupts. 4 .com u datasheet
chapter 10 liquid crystal display (lcd32f4bv1) MC9S12XHZ512 data sheet, rev. 1.02 442 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 443 chapter 11 motor controller (mc10b12cv2) 11.1 introduction the block mc10b12c is a pwm motor controller suitable to drive instruments in a cluster con?uration or any other loads requiring a pwm signal. the motor controller has twelve pwm channels associated with two pins each (24 pins in total). 11.1.1 features the mc_10b12c includes the following features: 10/11-bit pwm counter 11-bit resolution with selectable pwm dithering function 7-bit resolution mode (fast mode): duty cycle can be changed by accessing only 1 byte/output left, right, or center aligned pwm output slew rate control this module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. this module can be used for other motor control or pwm applications that match the frequency, resolution, and output drive capabilities of the module. 11.1.2 modes of operation 11.1.2.1 functional modes 11.1.2.1.1 pwm resolution the motor controller can be con?ured to either 11- or 7-bits resolution mode by clearing or setting the fast bit. this bit in?ences all pwm channels. for details, please refer to section 11.3.2.5, ?otor controller duty cycle registers . 11.1.2.1.2 dither function dither function can be selected or deselected by setting or clearing the dith bit. this bit in?ences all pwm channels. for details, please refer to section 11.4.1.3.5, ?ither bit (dith) . 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 444 freescale semiconductor 11.1.2.2 pwm channel con?uration modes the twelve pwm channels can operate in three functional modes. those modes are, with some restrictions, selectable for each channel independently. 11.1.2.2.1 dual full h-bridge mode this mode is suitable to drive a stepper motor or a 360 o air gauge instrument. for details, please refer to section 11.4.1.1.1, ?ual full h-bridge mode (mcom = 11) . in this mode two adjacent pwm channels are combined, and two pwm channels drive four pins. 11.1.2.2.2 full h-bridge mode this mode is suitable to drive any load requiring a pwm signal in a h-bridge con?uration using two pins. for details please refer to section 11.4.1.1.2, ?ull h-bridge mode (mcom = 10) . 11.1.2.2.3 half h-bridge mode this mode is suitable to drive a 90 o instrument driven by one pin. for details, please refer to section 11.4.1.1.3, ?alf h-bridge mode (mcom = 00 or 01) . 11.1.2.3 pwm alignment modes each pwm channel can operate independently in three different alignment modes. for details, please refer to section 11.4.1.3.1, ?wm alignment modes . 11.1.2.4 low-power modes the behavior of the motor controller in low-power modes is programmable. for details, please refer to section 11.4.5, ?peration in wait mode and section 11.4.6, ?peration in stop and pseudo-stop modes . 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 445 11.1.3 block diagram figure 11-1. mc10b12c block diagram period register 11-bit timer/counter duty register 0 comparator m0c0m m0c0p duty register 1 comparator m0c1m m0c1p duty register 2 comparator m1c0m m1c0p duty register 3 comparator m1c1m m1c1p duty register 4 comparator m2c0m m2c0p duty register 5 comparator m2c1m m2c1p duty register 6 comparator m3c0m m3c0p duty register 7 comparator m3c1m m3c1p control registers fast dith 11 pwm channel pair pwm channel duty register 8 comparator m4c0m m4c0p duty register 9 comparator m4c1m m4c1p duty register 10 comparator m5c0m m5c0p duty register 11 comparator m5c1m m5c1p 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 446 freescale semiconductor 11.2 external signal description the motor controller is associated with 24 pins. table 11-1 lists the relationship between the pwm channels and signal pins as well as pwm channel pair (motor number), coils, and nodes they are supposed to drive if all channels are set to dual full h-bridge con?uration. 11.2.1 m0c0m/m0c0p/m0c1m/m0c1p ?pwm output pins for motor 0 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive current ?w through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current ?w through coil 1 when m0c1p is driven to a logic high state. table 11-1. pwm channel and pin assignment pin name pwm channel pwm channel pair 1 1 a pwm channel pair always consists of pwm channel x and pwm channel x+1 (x = 2 ? n). the term ?wm channel pair?is equivalent to the term ?otor? e.g. channel pair 0 is equivalent to motor 0 coil node m0c0m 0 0 0 minus m0c0p plus m0c1m 1 1 minus m0c1p plus m1c0m 2 1 0 minus m1c0p plus m1c1m 3 1 minus m1c1p plus m2c0m 4 2 0 minus m2c0p plus m2c1m 5 1 minus m2c1p plus m3c0m 6 3 0 minus m3c0p plus m3c1m 7 1 minus m3c1p plus m4c0m 8 4 0 minus m4c0p plus m4c1m 9 1 minus m4c1p plus m5c0m 10 5 0 minus m5c0p plus m5c1m 11 1 minus m5c1p plus 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 447 11.2.2 m1c0m/m1c0p/m1c1m/m1c1p ?pwm output pins for motor 1 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive current ?w through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current ?w through coil 1 when m1c1p is driven to a logic high state. 11.2.3 m2c0m/m2c0p/m2c1m/m2c1p ?pwm output pins for motor 2 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive current ?w through coil 0 when m2c0p is driven to a logic high state. pwm output on m2c1m results in a positive current ?w through coil 1 when m2c1p is driven to a logic high state. 11.2.4 m3c0m/m3c0p/m3c1m/m3c1p ?pwm output pins for motor 3 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive current ?w through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current ?w through coil 1 when m3c1p is driven to a logic high state. 11.2.5 m4c0m/m4c0p/m4c1m/m4c1p ?pwm output pins for motor 4 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive current ?w through coil 0 when m4c0p is driven to a logic high state. pwm output on m4c1m results in a positive current ?w through coil 1 when m4c1p is driven to a logic high state. 11.2.6 m5c0m/m5c0p/m5c1m/m5c1p ?pwm output pins for motor 5 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive current ?w through coil 0 when m5c0p is driven to a logic high state. pwm output on m5c1m results in a positive current ?w through coil 1 when m5c1p is driven to a logic high state. 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 448 freescale semiconductor 11.3 memory map and register de?ition this section provides a detailed description of all registers of the 10-bit 12-channel motor controller module. 11.3.1 module memory map table 11-2 shows the memory map of the 10-bit 12-channel motor controller module. table 11-2. mc10b12c - memory map address offset use access $00 mcctl0 rw $01 mcctl1 rw $02 mcper (high byte) rw $03 mcper (low byte) rw $04 reserved - $05 reserved - $06 reserved - $07 reserved - $08 reserved - $09 reserved - $0a reserved - $0b reserved - $0c reserved - $0d reserved - $0e reserved - $0f reserved - $10 mccc0 rw $11 mccc1 rw $12 mccc2 rw $13 mccc3 rw $14 mccc4 rw $15 mccc5 rw $16 mccc6 rw $17 mccc7 rw $18 mccc8 rw $19 mccc9 rw $1a mccc10 rw $1b mccc11 rw $1c reserved - $1d reserved - $1e reserved - $1f reserved - $20 mcdc0 (high byte) rw $21 mcdc0 (low byte) rw $22 mcdc1 (high byte) rw 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 449 $23 mcdc1 (low byte) rw $24 mcdc2 (high byte) rw $25 mcdc2 (low byte) rw $26 mcdc3 (high byte) rw $27 mcdc3 (low byte) rw $28 mcdc4 (high byte) rw $29 mcdc4 (low byte) rw $2a mcdc5 (high byte) rw $2b mcdc5 (low byte) rw $2c mcdc6 (high byte) rw $2d mcdc6 (low byte) rw $2e mcdc7 (high byte) rw $2f mcdc7 (low byte) rw $30 mcdc8 (high byte) rw $31 mcdc8 (low byte) rw $32 mcdc9 (high byte) rw $33 mcdc9 (low byte) rw $34 mcdc10 (high byte) rw $35 mcdc10 (low byte) rw $36 mcdc11 (high byte) rw $37 mcdc11 (low byte) rw $38 reserved - $39 reserved - $3a reserved - $3b reserved - $3c reserved - $3d reserved - $3e reserved - $3f reserved - table 11-2. mc10b12c - memory map 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 450 freescale semiconductor 11.3.2 register descriptions 11.3.2.1 motor controller control register 0 this register controls the operating mode of the motor controller module. . 76543210 r0 mcpre[1:0] mcswai fast dith 0 mctoif w reset 00000000 = unimplemented or reserved figure 11-3. motor controller control register 0 (mcctl0) table 11-3. mcctl0 field descriptions field description 6:5 mcpre[1:0] motor controller prescaler select mcpre1 and mcpre0 determine the prescaler value that sets the motor controller timer counter clock frequency (f tc ). the clock source for the prescaler is the peripheral bus clock (f bus ) as shown in figure 11-22 . writes to mcpre1 or mcpre0 will not affect the timer counter clock frequency f tc until the start of the next pwm period. table 11-4 shows the prescaler values that result from the possible combinations of mcpre1 and mcpre0 4 mcswai motor controller module stop in wait mode 0 entering wait mode has no effect on the motor controller module and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 1 entering wait mode will stop the clock of the module and debias the analog circuitry. the module will release the pins. 3 fast motor controller pwm resolution mode 0 pwm operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode. 1 pwm operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode. 2 dith motor control/driver dither feature enable (refer to section 11.4.1.3.5, ?ither bit (dith) ) 0 dither feature is disabled. 1 dither feature is enabled. 0 mctoif motor controller timer counter over?w interrupt flag ?this bit is set when a motor controller timer counter over?w occurs. the bit is cleared by writing a 1 to the bit. 0 a motor controller timer counter over?w has not occurred since the last reset or since the bit was cleared. 1 a motor controller timer counter over?w has occurred. table 11-4. prescaler values mcpre[1:0] f tc 00 f bus 01 f bus /2 10 f bus /4 11 f bus /8 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 451 11.3.2.2 motor controller control register 1 this register controls the behavior of the analog section of the motor controller as well as the interrupt enables. 76543210 r recirc 000000 mctoie w reset 00000000 = unimplemented or reserved figure 11-4. motor controller control register 1 (mcctl1) table 11-5. mcctl1 field descriptions field description 7 recirc recirculation in (dual) full h-bridge mode (refer to section 11.4.1.3.3, ?ecirc bit ) recirc only affects the outputs in (dual) full h-bridge modes. in half h-bridge mode, the pwm output is always active low. recirc = 1 will also invert the effect of the s bits (refer to section 11.4.1.3.2, ?ign bit (s) ) in (dual) full h-bridge modes. recirc must be changed only while no pwm channel is operating in (dual) full h-bridge mode; otherwise, erroneous output pattern may occur. 0 recirculation on the high side transistors. active state for pwm output is logic low, the static channel will output logic high. 1 recirculation on the low side transistors. active state for pwm output is logic high, the static channel will output logic low. 0 mctoie motor controller timer counter over?w interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the motor controller timer counter over?w interrupt ?g (mctoif) is set. 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 452 freescale semiconductor 11.3.2.3 motor controller period register the period register de?es per, the number of motor controller timer counter clocks a pwm period lasts. the motor controller timer counter is clocked with the frequency f tc . if dither mode is enabled (dith = 1, refer to section 11.4.1.3.5, ?ither bit (dith) ), p0 is ignored and reads as a 0. in this case per = 2 * d[10:1]. for example, programming mcper to 0x0022 (per = 34 decimal) will result in 34 counts for each complete pwm period. setting mcper to 0 will shut off all pwm channels as if mcam[1:0] is set to 0 in all channel control registers after the next period timer counter over?w. in this case, the motor controller releases all pins. note programming mcper to 0x0001 and setting the dith bit will be managed as if mcper is programmed to 0x0000. all pwm channels will be shut off after the next period timer counter over?w. 1514131211109876543210 r00000 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 11-5. motor controller period register (mcper) with dith = 0 1514131211109876543210 r00000 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 11-6. motor controller period register (mcper) with dith = 1 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 453 11.3.2.4 motor controller channel control registers each pwm channel has one associated control register to control output delay, pwm alignment, and output mode. the registers are named mccc0... mccc11. in the following, mccc0 is described as a reference for all twelve registers. 76543210 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w reset 00000000 = unimplemented or reserved figure 11-7. motor controller control register channel0 .. 11 (mccc0 .. mccc11) table 11-6. mccc0?ccc11 field descriptions field description 7:6 mcom[1:0] output mode mcom1, mcom0 control the pwm channels output mode. see table 11-7 . 5:4 mcam[1:0] pwm channel alignment mode mcam1, mcam0 control the pwm channels pwm alignment mode and operation. see table 11-8 . mcam[1:0] and mcom[1:0] are double buffered. the values used for the generation of the output waveform will be copied to the working registers either at once (if all pwm channels are disabled or mcper is set to 0) or if a timer counter over?w occurs. reads of the register return the most recent written value, which are not necessarily the currently active values. 1:0 cd[1:0] pwm channel delay each pwm channel can be individually delayed by a programmable number of pwm timer counter clocks. the delay will be n/f tc . see table 11-9 . table 11-7. output mode mcom[1:0] output mode 00 half h-bridge mode, pwm on mncxm, mncxp is released 01 half h-bridge mode, pwm on mncxp, mncxm is released 10 full h-bridge mode 11 dual full h-bridge mode table 11-8. pwm alignment mode mcam[1:0] pwm alignment mode 00 channel disabled 01 left aligned 10 right aligned 11 center aligned 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 454 freescale semiconductor note the pwm motor controller will release the pins after the next pwm timer counter over?w without accommodating any channel delay if a single channel has been disabled or if the period register has been cleared or all channels have been disabled. program one or more inactive pwm frames (duty cycle = 0) before writing a con?uration that disables a single channel or the entire pwm motor controller. 11.3.2.5 motor controller duty cycle registers each duty cycle register sets the sign and duty functionality for the respective pwm channel. the contents of the duty cycle registers de?e duty, the number of motor controller timer counter clocks the corresponding output is driven low (recirc = 0) or is driven high (recirc = 1). setting all bits to 0 will give a static high output in case of recirc = 0; otherwise, a static low output. values greater than or equal to the contents of the period register will generate a static low output in case of recirc = 0, or a static high output if recirc = 1. the layout of the duty cycle registers differ dependent upon the state of the fast bit in the control register 0. table 11-9. channel delay cd[1:0] n [# of pwm clocks] 00 0 01 1 10 2 11 3 1514131211109876543210 r s ssss d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 11-8. motor controller duty cycle register x (mcdcx) with fast = 0 1514131211109876543210 r s d8d7d6d5d4d3d2 00000000 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 11-9. motor controller duty cycle register x (mcdcx) with fast = 1 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 455 whenever fast = 1, the bits d10, d9, d1, and d0 will be set to 0 if the duty cycle register is written. for example setting mcdcx = 0x0158 with fast = 0 gives the same output waveform as setting mcdcx = 0x5600 with fast = 1 (with fast = 1, the low byte of mcdcx needs not to be written). the state of the fast bit has impact only during write and read operations. a change of the fast bit (set or clear) without writing a new value does not impact the internal interpretation of the duty cycle values. to prevent the output from inconsistent signals, the duty cycle registers are double buffered. the motor controller module will use working registers to generate the output signals. the working registers are copied from the bus accessible registers at the following conditions: mcper is set to 0 (all channels are disabled in this case) mcam[1:0] of the respective channel is set to 0 (channel is disabled) a pwm timer counter over?w occurs while in half h-bridge or full h-bridge mode a pwm channel pair is con?ured to work in dual full h-bridge mode and a pwm timer counter over?w occurs after the odd 1 duty cycle register of the channel pair has been written. in this way, the output of the pwm will always be either the old pwm waveform or the new pwm waveform, not some variation in between. reads of this register return the most recent value written. reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme. table 11-10. mcdcx field descriptions field description 0 s sign the sign bit is used to de?e which output will drive the pwm signal in (dual) full-h-bridge modes. the sign bit has no effect in half-bridge modes. see section 11.4.1.3.2, ?ign bit (s) , and table table 11-12 for detailed information about the impact of recirc and sign bit on the pwm output. 1. odd duty cycle register: mcdcx+1, x = 2 ? n 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 456 freescale semiconductor 11.4 functional description 11.4.1 modes of operation 11.4.1.1 pwm output modes the motor controller is con?urable between three output modes. dual full h-bridge mode can be used to control either a stepper motor or a 360 air core instrument. in this case two pwm channels are combined. in full h-bridge mode, each pwm channel is updated independently. in half h-bridge mode, one pin of the pwm channel can generate a pwm signal to control a 90 air core instrument (or other load requiring a pwm signal) and the other pin is unused. the mode of operation for each pwm channel is determined by the corresponding mcom[1:0] bits in channel control registers. after a reset occurs, each pwm channel will be disabled, the corresponding pins are released. each pwm channel consists of two pins. one output pin will generate a pwm signal. the other will operate as logic high or low output depending on the state of the recirc bit (refer to section 11.4.1.3.3, ?ecirc bit ), while in (dual) full h-bridge mode, or will be released, while in half h-bridge mode. the state of the s bit in the duty cycle register determines the pin where the pwm signal is driven in full h-bridge mode. while in half h-bridge mode, the state of the released pin is determined by other modules associated with this pin. associated with each pwm channel pair n are two pwm channels, x and x + 1, where x = 2 * n and n (0,1,2... 5) is the pwm channel pair number. duty cycle register x controls the sign of the pwm signal (which pin drives the pwm signal) and the duty cycle of the pwm signal for motor controller channel x. the pins associated with pwm channel x are mnc0p and mnc0m. similarly, duty cycle register x + 1 controls the sign of the pwm signal and the duty cycle of the pwm signal for channel x + 1. the pins associated with pwm channel x + 1 are mnc1p and mnc1m. this is summarized in table 11-11 . table 11-11. corresponding registers and pin names for each pwm channel pair pwm channel pair number pwm channel control register duty cycle register channel number pin names n mcmcx mcdcx pwm channel x, x = 2 ? n mnc0m mnc0p mcmcx+1 mcdcx+1 pwm channel x+1, x = 2 ? n mnc1m mnc1p 0 mcmc0 mcdc0 pwm channel 0 m0c0m m0c0p mcmc1 mcdc1 pwm channel 1 m0c1m m0c1p 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 457 11.4.1.1.1 dual full h-bridge mode (mcom = 11) pwm channel pairs x and x + 1 operate in dual full h-bridge mode if both channels have been enabled (mcam[1:0]=01, 10, or 11) and both of the corresponding output mode bits mcom[1:0] in both pwm channel control registers are set. a typical con?uration in dual full h-bridge mode is shown in figure 11-10 . pwm channel x drives the pwm output signal on either mnc0p or mnc0m. if mnc0p drives the pwm signal, mnc0m will be output either high or low depending on the recirc bit. if mnc0m drives the pwm signal, mnc0p will be an output high or low. pwm channel x + 1 drives the pwm output signal on either mnc1p or mnc1m. if mnc1p drives the pwm signal, mnc1m will be an output high or low. if mnc1m drives the pwm signal, mnc1p will be an output high or low. this results in motor recirculation currents on the high side drivers (recirc = 0) while the pwm signal is at a logic high level, or motor recirculation currents on the low side drivers (recirc = 1) while the pwm signal is at a logic low level. the pin driving the pwm signal is determined by the s (sign) bit in the corresponding duty cycle register and the state of the recirc bit. the value of the pwm duty cycle is determined by the value of the d[10:0] or d[8:2] bits respectively in the duty cycle register depending on the state of the fast bit. 1 mcmc2 mcdc2 pwm channel 2 m1c0m m1c0p mcmc3 mcdc3 pwm channel 3 m1c1m m1c1p 2 mcmc4 mcdc4 pwm channel 4 m2c0m m2c0p mcmc5 mcdc5 pwm channel 5 m2c1m m2c1p 3 mcmc6 mcdc6 pwm channel 6 m3c0m m3c0p mcmc7 mcdc7 pwm channel 7 m3c1m m3c1p 4 mcmc8 mcdc8 pwm channel 8 m4c0m m4c0p mcmc9 mcdc9 pwm channel 9 m4c1m m4c1p 5 mcmc10 mcdc10 pwm channel 10 m5c0m m5c0p mcmc11 mcdc11 pwm channel 11 m5c1m m5c1p table 11-11. corresponding registers and pin names for each pwm channel pair pwm channel pair number pwm channel control register duty cycle register channel number pin names 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 458 freescale semiconductor figure 11-10. typical dual full h-bridge mode con?uration whenever fast = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable duty cycles. while fast mode is enabled (fast = 1), 8-bit write accesses to the high byte of the duty cycle registers are allowed, because only the high byte of the duty cycle register is used to determine the duty cycle. the following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent pwm output: 1. write to duty cycle register x 2. write to duty cycle register x + 1. at the next timer counter over?w, the duty cycle registers will be copied to the working duty cycle registers. sequential writes to the duty cycle register x will result in the previous data being overwritten. 11.4.1.1.2 full h-bridge mode (mcom = 10) in full h-bridge mode, the pwm channels x and x + 1 operate independently. the duty cycle working registers are updated whenever a timer counter over?w occurs. 11.4.1.1.3 half h-bridge mode (mcom = 00 or 01) in half h-bridge mode, the pwm channels x and x + 1 operate independently. in this mode, each pwm channel can be con?ured such that one pin is released and the other pin is a pwm output. figure 11-11 shows a typical con?uration in half h-bridge mode. the two pins associated with each channel are switchable between released mode and pwm output dependent upon the state of the mcom[1:0] bits in the mcccx (channel control) register. see register description in section 11.3.2.4, ?otor controller channel control registers . in half h-bridge mode, the state of the s bit has no effect. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m motor n, coil 0 motor n, coil 1 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 459 figure 11-11. typical quad half h-bridge mode con?uration 11.4.1.2 relationship between pwm mode and pwm channel enable the pair of motor controller channels cannot be placed into dual full h-bridge mode unless both motor controller channels have been enabled (mcam[1:0] not equal to 00) and dual full h-bridge mode is selected for both pwm channels (mcom[1:0] = 11). if only one channel is set to dual full h-bridge mode, this channel will operate in full h-bridge mode, the other as programmed. 11.4.1.3 relationship between sign, duty, dither, recirc, period, and pwm mode functions 11.4.1.3.1 pwm alignment modes each pwm channel can be programmed individually to three different alignment modes. the mode is determined by the mcam[1:0] bits in the corresponding channel control register. left aligned (mcam[1:0] = 01): the output will start active (low if recirc = 0 or high if recirc = 1) and will turn inactive (high if recirc = 0 or low if recirc = 1) after the number of counts speci?d by the corresponding duty cycle register. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m released pwm output v ssm v ddm v ssm v ddm released pwm output 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 460 freescale semiconductor right aligned (mcam[1:0] = 10): the output will start inactive (high if recirc = 0 and low if recirc = 1) and will turn active after the number of counts speci?d by the difference of the contents of period register and the corresponding duty cycle register. center aligned (mcam[1:0] = 11): even periods will be output left aligned, odd periods will be output right aligned. pwm operation starts with the even period after the channel has been enabled. pwm operation in center aligned mode might start with the odd period if the channel has not been disabled before changing the alignment mode to center aligned. 0 15 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 dith = 0, mcam[1:0] = 01, mcdcx = 15, mcper = 100, recirc = 0 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 85 99 99 dith = 0, mcam[1:0] = 10, mcdcx = 15, mcper = 100, recirc = 0 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 dith = 0, mcam[1:0] = 11, mcdcx = 15, mcper = 100, recirc = 0 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 461 11.4.1.3.2 sign bit (s) assuming recirc = 0 (the active state of the pwm signal is low), when the s bit for the corresponding channel is cleared, mnc0p (if the pwm channel number is even, n = 0, 1, 2...5, see table 11-11 ) or mnc1p (if the pwm channel number is odd, ,n = 0, 1, 2...5 see table 11-11 ), outputs a logic high while in (dual) full h-bridge mode. in half h-bridge mode the state of the s bit has no effect. the pwm output signal is generated on mnc0m (if the pwm channel number is even, n = 0, 1, 2...5, see table 11-11 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2...5). assuming recirc = 0 (the active state of the pwm signal is low), when the s bit for the corresponding channel is set, mnc0m (if the pwm channel number is even, n = 0, 1, 2...5, see table 11-11 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2...5, see table 11-11 ), outputs a logic high while in (dual) full h-bridge mode. in half h-bridge mode the state of the s bit has no effect. the pwm output signal is generated on mnc0p (if the pwm channel number is even, n = 0, 1, 2...5, see table 11-11 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2...5). setting recirc = 1 will also invert the effect of the s bit such that while s = 0, mnc0p or mnc1p will generate the pwm signal and mnc0m or mnc1m will be a static low output. while s = 1, mnc0m or mnc1m will generate the pwm signal and mnc0p or mnc1p will be a static low output. in this case the active state of the pwm signal will be high. see table 11-12 for detailed information about the impact of sign and recirc bit on the pwm output. 11.4.1.3.3 recirc bit the recirc bit controls the ?w of the recirculation current of the load. setting recirc = 0 will cause recirculation current to ?w through the high side transistors, and recirc = 1 will cause the recirculation current to ?w through the low side transistors. the recirc bit is only active in (dual) full h-bridge modes. effectively, recirc = 0 will cause a static high output on the output terminal not driven by the pwm, recirc = 1 will cause a static low output on the output terminals not driven by the pwm. to achieve the same current direction, the s bit behavior is inverted if recirc = 1. figure 11-12 , figure 11-13 , figure 11-14 , and figure 11-15 illustrate the effect of the recirc bit in (dual) full h-bridge modes. table 11-12. impact of recirc and sign bit on the pwm output output mode recirc sign mncym mncyp (dual) full h-bridge 0 0 pwm 1 1 pwm: the pwm signal is low active. e.g., the waveform starts with 0 in left aligned mode. output m generates the pwm signal. output p is static high. 1 (dual) full h-bridge 0 1 1 pwm (dual) full h-bridge 1 0 0 pwm 2 2 pwm: the pwm signal is high active. e.g., the waveform starts with 1 in left aligned mode. output p generates the pwm signal. output m is static low. (dual) full h-bridge 1 1 pwm 1 half h-bridge: pwm on mncym don? care don? care pwm 3 3 the state of the output transistors is not controlled by the motor controller. half h-bridge: pwm on mncyp don? care don? care pwm 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 462 freescale semiconductor recirc bit must be changed only while no pwm channel is operated in (dual) full h-bridge mode. figure 11-12. pwm active phase, recirc = 0, s = 0 figure 11-13. pwm passive phase, recirc = 0, s = 0 v ddm v ssm mnc0p mnc0m static 0 pwm 1 pwm 1 static 0 v ddm v ssm mnc0p mnc0m static 0 pwm 0 static 0 pwm 0 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 463 figure 11-14. pwm active phase, recirc = 1, s = 0 figure 11-15. pwm passive phase, recirc = 1, s = 0 v ssm mnc0p mnc0m v ddm static 1 static 1 pwm 0 pwm 0 v ddm v ssm mnc0p mnc0m static 1 static 1 pwm 1 pwm 1 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 464 freescale semiconductor 11.4.1.3.4 relationship between recirc bit, s bit, mcom bits, pwm state, and output transistors please refer to figure 11-16 for the output transistor assignment. figure 11-16. output transistor assignment table 11-13 illustrates the state of the output transistors in different states of the pwm motor controller module. ?means that the state of the output transistor is not controlled by the motor controller. table 11-13. state of output transistors in various modes mode mcom[1:0] pwm duty recirc s t1 t2 t3 t4 off don? care don? care don? care half h-bridge 00 active don? care don? care off on half h-bridge 00 passive don? care don? care on off half h-bridge 01 active don? care don? care off on half h-bridge 01 passive don? care don? care on off (dual) full 10 or 11 active 0 0 on off off on (dual) full 10 or 11 passive 0 0 on off on off (dual) full 10 or 11 active 0 1 off on on off (dual) full 10 or 11 passive 0 1 on off on off (dual) full 10 or 11 active 1 0 on off off on (dual) full 10 or 11 passive 1 0 off on off on (dual) full 10 or 11 active 1 1 off on on off (dual) full 10 or 11 passive 1 1 off on off on v ddm v ssm mncyp mncym t1 t2 t3 t4 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 465 11.4.1.3.5 dither bit (dith) the purpose of the dither mode is to increase the minimum length of output pulses without decreasing the pwm resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. if dither mode is selected the output pattern will repeat after two timer counter over?ws. for the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. to achieve the same output frame frequency, the prescaler of the mc10b12c module has to be set to twice the division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. the dith bit in control register 0 enables or disables the dither function. dith = 0: dither function is disabled. when dith is cleared and assuming left aligned operation and recirc = 0, the pwm output will start at a logic low level at the beginning of the pwm period (motor controller timer counter = 0x000). the pwm output remains low until the motor controller timer counter matches the 11-bit pwm duty cycle value, duty, contained in d[10:0] in mcdcx. when a match (output compare between motor controller timer counter and duty) occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter over?ws (reaches the contents of mcper ?1). after the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this completes one pwm period. the pwm period repeats every p counts (as de?ed by the bits p[10:0] in the motor controller period register) of the motor controller timer counter. if duty >= p, the output will be static low. if duty = 0x0000, the output will be continuously at a logic high level. the relationship between the motor controller timer counter clock, motor controller timer counter value, and pwm output while dith = 0 is shown in figure 11-17 . figure 11-17. pwm output: dith = 0, mcam[1:0] = 01, mcdc = 100, mcper = 200, recirc = 0 dith = 1: dither function is enabled please note if dith = 1, the bit p0 in the motor controller period register will be internally forced to 0 and read always as 0. when dith is set and assuming left aligned operation and recirc = 0, the pwm output will start at a logic low level at the beginning of the pwm period (when the motor controller timer counter = 0x000). the pwm output remains low until the motor controller timer counter matches the 10-bit pwm duty cycle 0 100 0 100 0 pwm output 1 period 200 counts 200 counts 1 period motor controller timer counter clock motor controller timer counter 199 199 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 466 freescale semiconductor value, duty, contained in d[10:1] in mcdcx. when a match (output compare between motor controller timer counter and duty) occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter over?ws (reaches the value de?ed by p[10:1] 1 in mcper). after the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this completes the ?st half of the pwm period. during the second half of the pwm period, the pwm output will remain at a logic low level until either the motor controller timer counter matches the 10-bit pwm duty cycle value, duty, contained in d[10:1] in mcdcx if d0 = 0, or the motor controller timer counter matches the 10-bit pwm duty cycle value + 1 (the value of d[10:1] in mcdcx is increment by 1 and is compared with the motor controller timer counter value) if d0 = 1 in the corresponding duty cycle register. when a match occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter over?ws (reaches the value de?ed by p[10:1] ?1 in mcper). after the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this process will repeat every number of counts of the motor controller timer counter de?ed by the period register contents (p[10:0]). if the output is neither set to 0% nor to 100% there will be four edges on the pwm output per pwm period in this case. therefore, the pwm output compare function will alternate between duty and duty + 1 every half pwm period if d0 in the corresponding duty cycle register is set to 1. the relationship between the motor controller timer counter clock (f tc ), motor controller timer counter value, and left aligned pwm output if dith = 1 is shown in figure 11-18 and figure 11-19 . figure 11-20 and figure 11-21 show right aligned and center aligned pwm operation respectively, with dither feature enabled and d0 = 1. please note: in the following examples, the mcper value is de?ed by the bits p[10:0], which is, if dith = 1, always an even number. note the dith bit must be changed only if the motor controller is disabled (all channels disabled or period register cleared) to avoid erroneous waveforms. figure 11-18. pwm output: dith = 1, mcam[1:0] = 01, mcdc = 31, mcper = 200, recirc = 0 0 15 pwm output 16 0 100 counts motor controller timer counter motor controller timer counter clock 0 16 1 period 100 counts 15 99 99 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 467 figure 11-19. pwm output: dith = 1, mcam[1:0] = 01, mcdc = 30, mcper = 200, recirc = 0 . figure 11-20. pwm output: dith = 1, mcam[1:0] = 10, mcdc = 31, mcper = 200, recirc = 0 figure 11-21. pwm output: dith = 1, mcam[1:0] = 11, mcdc = 31, mcper = 200, recirc = 0 pwm output 1 period 100 counts motor controller timer counter motor controller timer counter clock 100 counts 015 16 0 0 16 15 99 99 0 84 pwm output 85 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 85 100 counts 84 99 99 0 84 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 100 counts 15 99 99 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 468 freescale semiconductor 11.4.2 pwm duty cycle the pwm duty cycle for the motor controller channel x can be determined by dividing the decimal representation of bits d[10:0] in mcdcx by the decimal representation of the bits p[10:0] in mcper and multiplying the result by 100% as shown in the equation below: note x = pwm channel number = 0, 1, 2, 3 ... 11. this equation is only valid if duty <= mcper and mcper is not equal to 0. whenever d[10:0] >= p[10:0], a constant low level (recirc = 0) or high level (recirc = 1) will be output. 11.4.3 motor controller counter clock source figure 11-22 shows how the pwm motor controller timer counter clock source is selected. figure 11-22. motor controller counter clock selection the peripheral bus clock is the source for the motor controller counter prescaler. the motor controller counter clock rate, f tc , is set by selecting the appropriate prescaler value. the prescaler is selected with the mcpre[1:0] bits in motor controller control register 0 (mcctl0). the motor controller channel frequency of operation can be calculated using the following formula if dith = 0: effective pwm channel x % duty cycle duty mcper --------------------- 100% ? = 1 1/2 1/4 1/8 motor controller timer counter prescaler motor controller timer counter clock prescaler select mppre0, mppre1 11-bit motor controller timer counter peripheral bus clock f bus clock generator clk clocks and reset generator module motor controller timer counter clock f tc motor channel frequency (hz) f tc mcper m ? ------------------------------- = 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 469 the motor controller channel frequency of operation can be calculated using the following formula if dith = 1: note both equations are only valid if mcper is not equal to 0. m = 1 for left or right aligned mode, m = 2 for center aligned mode. table 11-14 shows examples of the motor controller channel frequencies that can be generated based on different peripheral bus clock frequencies and the prescaler value. note due to the selectable slew rate control of the outputs, clipping may occur on short output pulses. 11.4.4 output switching delay in order to prevent large peak current draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level transitions on the motor controller outputs. the timing delay, t d , is determined by the cd[1:0] bits in the corresponding channel control register (mcmcx) and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. note a pwm channel gets disabled at the next timer counter over?w without notice of the switching delay. table 11-14. motor controller channel frequencies (hz), mcper = 256, dith = 0, mcam = 10, 01 prescaler peripheral bus clock frequency 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz 1 62500 39063 31250 19531 15625 1/2 31250 19531 15625 9766 7813 1/4 15625 9766 7813 4883 3906 1/8 7813 4883 3906 2441 1953 motor channel frequency (hz) f tc mcper m 2 ? ? -------------------------------------- = 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 470 freescale semiconductor 11.4.5 operation in wait mode during wait mode, the operation of the motor controller pins are selectable between the following two options: 1. mcswai = 1: all module clocks are stopped and the associated port pins are set to their inactive state, which is de?ed by the state of the recirc bit during wait mode. the motor controller module registers stay the same as they were prior to entering wait mode. therefore, after exiting from wait mode, the associated port pins will resume to the same functionality they had prior to entering wait mode. 2. mcswai = 0: the pwm clocks continue to run and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 11.4.6 operation in stop and pseudo-stop modes all module clocks are stopped and the associated port pins are set to their inactive state, which is de?ed by the state of the recirc bit. the motor controller module registers stay the same as they were prior to entering stop or pseudo-stop modes. therefore, after exiting from stop or pseudo-stop modes, the associated port pins will resume to the same functionality they had prior to entering stop or pseudo-stop modes. 11.5 reset the motor controller is reset by system reset. all associated ports are released, all registers of the motor controller module will switch to their reset state as de?ed in section 11.3.2, ?egister descriptions . 11.6 interrupts the motor controller has one interrupt source. 11.6.1 timer counter over?w interrupt an interrupt will be requested when the mctoie bit in the motor controller control register 1 is set and the running pwm frame is ?ished. the interrupt is cleared by either setting the mctoie bit to 0 or to write a 1 to the mctoif bit in the motor controller control register 0. 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 471 11.7 initialization/application information this section provides an example of how the pwm motor controller can be initialized and used by application software. the con?uration parameters (e.g., timer settings, duty cycle values, etc.) are not guaranteed to be adequate for any real application. the example software is implemented in assembly language. 11.7.1 code example one way to use the motor controller is: 1. perform global initialization a) set the motor controller control registers mcctl0 and mcctl1 to appropriate values. i) prescaler disabled (mcpre1 = 0, mcpre0 = 0). ii) fast mode and dither disabled (fast = 0, dith = 0). iii) recirculation feature in dual full h-bridge mode disabled (recirc = 0). all other bits in mcctl0 and mcctl1 are set to 0. b) con?ure the channel control registers for the desired mode. i) dual full h-bridge mode (mcom[1:0] = 11). ii) left aligned pwm (mcam[1:0] = 01). iii) no channel delay (mccd[1:0] = 00). 2. perform the startup phase a) clear the duty cycle registers mcdc0 and mcdc1 b) initialize the period register mcper, which is equivalent to enabling the motor controller. c) enable the timer which generates the timebase for the updates of the duty cycle registers. 3. main program a) check if pin pb0 is set to ??and execute the sub program if a timer interrupt is pending. b) initiate the shutdown procedure if pin pb0 is set to ?? 4. sub program a) update the duty cycle registers load the duty cycle registers mcdc0 and mcdc1 with new values from the table and clear the timer interrupt ?g. the sub program will initiate the shutdown procedure if pin pb0 is set to ?? b) shutdown procedure the timer is disabled and the duty cycle registers are cleared to drive an inactive value on the pwm output as long as the motor controller is enabled. the period register is cleared after a certain time, which disables the motor controller. the table address is restored and the timer interrupt ?g is cleared. 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 472 freescale semiconductor ;------------------------------------------------------------------------------------------ ; motor controller (mc10b8c) setup example ;------------------------------------------------------------------------------------------ ; timer defines ;------------------------------------------------------------------------------------------ t_start equ $0040 tscr1 equ t_start+$06 tflg2 equ t_start+$0f ;------------------------------------------------------------------------------------------ ; motor controller defines ;------------------------------------------------------------------------------------------ mc_start equ $0200 mcctl0 equ mc_start+$00 mcctl1 equ mc_start+$01 mcper_hi equ mc_start+$02 mcper_lo equ mc_start+$03 mccc0 equ mc_start+$10 mccc1 equ mc_start+$11 mccc2 equ mc_start+$12 mccc3 equ mc_start+$13 mcdc0_hi equ mc_start+$20 mcdc0_lo equ mc_start+$21 mcdc1_hi equ mc_start+$22 mcdc1_lo equ mc_start+$23 mcdc2_hi equ mc_start+$24 mcdc2_lo equ mc_start+$25 mcdc3_hi equ mc_start+$26 mcdc3_lo equ mc_start+$27 ;------------------------------------------------------------------------------------------ ; port defines ;------------------------------------------------------------------------------------------ ddrb equ $0003 portb equ $0001 ;------------------------------------------------------------------------------------------ ; flash defines ;------------------------------------------------------------------------------------------ flash_start equ $0100 fcmd equ flash_start+$06 fclkdiv equ flash_start+$00 fstat equ flash_start+$05 ftstmod equ flash_start+$02 ; variables code_start equ $1000 ; start of program code dtydat equ $1500 ; start of motor controller duty cycle data temp_x equ $1700 ; save location for ix reg in isr tablesize equ $1704 ; number of config entries in the table mcperiod equ $0250 ; motor controller period ;------------------------------------------------------------------------------------------ ;------------------------------------------------------------------------------------------ org code_start ; start of code lds #$1fff ; set stack pointer movw #$000a,tablesize ; number of configurations in the table movw tablesize,temp_x 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 473 ;------------------------------------------------------------------------------------------ ;global motor controller init ;------------------------------------------------------------------------------------------ glb_init: movb #$0000,mcctl0 ; fmc = fbus, fast=0, dith=0 movb #$0000,mcctl1 ; recirc=0, mctoie=0 movw #$d0d0,mccc0 ; dual full h-bridge mode, left aligned, ; no channel delay movw #$0000,mcper_hi ; disable motor controller ;------------------------------------------------------------------------------------------ ;motor controller startup ;------------------------------------------------------------------------------------------ startup: movw #$0000,mcdc0_hi ; define startup duty cycles movw #$0000,mcdc1_hi movw #mcperiod,mcper_hi ; define pwm period movb #$80,tscr1 ; enable timer main: ldaa portb ; if pb=0, activate shutdown anda #$01 beq mn0 jsr tim_sr mn0: tst tflg2 ; poll for timer counter overflow flag beq main ; tof set? jsr tim_sr ; yes, go to tim_sr bra main tim_sr: ldx temp_x ; restore index register x ldaa portb ; if pb=0, enter shutdown routine anda #$01 bne shutdown ldx temp_x ; restore index register x beq new_seq ; all mc configurations done? new_cfg: ldd dtydat,x ; load new config? std mcdc0_hi dex dex ldd dtydat,x std mcdc1_hi bra end_sr ; leave sub-routine shutdown: movb #$00,tscr1 ; disable timer movw #$0000,mcdc0_hi ; define startup duty cycle movw #$0000,mcdc1_hi ; define startup duty cycle ldaa #$0000 ; ensure that duty cycle registers are ; cleared for some time before disabling ; the motor controller loop deca bne loop movw #$0000,mcper_hi ; define pwm period new_seq: movw tablesize,temp_x ; start new tx loop ldx temp_x end_sr: stx temp_x ; save byte counter movb #$80,tflg2 ; clear tof rts ; wait for new timer overflow 4 .com u datasheet
chapter 11 motor controller (mc10b12cv2) MC9S12XHZ512 data sheet, rev. 1.02 474 freescale semiconductor ;------------------------------------------------------------------------------------------ ; motor controller duty cycles ;------------------------------------------------------------------------------------------ org dtydat dc.b $02, $ff 1 ; mcdc1_hi, mcdc1_lo dc.b $02, $d0 ; mcdc0_hi, mcdc0_lo dc.b $02, $a0 ; mcdc1_hi, mcdc1_lo dc.b $02, $90 ; mcdc0_hi, mcdc0_lo dc.b $02, $60 ; mcdc1_hi, mcdc1_lo dc.b $02, $25 ; mcdc0_hi, mcdc0_lo 1. the values for the duty cycle table have to be de?ed for the needs of the target application. 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 475 chapter 12 stepper stall detector (ssdv1) 12.1 introduction the stepper stall detector (ssd) block provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (rtz). during the rtz event, the pointer is returned to zero using full steps in either clockwise or counter clockwise direction, where only one coil is driven at any point in time. the back electromotive force (emf) signal present on the non-driven coil is integrated after a blanking time, and its results stored in a 16-bit accumulator. the 16-bit modulus down counter can be used to monitor the blanking time and the integration time. the value in the accumulator represents the change in linked ?x (magnetic ?x times the number of turns in the coil) and can be compared to a stored threshold. values above the threshold indicate a moving motor, in which case the pointer can be advanced another full step in the same direction and integration be repeated. values below the threshold indicate a stalled motor, thereby marking the cessation of the rtz event. the ssd is capable of multiplexing two stepper motors. 12.1.1 modes of operation return to zero modes blanking with no drive blanking with drive conversion integration low-power modes 12.1.2 features programmable full step state programmable integration polarity blanking (recirculation) state 16-bit integration accumulator register 16-bit modulus down counter with interrupt multiplex two stepper motors 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 476 freescale semiconductor 12.1.3 block diagram figure 12-1. ssd block diagram coil sinx coil cosx bus clock vddm cosxp cosxm t1 t2 t3 vssm 1/2 1/2 1/2 1/32 4:1 mux vddm t4 vssm s1 s3 s2 s4 vddm sinxp sinxm t5 t6 t7 vssm vddm t8 vssm s5 s7 s6 s8 16-bit accumulator register vddm vssm r2 r2 dff 16-bit modulus down counter r1 c1 + + 16-bit load register sigma-delta converter p a d p a d p a d p a d integrator reference 1/2 2:1 mux x = a or b dac (analog) 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 477 12.2 external signal description each ssd signal is the output pin of a half bridge, designed to source or sink current. the h-bridge pins drive the sine and cosine coils of a stepper motor to provide four-quadrant operation. the ssd is capable of multiplexing between stepper motor a and stepper motor b if two motors are connected. 12.2.1 cosxm/cosxp ?cosine coil pins for motor x these pins interface to the cosine coils of a stepper motor to measure the back emf for calibration of the pointer reset position. 12.2.2 sinxm/sinxp ?sine coil pins for motor x these pins interface to the sine coils of a stepper motor to measure the back emf for calibration of the pointer reset position. table 12-1. pin table 1 1 x = a or b indicating motor a or motor b pin name node coil cosxm minus cosx cosxp plus sinxm minus sinx sinxp plus 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 478 freescale semiconductor 12.3 memory map and register de?ition this section provides a detailed description of all registers of the stepper stall detector (ssd) block. 12.3.1 module memory map table 12-2 gives an overview of all registers in the ssdv1 memory map. the ssdv1 occupies eight bytes in the memory space. the register address results from the addition of base address and address offset. the base address is determined at the mcu level and is given in the device overview chapter. the address offset is de?ed at the block level and is given here. 12.3.2 register descriptions this section describes in detail all the registers and register bits in the ssdv1 block. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. table 12-2. ssdv1 memory map address offset use access 0x0000 rtzctl r/w 0x0001 mdcctl r/w 0x0002 ssdctl r/w 0x0003 ssdflg r/w 0x0004 mdccnt (high) r/w 0x0005 mdccnt (low) r/w 0x0006 itgacc (high) r 0x0007 itgacc (low) r 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 479 12.3.2.1 return-to-zero control register (rtzctl) read: anytime write: anytime 76543210 r itg dcoil rcir pol 0 sms step w reset 0 0 0 00000 = unimplemented or reserved figure 12-2. return-to-zero control register (rtzctl) table 12-3. rtzctl field descriptions field description 7 itg integration during return to zero (rtze = 1), one of the coils must be recirculated or non-driven determined by the step ?ld. if the itg bit is set, the coil is non-driven, and if the itg bit is clear, the coil is being recirculated. table 12-4 shows the condition state of each transistor from figure 12-1 based on the step, itg, dcoil and rcir bits. regardless of the rtze bit value, if the itg bit is set, one end of the non-driven coil connects to the (non-zero) reference input and the other end connects to the integrator input of the sigma-delta converter. regardless of the rtze bit value, if the itg bit is clear, the non-driven coil is in a blanking state, the converter is in a reset state, and the accumulator is initialized to zero. table 12-5 shows the condition state of each switch from figure 12-1 based on the itg, step and pol bits. 0 blanking 1 integration 6 dcoil drive coil ?during return to zero (rtze=1), one of the coils must be driven determined by the step ?ld. if the dcoil bit is set, this coil is driven. if the dcoil bit is clear, this coil is disconnected or drivers turned off. table 12-4 shows the condition state of each transistor from figure 12-1 based on the step, itg, dcoil and rcir bits. 0 disconnect coil 1 drive coil 5 rcir recirculation in blanking mode ?during return to zero (rtze = 1), one of the coils is recirculated prior to integration during the blanking period. this bit determines if the coil is recirculated via vddm or via vssm. table 12-4 shows the condition state of each transistor from figure 12-1 based on the step, itg, dcoil and rcir bits. 0 recirculation on the high side transistors 1 recirculation on the low side transistors 4 pol polarity ?this bit determines which end of the non-driven coil is routed to the sigma-delta converter during conversion or integration mode. table 12-5 shows the condition state of each switch from figure 12-1 based on the itg, step and pol bits. 2 sms stepper motor select this bit selects one of two possible stepper motors to be used for stall detection. see top level chip description for the stepper motor assignments to the ssd. 0 stepper motor a is selected for stall detection 1 stepper motor b is selected for stall detection 1:0 step full step state this ?ld indicates one of the four possible full step states. step 0 is considered the east pole or 0 angle, step 1 is the north pole or 90 angle, step 2 is the west pole or 180 angle, and step 3 is the south pole or 270 angle. for each full step state, table 12-6 shows the current through each of the two coils, and the coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode. 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 480 freescale semiconductor table 12-4. transistor condition states (rtze = 1) step itg dcoil rcir t1 t2 t3 t4 t5 t6 t7 t8 xx 1 0 x off off off off off off off off 00 0 0 0 off off off off on off on off 00 0 0 1 off off off off off on off on 00 0 1 0 on off off on on off on off 00 0 1 1 on off off on off on off on 00 1 1 x on off off on off off off off 01 0 0 0 on off on off off off off off 01 0 0 1 off on off on off off off off 01 0 1 0 on off on off on off off on 01 0 1 1 off on off on on off off on 01 1 1 x off off off off on off off on 10 0 0 0 off off off off on off on off 10 0 0 1 off off off off off on off on 10 0 1 0 off on on off on off on off 10 0 1 1 off on on off off on off on 10 1 1 x off on on off off off off off 11 0 0 0 on off on off off off off off 11 0 0 1 off on off on off off off off 11 0 1 0 on off on off off on on off 11 0 1 1 off on off on off on on off 11 1 1 x off off off off off on on off table 12-5. switch condition states (rtze = 1 or 0) itg step pol s1 s2 s3 s4 s5 s6 s7 s8 0 xx x open open open open open open open open 1 00 0 open open open open close open open close 1 00 1 open open open open open close close open 1 01 0 open close close open open open open open 1 01 1 close open open close open open open open 1 10 0 open open open open open close close open 1 10 1 open open open open close open open close 1 11 0 close open open close open open open open 1 11 1 open close close open open open open open 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 481 12.3.2.2 modulus down counter control register (mdcctl) read: anytime write: anytime. l table 12-6. full step states step pole angle cosine coil current sine coil current coil node to integrator input (close switch) coil node to reference input (close switch) dcoil = 0 dcoil = 1 dcoil = 0 dcoil = 1 itg = 1 pol = 0 itg = 1 pol = 1 itg = 1 pol = 0 itg = 1 pol = 1 0 east 0 0 + i max 0 0 sinxm (s8) sinxp (s6) sinxp (s5) sinxm (s7) 1 north 90 0 0 0 + i max cosxp (s2) cosxm (s4) cosxm (s3) cosxp (s1) 2 west 180 0 i max 0 0 sinxp (s6) sinxm (s8) sinxm (s7) sinxp (s5) 3 south 270 0 0 0 i max cosxm (s4) cosxp (s2) cosxp (s1) cosxm (s3) 76543210 r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc reset 0 0 0 00000 = unimplemented or reserved figure 12-3. modulus down counter control register (mdcctl) table 12-7. mdcctl field descriptions field description 7 mczie modulus counter under?w interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the modulus counter under?w interrupt ?g (mczif) is set. 6 modmc modulus mode enable 0 the modulus counter counts down from the value in the counter register and will stop at 0x0000. 1 modulus mode is enabled. when the counter reaches 0x0000, the counter is loaded with the latest value written to the modulus counter register. note: for proper operation, the mcen bit should be cleared before modifying the modmc bit in order to reset the modulus counter to 0xffff. 5 rdmcl read modulus down-counter load 0 reads of the modulus count register (mdccnt) will return the present value of the count register. 1 reads of the modulus count register (mdccnt) will return the contents of the load register. 4 pre prescaler 0 the modulus down counter clock frequency is the bus frequency divided by 64. 1 the modulus down counter clock frequency is the bus frequency divided by 512. note: a change in the prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 482 freescale semiconductor 12.3.2.3 stepper stall detector control register (ssdctl) read: anytime write: anytime l 3 flmc force load register into the modulus counter count register ?this bit always reads zero. 0 write zero to this bit has no effect. 1 write one into this bit loads the load register into the modulus counter count register. 2 mcen modulus down-counter enable 0 modulus down-counter is disabled. the modulus counter (mdccnt) is preset to 0xffff. this will prevent an early interrupt ?g when the modulus down-counter is enabled. 1 modulus down-counter is enabled. 0 aovie accumulator over?w interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the accumulator over?w interrupt ?g (aovif) is set. 76543210 r rtze sdcpu ssdwai ftst 00 aclks w reset 0 0 0 00000 = unimplemented or reserved figure 12-4. stepper stall detector control register (ssdctl) table 12-8. ssdctl field descriptions field description 7 rtze return to zero enable if this bit is set, the coils are controlled by the ssd and are con?ured into one of the four full step states as shown in table 12-6 . if this bit is cleared, the coils are not controlled by the ssd. 0 rtz is disabled. 1 rtz is enabled. 6 sdcpu sigma-delta converter power up ?this bit provides on/off control for the sigma-delta converter allowing reduced mcu power consumption. because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after it is powered up. 0 sigma-delta converter is powered down. 1 sigma-delta converter is powered up. 5 ssdwai ssd disabled during wait mode ?when entering wait mode, this bit provides on/off control over the ssd allowing reduced mcu power consumption. because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after exit from wait mode. 0 ssd continues to run in wait mode. 1 entering wait mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and if rtze bit is set, the sine and cosine coils are recirculated via vssm. table 12-7. mdcctl field descriptions (continued) field description 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 483 note a change in the accumulator sample frequency will not be effective until the itg bit is cleared. 12.3.2.4 stepper stall detector flag register (ssdflg) read: anytime write: anytime. l 4 ftst factory test ?this bit is reserved for factory test and reads zero in user mode. 1:0 aclks accumulator sample frequency select ?this ?ld sets the accumulator sample frequency by pre-scaling the bus frequency by a factor of 8, 16, 32, or 64. a faster sample frequency can provide more accurate results but cause the accumulator to over?w. best results are achieved with a frequency between 500 khz and 2 mhz. accumulator sample frequency = f bus / (8 x 2 aclks ) table 12-9. accumulator sample frequency aclks frequency f bus = 40 mhz f bus = 25 mhz f bus = 16 mhz 0f bus / 8 5.00 mhz 3.12 mhz 2.00 mhz 1f bus / 16 2.50 mhz 1.56 mhz 1.00 mhz 2f bus / 32 1.25 mhz 781 khz 500 khz 3f bus / 64 625 khz 391 khz 250 khz 76543210 r mczif 000000 aovif w reset 0 0 0 00000 = unimplemented or reserved figure 12-5. stepper stall detector flag register (ssdflg) table 12-10. ssdflg field descriptions field description 7 mczif modulus counter under?w interrupt flag ?this ?g is set when the modulus down-counter reaches 0x0000. if not masked (mczie = 1), a modulus counter under?w interrupt is pending while this ?g is set. this ?g is cleared by writing a ??to the bit. a write of ??has no effect. 0 aovif accumulator over?w interrupt flag ?this ?g is set when the integration accumulator has a positive or negative over?w. if not masked (aovie = 1), an accumulator over?w interrupt is pending while this ?g is set. this ?g is cleared by writing a ??to the bit. a write of ??has no effect. table 12-8. ssdctl field descriptions (continued) field description 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 484 freescale semiconductor 12.3.2.5 modulus down-counter count register (mdccnt) read: anytime write: anytime. note a separate read/write for high byte and low byte gives a different result than accessing the register as a word. if the rdmcl bit in the mdcctl register is cleared, reads of the mdccnt register will return the present value of the count register. if the rdmcl bit is set, reads of the mdccnt register will return the contents of the load register. with a 0x0000 write to the mdccnt register, the modulus counter stays at zero and does not set the mczif ?g in the ssdflg register. if modulus mode is not enabled (modmc = 0), a write to the mdccnt register immediately updates the load register and the counter register with the value written to it. the modulus counter will count down from this value and will stop at 0x0000. if modulus mode is enabled (modmc = 1), a write to the mdccnt register updates the load register with the value written to it. the count register will not be updated with the new value until the next counter under?w. the flmc bit in the mdcctl register can be used to immediately update the count register with the new value if an immediate load is desired. the modulus down counter clock frequency is the bus frequency divided by 64 or 512. 15 14 13 12 11 10 9 8 r mdccnt w reset 1 1 1 11111 figure 12-6. modulus down-counter count register high (mdccnt) 76543210 r mdccnt w reset 1 1 1 11111 figure 12-7. modulus down-counter count register low (mdccnt) 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 485 12.3.2.6 integration accumulator register (itgacc) read: anytime. write: never. note a separate read for high byte and low byte gives a different result than accessing the register as a word. this 16-bit ?ld is signed and is represented in twos complement. it indicates the change in ?x while integrating the back emf present in the non-driven coil during a return to zero event. when itg is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state. when itg is one, the accumulator increments or decrements depending on the sigma-delta conversion sample. the accumulator sample frequency is determined by the aclks ?ld. the accumulator freezes at 0x7fff on a positive over?w and freezes at 0x8000 on a negative over?w. 12.4 functional description the stepper stall detector (ssd) has a simple control block to con?ure the h-bridge drivers of a stepper motor in four different full step states with four available modes during a return to zero event. the ssd has a detect circuit using a sigma-delta converter to measure and integrate changes in ?x of the de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed register. the ssd also has a 16-bit modulus down counter to monitor blanking and integration times. dc offset compensation is implemented when using the modulus down counter to monitor integration times. 12.4.1 return to zero modes there are four return to zero modes as shown in table 12-11 . 15 14 13 12 11 10 9 8 r itgacc w reset 0 0 0 00000 figure 12-8. integration accumulator register high (itgacc) 76543210 r itgacc w reset 0 0 0 00000 figure 12-9. integration accumulator register low (itgacc) table 12-11. return to zero modes itg dcoil mode 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 486 freescale semiconductor 12.4.1.1 blanking with no drive in blanking mode with no drive, one of the coils is masked from the sigma-delta converter, and if rtz is enabled (rtze = 1), it is set up to recirculate its current. if rtz is enabled (rtze = 1), the other coil is disconnected to prevent any loss of ?x change that would occur when the motor starts moving before the end of recirculation and start of integration. in blanking mode with no drive, the accumulator is initialized to 0x0000 and the converter is in a reset state. 12.4.1.2 blanking with drive in blanking mode with drive, one of the coils is masked from the sigma-delta converter, and if rtz is enabled (rtze = 1), it is set up to recirculate its current. if rtz is enabled (rtze = 1), the other coil is driven. in blanking mode with drive, the accumulator is initialized to 0x0000 and the converter is in a reset state. 12.4.1.3 conversion in conversion mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. if rtz is enabled (rtze=1), both coils are disconnected. this mode is not useful for stall detection. 12.4.1.4 integration in integration mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. if rtz is enabled (rtze = 1), the other coil is driven. this mode is used to rectify and integrate the back emf produced by the coils to detect stepped rotary motion. dc offset compensation is implemented when using the modulus down counter to monitor integration time. 12.4.2 full step states during a return to zero (rtz) event, the stepper motor pointer requires a 90 full motor electrical step with full amplitude pulses applied to each phase in turn. for counter clockwise rotation (ccw), the step value is incremented 0, 1, 2, 3, 0 and so on, and for a clockwise rotation the step value is decremented 3, 2, 1, 0 and so on. figure 12-10 shows the current level through each coil for each full step in ccw rotation when dcoil is set. 0 0 blanking with no drive 0 1 blanking with drive 1 0 conversion 1 1 integration table 12-11. return to zero modes 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 487 figure 12-10. full steps (ccw) figure 12-11 shows the current ?w in the sinx and cosx h-bridges when step = 0, dcoil = 1, itg = 0 and rcir = 0. figure 12-11. current flow when step = 0, dcoil = 1, itg = 0, rcir = 0 figure 12-12 shows the current ?w in the sinx and cosx h-bridges when step = 1, dcoil = 1, itg = 0 and rcir = 1. 0 1 2 3 0 imax + _ imax 0 imax + _ imax sine coil current cosine coil current recirculation vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 488 freescale semiconductor figure 12-12. current flow when step = 1, dcoil = 1, itg = 0, rcir = 1 figure 12-13 shows the current ?w in the sinx and cosx h-bridges when step = 2, dcoil = 1 and itg = 1. figure 12-13. current ?w when step = 2, dcoil = 1, itg = 1 figure 12-14 shows the current ?w in the sinx and cosx h-bridges when step = 3, dcoil = 1 and itg = 1. vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 489 figure 12-14. current ?w when step = 3, dcoil = 1, itg = 1 vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 490 freescale semiconductor 12.4.3 operation in low power modes the ssd block can be con?ured for lower mcu power consumption in three different ways. stop mode powers down the sigma-delta converter and halts clock to the modulus counter. exit from stop enables the sigma-delta converter and the clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. wait mode with ssdwai bit set powers down the sigma-delta converter and halts the clock to the modulus counter. exit from wait enables the sigma-delta converter and clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. clearing sdcpu bit powers down the sigma-delta converter. 12.4.4 stall detection flow figure 12-15 shows a ?wchart and software setup for stall detection of a stepper motor. to control a second stepper motor, the sms bit must be toggled during the ssd initialization. 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 491 figure 12-15. return-to-zero flowchart advance pointer initialize ssd start blanking start integration disable ssd end of blanking? end of integration? stall detection? using motor control module, drive pointer to within 3 full steps of calibrated zero position. 1. clear (or set) rcir; clear (or set) pol; clear (or set) sms; 2. set mczie; clear modmc; clear (or set) pre; set mcen. 3. set rtze; set sdcpu; write aclks (select sample frequency). 4. store threshold value in ram. 1. clear mczif. 2. write mdccnt with blanking time value. 3. clear itg; clear (or set) dcoil; increment (or decrement) step for ccw (or cw) motion. mdccnt = 0x0000? or mczif = 1? 1. clear mczif. 2. write mdccnt with integration time value. 3. set itg; set dcoil. mdccnt = 0x0000? or mczif = 1? yes no yes no itgacc < threshold (ram value)? 1. clear mczif. 2. clear mcen. 3. clear itg. 4. clear rtze; clear sdcpu. yes no 4 .com u datasheet
chapter 12 stepper stall detector (ssdv1) MC9S12XHZ512 data sheet, rev. 1.02 492 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 493 chapter 13 inter-integrated circuit (iicv3) 13.1 introduction the inter-ic bus (iic) is a two-wire, bidirectional serial bus that provides a simple, ef?ient method of data exchange between devices. being a two-wire device, the iic bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. this bus is suitable for applications requiring occasional communications over a short distance between a number of devices. it also provides ?xibility, allowing additional devices to be connected to the bus for further expansion and system development. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. 13.1.1 features the iic module has the following key features: compatible with i2c bus standard multi-master operation software programmable for one of 256 different serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identi?ation interrupt start and stop signal generation/detection repeated start signal generation acknowledge bit generation/detection bus busy detection general call address detection compliant to ten-bit address 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 494 freescale semiconductor 13.1.2 modes of operation the iic functions the same in normal, special, and emulation modes. it has two low power modes: wait and stop modes. 13.1.3 block diagram the block diagram of the iic module is shown in figure 13-1 . figure 13-1. iic block diagram in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock iic registers 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 495 13.2 external signal description the iicv3 module has two external pins. 13.2.1 iic_scl ?serial clock line pin this is the bidirectional serial clock line (scl) of the module, compatible to the iic bus speci?ation. 13.2.2 iic_sda ?serial data line pin this is the bidirectional serial data line (sda) of the module, compatible to the iic bus speci?ation. 13.3 memory map and register de?ition this section provides a detailed description of all memory and registers for the iic module. 13.3.1 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 654321 bit 0 ibad r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w ibfd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w ibcr r iben ibie ms/ sl tx/ rx txak 00 ibswai w rsta ibsr r tcf iaas ibb ibal 0srw ibif rxak w ibdr r d7 d6 d5 d4 d3 d2 d1 d0 w ibcr2 r gcen adtype 000 ad10 ad9 ad8 w = unimplemented or reserved figure 13-2. iic register summary 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 496 freescale semiconductor 13.3.1.1 iic address register (ibad) read and write anytime this register contains the address the iic bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. 13.3.1.2 iic frequency divider register (ibfd) read and write anytime 76543210 r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w reset 0 0 0 00000 = unimplemented or reserved figure 13-3. iic bus address register (ibad) table 13-1. ibad field descriptions field description 7:1 ad[7:1] slave address bit 1 to bit 7 contain the speci? slave address to be used by the iic bus module.the default mode of iic bus is slave mode for an address match on the bus. 0 reserved reserved ?bit 0 of the ibad is reserved for future compatibility. this bit will always read 0. 76543210 r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w reset 0 0 0 00000 = unimplemented or reserved figure 13-4. iic bus frequency divider register (ibfd) table 13-2. ibfd field descriptions field description 7:0 ibc[7:0] i bus clock rate 7:0 ?this ?ld is used to prescale the clock for bit rate selection. the bit clock generator is implemented as a prescale divider ibc7:6, prescaled shift register ibc5:3 select the prescaler divider and ibc2-0 select the shift register tap point. the ibc bits are decoded to give the tap and prescale values as shown in table 13-3 . 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 497 the number of clocks from the falling edge of scl to the ?st tap (tap[1]) is de?ed by the values shown in the scl2tap column of table 13-3 , all subsequent tap points are separated by 2 ibc5-3 as shown in the tap2tap column in table 13-3 . the scl tap is used to generated the scl period and the sda tap is used to determine the delay from the falling edge of scl to sda changing, the sda hold time. ibc7? de?es the multiplier factor mul. the values of mul are shown in the table 13-4 . table 13-3. i-bus tap and prescale values ibc2-0 (bin) scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 ibc5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0002741 0012742 0102964 0116968 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 table 13-4. multiplier factor ibc7-6 mul 00 01 01 02 10 04 11 reserved 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 498 freescale semiconductor figure 13-5. scl divider and sda hold the equation used to generate the divider values from the ibfd bits is: scl divider = mul x {2 x (scl2tap + [(scl_tap -1) x tap2tap] + 2)} the sda hold delay is equal to the cpu clock period multiplied by the sda hold value shown in table 13-5 . the equation used to generate the sda hold value from the ibfd bits is: sda hold = mul x {scl2tap + [(sda_tap - 1) x tap2tap] + 3} the equation for scl hold values to generate the start and stop conditions from the ibfd bits is: scl hold(start) = mul x [scl2start + (scl_tap - 1) x tap2tap] scl hold(stop) = mul x [scl2stop + (scl_tap - 1) x tap2tap] table 13-5. iic divider and hold values (sheet 1 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul=1 scl divider sda hold scl sda sda scl start condition stop condition scl hold(start) scl hold(stop) 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 499 00 20 7 6 11 01 22 7 7 12 02 24 8 8 13 03 26 8 9 14 04 28 9 10 15 05 30 9 11 16 06 34 10 13 18 07 40 10 16 21 08 28 7 10 15 09 32 7 12 17 0a 36 9 14 19 0b 40 9 16 21 0c 44 11 18 23 0d 48 11 20 25 0e 56 13 24 29 0f 68 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 17 54 57 1b 128 17 62 65 1c 144 25 70 73 1d 160 25 78 81 1e 192 33 94 97 1f 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 2b 512 65 254 257 2c 576 97 286 289 table 13-5. iic divider and hold values (sheet 2 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 500 freescale semiconductor 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921 mul=2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 4b 80 18 32 42 4c 88 22 36 46 4d 96 22 40 50 4e 112 26 48 58 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 table 13-5. iic divider and hold values (sheet 3 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 501 59 192 18 92 98 5a 224 34 108 114 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 34 156 162 61 384 34 188 194 62 448 66 220 226 63 512 66 252 258 64 576 98 284 290 65 640 98 316 322 66 768 130 380 386 67 960 130 476 482 68 640 66 316 322 69 768 66 380 386 6a 896 130 444 450 6b 1024 130 508 514 6c 1152 194 572 578 6d 1280 194 636 642 6e 1536 258 764 770 6f 1920 258 956 962 70 1280 130 636 642 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 1148 1154 75 2560 386 1276 1282 76 3072 514 1532 1538 77 3840 514 1916 1922 78 2560 258 1276 1282 79 3072 258 1532 1538 7a 3584 514 1788 1794 7b 4096 514 2044 2050 7c 4608 770 2300 2306 7d 5120 770 2556 2562 7e 6144 1026 3068 3074 7f 7680 1026 3836 3842 mul=4 80 80 28 24 44 81 88 28 28 48 82 96 32 32 52 83 104 32 36 56 84 112 36 40 60 table 13-5. iic divider and hold values (sheet 4 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 502 freescale semiconductor 85 120 36 44 64 86 136 40 52 72 87 160 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 36 56 76 8b 160 36 64 84 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 b0 2560 260 1272 1284 b1 3072 260 1528 1540 table 13-5. iic divider and hold values (sheet 5 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 503 13.3.1.3 iic control register (ibcr) read and write anytime b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 76543210 r iben ibie ms/sl tx/rx txak 00 ibswai w rsta reset 0 0 0 00000 = unimplemented or reserved figure 13-6. iic bus control register (ibcr) table 13-6. ibcr field descriptions field description 7 iben i-bus enable ?this bit controls the software reset of the entire iic bus module. 0 the module is reset and disabled. this is the power-on reset situation. when low the interface is held in reset but registers can be accessed 1 the iic bus module is enabled.this bit must be set before any other ibcr bits have any effect if the iic bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. this would ultimately result in either the current bus master or the iic bus module losing arbitration, after which bus operation would return to normal. 6 ibie i-bus interrupt enable 0 interrupts from the iic bus module are disabled. note that this does not clear any currently pending interrupt condition 1 interrupts from the iic bus module are enabled. an iic bus interrupt occurs provided the ibif bit in the status register is also set. table 13-5. iic divider and hold values (sheet 6 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 504 freescale semiconductor wait mode is entered via execution of a cpu wai instruction. in the event that the ibswai bit is set, all clocks internal to the iic will be stopped and any transmission currently in progress will halt.if the cpu were woken up by a source other than the iic module, then clocks would restart and the iic would resume from where was during the previous transmission. it is not possible for the iic to wake up the cpu when its internal clocks are stopped. if it were the case that the ibswai bit was cleared when the wai instruction was executed, the iic internal clocks and interface would remain alive, continuing the operation which was currently underway. it is also possible to con?ure the iic such that it will wake up the cpu via an interrupt at the conclusion of the current operation. see the discussion on the ibif and ibie bits in the ibsr and ibcr, respectively. 5 ms/sl master/slave mode select bit upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave.a stop signal should only be generated if the ibif ?g is set. ms/ sl is cleared without generating a stop signal when the master loses arbitration. 0 slave mode 1 master mode 4 tx/rx transmit/receive mode select bit ?this bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software according to the srw bit in the status register. in master mode this bit should be set according to the type of transfer required. therefore, for address cycles, this bit will always be high. 0 receive 1 transmit 3 txak transmit acknowledge enable this bit speci?s the value driven onto sda during data acknowledge cycles for both master and slave receivers. the iic module will always acknowledge address matches, provided it is enabled, regardless of the value of txak. note that values written to this bit are only used when the iic bus is a receiver, not a transmitter. 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 2 rsta repeat start ?writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a low. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 1 reserved reserved ?bit 1 of the ibcr is reserved for future compatibility. this bit will always read 0. 0 ibswai i bus interface stop in wait mode 0 iic bus module clock operates normally 1 halt iic bus module clock generation in wait mode table 13-6. ibcr field descriptions (continued) field description 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 505 13.3.1.4 iic status register (ibsr) this status register is read-only with exception of bit 1 (ibif) and bit 4 (ibal), which are software clearable. 76543210 r tcf iaas ibb ibal 0srw ibif rxak w reset 1 0 0 00000 = unimplemented or reserved figure 13-7. iic bus status register (ibsr) table 13-7. ibsr field descriptions field description 7 tcf data transferring bit ?while one byte of data is being transferred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that this bit is only valid during or immediately following a transfer to the iic module or from the iic module. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave bit when its own speci? address (i-bus address register) is matched with the calling address or it receives the general call address with gcen== 1,this bit is set.the cpu is interrupted provided the ibie is set.then the cpu needs to check the srw bit and set its tx/ rx mode accordingly.writing to the i-bus control register clears this bit. 0 not addressed 1 addressed as a slave 5 ibb bus busy bit 0 this bit indicates the status of the bus. when a start signal is detected, the ibb is set. if a stop signal is detected, ibb is cleared and the bus enters idle state. 1 bus is busy 4 ibal arbitration lost ?the arbitration lost bit (ibal) is set by hardware when the arbitration procedure is lost. arbitration is lost in the following circumstances: 1. sda sampled low when the master drives a high during an address or data transmit cycle. 2. sda sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. a start cycle is attempted when the bus is busy. 4. a repeated start cycle is requested in slave mode. 5. a stop condition is detected when the master did not request it. this bit must be cleared by software, by writing a one to it. a write of 0 has no effect on this bit. 3 reserved reserved ?bit 3 of ibsr is reserved for future use. a read operation on this bit will return 0. 2 srw slave read/write when iaas is set this bit indicates the value of the r/w command bit of the calling address sent from the master this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. checking this bit, the cpu can select slave transmit/receive mode according to the command of the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 506 freescale semiconductor 13.3.1.5 iic data i/o register (ibdr) in master transmit mode, when data is written to the ibdr a data transfer is initiated. the most signi?ant bit is sent ?st. in master receive mode, reading this register initiates next byte data receiving. in slave mode, the same functions are available after an address match has occurred.note that the tx/rx bit in the ibcr must correctly re?ct the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is con?ured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. reading the ibdr will return the last byte received while the iic is con?ured in either master receive or slave receive modes. the ibdr does not re?ct every byte that is transmitted on the iic bus, nor can software verify that a byte has been written to the ibdr correctly by reading it back. in master transmit mode, the ?st byte of data written to ibdr following assertion of ms/ sl is used for the address transfer and should com.prise of the calling address (in position d7:d1) concatenated with the required r/ w bit (in position d0). 1 ibif i-bus interrupt ?the ibif bit is set when one of the following conditions occurs: ?arbitration lost (ibal bit set) ?byte transfer complete (tcf bit set) ?addressed as slave (iaas bit set) it will cause a processor interrupt request if the ibie bit is set. this bit must be cleared by software, writing a one to it. a write of 0 has no effect on this bit. 0 rxak received acknowledge ?the value of sda during the acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. 0 acknowledge received 1 no acknowledge received 76543210 r d7 d6 d5 d4 d3 d2 d1 d0 w reset 0 0 0 00000 figure 13-8. iic bus data i/o register (ibdr) table 13-7. ibsr field descriptions (continued) field description 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 507 13.3.1.6 iic control register 2(ibcr2) figure 13-9. iic bus control register 2(ibcr2) this register contains the variables used in general call and in ten-bit address. read and write anytime 13.4 functional description this section provides a complete functional description of the iicv3. 13.4.1 i-bus protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. logic and function is exercised on both lines with external pull-up resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave address transmission, data transfer and stop signal. they are described brie? in the following sections and illustrated in figure 13-10 . 76543210 r gcen adtype 000 ad10 ad9 ad8 w reset 0 0 0 00000 table 13-8. ibcr2 field descriptions field description 7 gcen general call enable . 0 general call is disabled. the module dont receive any general call data and address. 1 enable general call. it indicates that the module can receive address and any data. 6 adtype address type this bit selects the address length. the variable must be con?ured correctly before iic enters slave mode. 0 7-bit address 1 10-bit address 5,4,3 reserved reserved ?bit 5,4 and 3 of the ibcr2 are reserved for future compatibility. these bits will always read 0. 2:0 ad[10:8] slave address [10:8] ?hese 3 bits represent the msb of the 10-bit address when address type is asserted (adtype = 1). 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 508 freescale semiconductor figure 13-10. iic-bus transmission signals 13.4.1.1 start signal when the bus is free, i.e. no master device is engaging the bus (both scl and sda lines are at logical high), a master may initiate communication by sending a start signal.as shown in figure 13-10 , a start signal is de?ed as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. figure 13-11. start and stop conditions scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 99 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write sda scl start condition stop condition 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 509 13.4.1.2 slave address transmission the ?st byte of data transfer immediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. if the calling address is 10-bit, another byte is followed by the ?st byte.only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pulling the sda low at the 9th clock (see figure 13-10 ). no two slaves in the system may have the same address. if the iic bus is master, it must not transmit an address that is equal to its own slave address. the iic bus cannot be master and slave at the same time.however, if arbitration is lost during an address cycle the iic bus will revert to slave mode and operate correctly even if it is being addressed by another master. 13.4.1.3 data transfer as soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction speci?d by the r/w bit sent by the calling master all transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 13-10 . there is one clock pulse on scl for each data bit, the msb being transferred ?st. each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the sda low at the ninth clock. so one complete data byte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. if the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda line for the master to generate stop or start signal. 13.4.1.4 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal ?st. this is called repeated start. a stop signal is de?ed as a low-to-high transition of sda while scl at logical 1 (see figure 13-10 ). the master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 510 freescale semiconductor 13.4.1.5 repeated start signal as shown in figure 13-10 , a repeated start signal is a start signal generated without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 13.4.1.6 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. 13.4.1.7 clock synchronization because wire-and logic is performed on scl line, a high-to-low transition on scl line affects all the devices connected on the bus. the devices start counting their low period and as soon as a device's clock has gone low, it holds the scl line low until the clock high state is reached.however, the change of low to high in this device clock may not change the state of the scl line if another device clock is within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 13-11 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods.the ?st device to complete its high period pulls the scl line low again. figure 13-12. iic-bus clock synchronization scl1 scl2 scl internal counter reset wait start counting high period 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 511 13.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 13.4.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive scl low for the required period and then release it.if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 13.4.1.10 ten-bit address a ten-bit address is indicated if the ?st 5 bits of the ?st address byte are 0x11110. the following rules apply to the ?st address byte. figure 13-13. de?ition of bits in the ?st byte . the address type is identi?d by adtype. when adtype is 0, 7-bit address is applied. reversely, the address is 10-bit address.generally, there are two cases of 10-bit address.see the fig.1-14 and 1-15. figure 13-14. a master-transmitter addresses a slave-receiver with a 10-bit address figure 13-15. a master-receiver addresses a slave-transmitter with a 10-bit address. in the ?ure 1-15,the ?st two bytes are the similar to ?ure1-14.after the repeated start(sr),the ?st slave address is transmitted again, but the r/w is 1, meaning that the slave is acted as a transmitter. slave address r/w bit description 0000000 0 general call address 0000010 x reserved for different bus format 0000011 x reserved for future purposes 11111xx x reserved for future purposes 11110xx x 10-bit slave addressing s slave add1st 7bits 11110+ad10+ad9 r/w 0 a1 slave add 2nd byte ad[8:1] a2 data a3 s slave add1st 7bits 11110+ad10+ad9 r/w 0 a1 slave add 2nd byte ad[8:1] a2 sr slave add 1st 7bits 11110+ad10+ad9 r/w 1 a3 data a4 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 512 freescale semiconductor 13.4.1.11 general call address if some device want to generate a broadcast, it must ?st generate general call address($00), then after receiving acknowledge, it should generate data. in the communication, as slave device, provided its gcen is asserted, it would acknowledge the broadcast and receive data until the gcen is disabled or the master device release the bus or generate a new transfer.in the broadcast, slaves always act as receivers. note in general call, iaas is also used to indicate the address match.in order to distinguish whether the address match is the normal address match or the general call address match, ibdr should be read after its addressed. if the data is ?0?we can conclude the match is general call address match. the meaning of the general call address is always speci?d in the ?st data byte. but iic dont interpret it. it must be dealt with by s/w. when one byte transfer is done, user can get the data by reading ibdr. generally, user can control the procedure by enabling or disabling gcen. 13.4.2 operation in run mode this is the basic mode of operation. 13.4.3 operation in wait mode iic operation in wait mode can be con?ured. depending on the state of internal bits, the iic can operate normally when the cpu is in wait mode or the iic clock generation can be turned off and the iic module enters a power conservation state during wait mode. in the later case, any transmission or reception in progress stops at wait mode entry. 13.4.4 operation in stop mode the iic is inactive in stop mode for reduced power consumption. the stop instruction does not affect iic register states. 13.5 resets the reset state of each individual bit is listed in section 13.3, ?emory map and register de?ition , which details the registers and their bit-?lds. 13.6 interrupts iicv3 uses only one interrupt vector. table 13-9. interrupt summary internally there are three types of interrupts in iic. the interrupt service routine can determine the interrupt type by reading the status register. interrupt offset vector priority source description iic interrupt ibal, tcf, iaas bits in ibsr register when either of ibal, tcf or iaas bits is set may cause an interrupt based on arbitration lost, transfer complete or address detect conditions 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 513 iic interrupt can be generated on 1. arbitration lost condition (ibal bit set) 2. byte transfer condition (tcf bit set) 3. address detect condition (iaas bit set) the iic interrupt is enabled by the ibie bit in the iic control register. it must be cleared by writing 0 to the ibf bit in the interrupt service routine. 13.7 application information 13.7.1 iic programming examples 13.7.1.1 initialization sequence reset will put the iic bus control register to its default status. before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. update the frequency divider register (ibfd) and select the required division ratio to obtain scl frequency from system clock. 2. update the adtype of ibcr2 to de?e the address length, 7 bits or 10 bits. 3. update the iic bus address register (ibad) to de?e its slave address. if 10-bit address is applied ibcr2 should be updated to de?e the rest bits of address. 4. set the iben bit of the iic bus control register (ibcr) to enable the iic interface system. 5. modify the bits of the iic bus control register (ibcr) to select master/slave mode, transmit/receive mode and interrupt enable or not. 6. if supported general call, the gcen in ibcr2 should be asserted. 13.7.1.2 generation of start after completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the iic bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the ?st byte (the slave address) can be sent. the data written to the data register comprises the slave calling address and the lsb set to indicate the direction of transfer required from the slave. the bus free time (i.e., the time between a stop condition and the following start condition) is built into the hardware that generates the start cycle. depending on the relative frequencies of the system clock and the scl period it may be necessary to wait until the iic is busy after writing the calling address to the ibdr before proceeding with the following instructions. this is illustrated in the following example. an example of a program which generates the start signal and transmits the ?st byte of data (slave address) is shown below: 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 514 freescale semiconductor 13.7.1.3 post-transfer software response transmission or reception of a byte will set the data transferring bit (tcf) to 1, which indicates one byte communication is ?ished. the iic bus interrupt bit (ibif) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the ibie bit. software must clear the ibif bit in the interrupt routine ?st. the tcf bit will be cleared by reading from the iic bus data i/o register (ibdr) in receive mode or writing to ibdr in transmit mode. software may service the iic i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that polling should monitor the ibif bit rather than the tcf bit because their operation is different when arbitration is lost. note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. if master receive mode is required, indicated by r/w bit in ibdr, then the tx/rx bit should be toggled at this stage. during slave mode address cycles (iaas=1), the srw bit in the status register is read to determine the direction of the subsequent transfer and the tx/rx bit is programmed accordingly.for slave mode data cycles (iaas=0) the srw bit is not valid, the tx/rx bit in the control register should be read to determine the direction of the current transfer. the following is an example of a software response by a 'master transmitter' in the interrupt routine. 13.7.1.4 generation of stop a data transfer ends with a stop signal generated by the 'master' device. a master transmitter can simply generate a stop signal after all the data has been transmitted. the following is an example showing how a stop condition is generated by a master transmitter. if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (txak) chflag brset ibsr,#$20,* ;wait for ibb flag to clear txstart bset ibcr,#$30 ;set transmit and master mode;i.e. generate start condition movb calling,ibdr ;transmit the calling address, d0=r/w ibfree brclr ibsr,#$20,* ;wait for ibb flag to set isr bclr ibsr,#$02 ;clear the ibif flag brclr ibcr,#$20,slave ;branch if in slave mode brclr ibcr,#$10,receive ;branch if in receive mode brset ibsr,#$01,end ;if no ack, end of transmission transmit movb databuf,ibdr ;transmit next byte of data mastx tst txcnt ;get value from the transmiting counter beq end ;end if no more data brset ibsr,#$01,end ;end if no ack movb databuf,ibdr ;transmit next byte of data dec txcnt ;decrease the txcnt bra emastx ;exit end bclr ibcr,#$20 ;generate a stop condition emastx rti ;return from interrupt 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 515 before reading the 2nd last byte of data. before reading the last byte of data, a stop signal must be generated ?st. the following is an example showing how a stop signal is generated by a master receiver. 13.7.1.5 generation of repeated start at the end of data transfer, if the master continues to want to communicate on the bus, it can generate another start signal followed by another slave address without ?st generating a stop signal. a program example is as shown. 13.7.1.6 slave mode in the slave interrupt service routine, the module addressed as slave bit (iaas) should be tested to check if a calling of its own address has just been received. if iaas is set, software should set the transmit/receive mode select bit (tx/rx bit of ibcr) according to the r/w command bit (srw). writing to the ibcr clears the iaas automatically. note that the only time iaas is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have iaas cleared. a data transfer may now be initiated by writing information to ibdr, for slave transmits, or dummy reading from ibdr, in slave receive mode. the slave will drive scl low in-between byte transfers, scl is released when the ibdr is accessed in the required mode. in slave transmitter routine, the received acknowledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal. 13.7.1.7 arbitration lost if several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. the devices which lost arbitration are immediately switched to slave receive mode by the hardware. their data output to the sda line is stopped, but scl continues to be generated until the end of the byte during which arbitration was lost. an interrupt occurs at the falling edge of the ninth clock of this transfer with ibal=1 and ms/sl=0. if one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the ms/sl bit from 1 to 0 without generating stop condition; generate an interrupt to cpu and set the ibal to indicate that the masr dec rxcnt ;decrease the rxcnt beq enmasr ;last byte to be read movb rxcnt,d1 ;check second last byte dec d1 ;to be read bne nxmar ;not last or second last lamar bset ibcr,#$08 ;second last, disable ack ;transmitting bra nxmar enmasr bclr ibcr,#$20 ;last one, generate ?top?signal nxmar movb ibdr,rxbuf ;read data and store rti restart bset ibcr,#$04 ;another start (restart) movb calling,ibdr ;transmit the calling address;d0=r/w 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 516 freescale semiconductor attempt to engage the bus is failed. when considering these cases, the slave service routine should test the ibal ?st and the software should clear the ibal bit if it is set. 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 517 figure 13-16. flow-chart of typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n ibif address transfer data transfer 4 .com u datasheet
chapter 13 inter-integrated circuit (iicv3) MC9S12XHZ512 data sheet, rev. 1.02 518 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 519 chapter 14 freescales scalable controller area network (mscanv3) 14.1 introduction freescales scalable controller area network (s12mscanv3) de?ition is based on the mscan12 de?ition, which is the speci? implementation of the mscan concept targeted for the m68hc12 microcontroller family. the module is a communication controller implementing the can 2.0a/b protocol as de?ed in the bosch speci?ation dated september 1991. for users to fully understand the mscan speci?ation, it is recommended that the bosch speci?ation be read ?st to familiarize the reader with the terms and concepts contained within this document. though not exclusively intended for automotive applications, can protocol is designed to meet the speci? requirements of a vehicle serial data bus: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, and required bandwidth. mscan uses an advanced buffer arrangement resulting in predictable real-time behavior and simpli?d application software. 14.1.1 glossary ack: acknowledge of can message can: controller area network crc: cyclic redundancy code eof: end of frame fifo: first-in-first-out memory ifs: inter-frame sequence sof: start of frame cpu bus: cpu related read/write data bus can bus: can protocol related serial bus oscillator clock: direct clock from external oscillator bus clock: cpu bus realated clock can clock: can protocol related clock 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 520 freescale semiconductor 14.1.2 block diagram figure 14-1. mscan block diagram 14.1.3 features the basic features of the mscan are as follows: implementation of the can protocol ?version 2.0a/b standard and extended data frames zero to eight bytes data length programmable bit rate up to 1 mbps 1 support for remote frames five receive buffers with fifo storage scheme three transmit buffers with internal prioritization using a ?ocal priority?concept flexible maskable identi?r ?ter supports two full-size (32-bit) extended identi?r ?ters, or four 16-bit ?ters, or eight 8-bit ?ters programmable wakeup functionality with integrated low-pass ?ter programmable loopback mode supports self-test operation programmable listen-only mode for monitoring of can bus programmable bus-off recovery functionality separate signalling and interrupt capabilities for all can receiver and transmitter error states (warning, error passive, bus-off) programmable mscan clock source either bus clock or oscillator clock internal timer for time-stamping of received and transmitted messages 1. depending on the actual bit timing and the clock jitter of the pll. rxcan txcan receive/ transmit engine message filtering and buffering control and status wake-up interrupt req. errors interrupt req. receive interrupt req. transmit interrupt req. canclk bus clock con?uration oscillator clock mux presc. tq clk mscan low pass filter wake-up registers 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 521 three low-power modes: sleep, power down, and mscan enable global initialization of con?uration registers 14.1.4 modes of operation the following modes of operation are speci? to the mscan. see section 14.4, ?unctional description , for details. listen-only mode mscan sleep mode mscan initialization mode mscan power down mode 14.2 external signal description the mscan uses two external pins: 14.2.1 rxcan ?can receiver input pin rxcan is the mscan receiver input pin. 14.2.2 txcan ?can transmitter output pin txcan is the mscan transmitter output pin. the txcan output pin represents the logic level on the can bus: 0 = dominant state 1 = recessive state 14.2.3 can system a typical can system with mscan is shown in figure 14-2 . each can station is connected physically to the can bus lines through a transceiver device. the transceiver is capable of driving the large current needed for the can bus and has current protection against defective can or defective stations. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 522 freescale semiconductor figure 14-2. can system 14.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the mscan. 14.3.1 module memory map figure 14-3 gives an overview on all registers and their individual bits in the mscan memory map. the register address results from the addition of base address and address offset . the base address is determined at the mcu level and can be found in the mcu memory map description. the address offset is de?ed at the module level. the mscan occupies 64 bytes in the memory space. the base address of the mscan module is determined at the mcu level when the mcu is de?ed. the register decode map is ?ed and begins at the ?st address of the module address offset. the detailed register descriptions follow in the order they appear in the register map. can bus can controller (mscan) transceiver can node 1 can node 2 can node n can_l can_h mcu txcan rxcan 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 523 register name bit 7 6 5 4 3 2 1 bit 0 0x0000 canctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0001 canctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0002 canbtr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0003 canbtr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0004 canrflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0005 canrier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0006 cantflg r0 0 0 00 txe2 txe1 txe0 w 0x0007 cantier r00000 txeie2 txeie1 txeie0 w 0x0008 cantarq r00000 abtrq2 abtrq1 abtrq0 w 0x0009 cantaak r00000 abtak2 abtak1 abtak0 w 0x000a cantbsel r00000 tx2 tx1 tx0 w 0x000b canidac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x000c reserved r00000000 w 0x000d canmisc r0000000 bohold w 0x000e canrxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w = unimplemented or reserved u = unaffected figure 14-3. mscan register summary 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 524 freescale semiconductor 14.3.2 register descriptions this section describes in detail all the registers and register bits in the mscan module. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. all bits of all registers in this module are completely synchronous to internal clocks during a register read. 14.3.2.1 mscan control register 0 (canctl0) the canctl0 register provides various control bits of the mscan module as described below. 0x000f cantxerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0010?x0013 canidar0? r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0014?x0017 canidmrx r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0018?x001b canidar4? r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x001c?x001f canidmr4? r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0020?x002f canrxfg r see section 14.3.3, ?rogrammers model of message storage w 0x0030?x003f cantxfg r see section 14.3.3, ?rogrammers model of message storage w module base + 0x0000 76543210 r rxfrm rxact cswai synch time wupe slprq initrq w reset: 00000001 = unimplemented figure 14-4. mscan control register 0 (canctl0) register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved u = unaffected figure 14-3. mscan register summary (continued) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 525 note the canctl0 register, except wupe, initrq, and slprq, is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). read: anytime write: anytime when out of initialization mode; exceptions are read-only rxact and synch, rxfrm (which is set by the module only), and initrq (which is also writable in initialization mode). table 14-1. canctl0 register field descriptions field description 7 rxfrm 1 received frame flag this bit is read and clear only. it is set when a receiver has received a valid message correctly, independently of the ?ter con?uration. after it is set, it remains set until cleared by software or reset. clearing is done by writing a 1. writing a 0 is ignored. this bit is not valid in loopback mode. 0 no valid message was received since last clearing this ?g 1 a valid message was received since last clearing of this ?g 6 rxact receiver active status ?this read-only ?g indicates the mscan is receiving a message. the ?g is controlled by the receiver front end. this bit is not valid in loopback mode. 0 mscan is transmitting or idle 2 1 mscan is receiving a message (including when arbitration is lost) 2 5 cswai 3 can stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the cpu bus interface to the mscan module. 0 the module is not affected during wait mode 1 the module ceases to be clocked during wait mode 4 synch synchronized status this read-only ?g indicates whether the mscan is synchronized to the can bus and able to participate in the communication process. it is set and cleared by the mscan. 0 mscan is not synchronized to the can bus 1 mscan is synchronized to the can bus 3 time timer enable this bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. if the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active tx/rx buffer. right after the eof of a valid message on the can bus, the time stamp is written to the highest bytes (0x000e, 0x000f) in the appropriate buffer (see section 14.3.3, ?rogrammers model of message storage ?. the internal timer is reset (all bits set to 0) when disabled. this bit is held low in initialization mode. 0 disable internal mscan timer 1 enable internal mscan timer 2 wupe 4 wake-up enable this con?uration bit allows the mscan to restart from sleep mode when traf? on can is detected (see section 14.4.5.4, ?scan sleep mode ?. this bit must be con?ured before sleep mode entry for the selected function to take effect. 0 wake-up disabled ?the mscan ignores traf? on can 1 wake-up enabled ?the mscan is able to restart 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 526 freescale semiconductor 14.3.2.2 mscan control register 1 (canctl1) the canctl1 register provides various control bits and handshake status information of the mscan module as described below. 1 slprq 5 sleep mode request ?this bit requests the mscan to enter sleep mode, which is an internal power saving mode (see section 14.4.5.4, ?scan sleep mode ?. the sleep mode request is serviced when the can bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. the module indicates entry to sleep mode by setting slpak = 1 (see section 14.3.2.2, ?scan control register 1 (canctl1) ?. slprq cannot be set while the wupif ?g is set (see section 14.3.2.5, ?scan receiver flag register (canrflg) ?. sleep mode will be active until slprq is cleared by the cpu or, depending on the setting of wupe, the mscan detects activity on the can bus and clears slprq itself. 0 running ?the mscan functions normally 1 sleep mode request ?the mscan enters sleep mode when can bus idle 0 initrq 6,7 initialization mode request ?when this bit is set by the cpu, the mscan skips to initialization mode (see section 14.4.5.5, ?scan initialization mode ?. any ongoing transmission or reception is aborted and synchronization to the can bus is lost. the module indicates entry to initialization mode by setting initak = 1 ( section 14.3.2.2, ?scan control register 1 (canctl1) ?. the following registers enter their hard reset state and restore their default values: canctl0 8 , canrflg 9 , canrier 10 , cantflg, cantier, cantarq, cantaak, and cantbsel. the registers canctl1, canbtr0, canbtr1, canidac, canidar0-7, and canidmr0-7 can only be written by the cpu when the mscan is in initialization mode (initrq = 1 and initak = 1). the values of the error counters are not affected by initialization mode. when this bit is cleared by the cpu, the mscan restarts and then tries to synchronize to the can bus. if the mscan is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the can bus; if the mscan is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. writing to other bits in canctl0, canrflg, canrier, cantflg, or cantier must be done only after initialization mode is exited, which is initrq = 0 and initak = 0. 0 normal operation 1 mscan in initialization mode 1 the mscan must be in normal mode for this bit to become set. 2 see the bosch can 2.0a/b speci?ation for a detailed de?ition of transmitter and receiver states. 3 in order to protect from accidentally violating the can protocol, the txcan pin is immediately forced to a recessive state when the cpu enters wait (cswai = 1) or stop mode (see section 14.4.5.2, ?peration in wait mode ?and section 14.4.5.3, ?peration in stop mode ? . 4 the cpu has to make sure that the wupe register and the wupie wake-up interrupt enable register (see section 14.3.2.6, ?scan receiver interrupt enable register (canrier) ) is enabled, if the recovery mechanism from stop or wait is required. 5 the cpu cannot clear slprq before the mscan has entered sleep mode (slprq = 1 and slpak = 1). 6 the cpu cannot clear initrq before the mscan has entered initialization mode (initrq = 1 and initak = 1). 7 in order to protect from accidentally violating the can protocol, the txcan pin is immediately forced to a recessive state when the initialization mode is requested by the cpu. thus, the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before requesting initialization mode. 8 not including wupe, initrq, and slprq. 9 tstat1 and tstat0 are not affected by initialization mode. 10 rstat1 and rstat0 are not affected by initialization mode. table 14-1. canctl0 register field descriptions (continued) field description 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 527 read: anytime write: anytime when initrq = 1 and initak = 1, except cane which is write once in normal and anytime in special system operation modes when the mscan is in initialization mode (initrq = 1 and initak = 1). module base + 0x0001 76543210 r cane clksrc loopb listen borm wupm slpak initak w reset: 00010001 = unimplemented figure 14-5. mscan control register 1 (canctl1) table 14-2. canctl1 register field descriptions field description 7 cane mscan enable 0 mscan module is disabled 1 mscan module is enabled 6 clksrc mscan clock source this bit de?es the clock source for the mscan module (only for systems with a clock generation module; section 14.4.3.2, ?lock system , and section figure 14-43., ?scan clocking scheme ,?. 0 mscan clock source is the oscillator clock 1 mscan clock source is the bus clock 5 loopb loopback self test mode when this bit is set, the mscan performs an internal loopback which can be used for self test operation. the bit stream output of the transmitter is fed back to the receiver internally. the rxcan input pin is ignored and the txcan output goes to the recessive state (logic 1). the mscan behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. in this state, the mscan ignores the bit sent during the ack slot in the can frame acknowledge ?ld to ensure proper reception of its own message. both transmit and receive interrupts are generated. 0 loopback self test disabled 1 loopback self test enabled 4 listen listen only mode this bit con?ures the mscan as a can bus monitor. when listen is set, all valid can messages with matching id are received, but no acknowledgement or error frames are sent out (see section 14.4.4.4, ?isten-only mode ?. in addition, the error counters are frozen. listen only mode supports applications which require ?ot plugging?or throughput analysis. the mscan is unable to transmit any messages when listen only mode is active. 0 normal operation 1 listen only mode activated 3 borm bus-off recovery mode ?this bits con?ures the bus-off state recovery mode of the mscan. refer to section 14.5.2, ?us-off recovery , for details. 0 automatic bus-off recovery (see bosch can 2.0a/b protocol speci?ation) 1 bus-off recovery upon user request 2 wupm wake-up mode ?if wupe in canctl0 is enabled, this bit de?es whether the integrated low-pass ?ter is applied to protect the mscan from spurious wake-up (see section 14.4.5.4, ?scan sleep mode ?. 0 mscan wakes up on any dominant level on the can bus 1 mscan wakes up only in case of a dominant pulse on the can bus that has a length of t wup 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 528 freescale semiconductor 1 slpak sleep mode acknowledge ?this ?g indicates whether the mscan module has entered sleep mode (see section 14.4.5.4, ?scan sleep mode ?. it is used as a handshake ?g for the slprq sleep mode request. sleep mode is active when slprq = 1 and slpak = 1. depending on the setting of wupe, the mscan will clear the ?g if it detects activity on the can bus while in sleep mode. 0 running ?the mscan operates normally 1 sleep mode active ?the mscan has entered sleep mode 0 initak initialization mode acknowledge ?this ?g indicates whether the mscan module is in initialization mode (see section 14.4.5.5, ?scan initialization mode ?. it is used as a handshake ?g for the initrq initialization mode request. initialization mode is active when initrq = 1 and initak = 1. the registers canctl1, canbtr0, canbtr1, canidac, canidar0?anidar7, and canidmr0?anidmr7 can be written only by the cpu when the mscan is in initialization mode. 0 running ?the mscan operates normally 1 initialization mode active ?the mscan has entered initialization mode table 14-2. canctl1 register field descriptions (continued) field description 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 529 14.3.2.3 mscan bus timing register 0 (canbtr0) the canbtr0 register con?ures various can bus timing parameters of the mscan module. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) module base + 0x0002 76543210 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w reset: 00000000 figure 14-6. mscan bus timing register 0 (canbtr 0 ) table 14-3. canbtr 0 register field descriptions field description 7:6 sjw[1:0] synchronization jump width the synchronization jump width de?es the maximum number of time quanta (tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the can bus (see table 14-4 ). 5:0 brp[5:0] baud rate prescaler these bits determine the time quanta (tq) clock which is used to build up the bit timing (see table 14-5 ). table 14-4. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 14-5. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 64 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 530 freescale semiconductor 14.3.2.4 mscan bus timing register 1 (canbtr1) the canbtr1 register con?ures various can bus timing parameters of the mscan module. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) module base + 0x0003 76543210 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w reset: 00000000 figure 14-7. mscan bus timing register 1 (canbtr1) table 14-6. canbtr1 register field descriptions field description 7 samp sampling ?this bit determines the number of can bus samples taken per bit time. 0 one sample per bit. 1 three samples per bit 1 . if samp = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. if samp = 1, the resulting bit value is determined by using majority rule on the three total samples. for higher bit rates, it is recommended that only one sample is taken per bit time (samp = 0). 1 in this case, phase_seg1 must be at least 2 time quanta (tq). 6:4 tseg2[2:0] time segment 2 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 14-44 ). time segment 2 (tseg2) values are programmable as shown in table 14-7 . 3:0 tseg1[3:0] time segment 1 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 14-44 ). time segment 1 (tseg1) values are programmable as shown in table 14-8 . table 14-7. time segment 2 values tseg22 tseg21 tseg20 time segment 2 0 0 0 1 tq clock cycle 1 1 this setting is not valid. please refer to table 14-35 for valid settings. 0 0 1 2 tq clock cycles ::: : 1 1 0 7 tq clock cycles 1 1 1 8 tq clock cycles 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 531 the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown in table 14-7 and table 14-8 ). eqn. 14-1 14.3.2.5 mscan receiver flag register (canrflg) a ?g can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. every ?g has an associated interrupt enable bit in the canrier register. note the canrflg register is held in the reset state 1 when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). read: anytime write: anytime when out of initialization mode, except rstat[1:0] and tstat[1:0] ?gs which are read-only; write of 1 clears ?g; write of 0 is ignored. table 14-8. time segment 1 values tseg13 tseg12 tseg11 tseg10 time segment 1 0 0 0 0 1 tq clock cycle 1 1 this setting is not valid. please refer to table 14-35 for valid settings. 0 0 0 1 2 tq clock cycles 1 0 0 1 0 3 tq clock cycles 1 0 0 1 1 4 tq clock cycles :::: : 1 1 1 0 15 tq clock cycles 1 1 1 1 16 tq clock cycles module base + 0x0004 76543210 r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w reset: 00000000 = unimplemented figure 14-8. mscan receiver flag register (canrflg) 1. the rstat[1:0], tstat[1:0] bits are not affected by initialization mode. bit time prescaler value () f canclk ----------------------------------------------------- - 1 timesegment1 timesegment2 ++ () ? = 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 532 freescale semiconductor table 14-9. canrflg register field descriptions field description 7 wupif wake-up interrupt flag ?if the mscan detects can bus activity while in sleep mode (see section 14.4.5.4, ?scan sleep mode ,? and wupe = 1 in cantctl0 (see section 14.3.2.1, ?scan control register 0 (canctl0) ?, the module will set wupif. if not masked, a wake-up interrupt is pending while this ?g is set. 0 no wake-up activity observed while in sleep mode 1 mscan detected activity on the can bus and requested wake-up 6 cscif can status change interrupt flag ?this ?g is set when the mscan changes its current can bus status due to the actual value of the transmit error counter (tec) and the receive error counter (rec). an additional 4-bit (rstat[1:0], tstat[1:0]) status register, which is split into separate sections for tec/rec, informs the system on the actual can bus status (see section 14.3.2.6, ?scan receiver interrupt enable register (canrier) ?. if not masked, an error interrupt is pending while this ?g is set. cscif provides a blocking interrupt. that guarantees that the receiver/transmitter status bits (rstat/tstat) are only updated when no can status change interrupt is pending. if the tecs/recs change their current value after the cscif is asserted, which would cause an additional state change in the rstat/tstat bits, these bits keep their status until the current cscif interrupt is cleared again. 0 no change in can bus status occurred since last interrupt 1 mscan changed current can bus status 5:4 rstat[1:0] receiver status bits ?the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate receiver related can bus status of the mscan. the coding for the bits rstat1, rstat0 is: 00 rxok: 0 receive error counter 96 01 rxwrn: 96 < receive error counter 127 10 rxerr: 127 < receive error counter 11 bus-off 1 : transmit error counter > 255 1 redundant information for the most critical can bus status which is ?us-off? this only occurs if the tx error counter exceeds a number of 255 errors. bus-off affects the receiver state. as soon as the transmitter leaves its bus-off state the receiver state skips to rxok too. refer also to tstat[1:0] coding in this register. 3:2 tstat[1:0] transmitter status bits ?the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate transmitter related can bus status of the mscan. the coding for the bits tstat1, tstat0 is: 00 txok: 0 transmit error counter 96 01 txwrn: 96 < transmit error counter 127 10 txerr: 127 < transmit error counter 255 11 bus-off: transmit error counter > 255 1 ovrif overrun interrupt flag this ?g is set when a data overrun condition occurs. if not masked, an error interrupt is pending while this ?g is set. 0 no data overrun condition 1 a data overrun detected 0 rxf 2 2 to ensure data integrity, do not read the receive buffer registers while the rxf ?g is cleared. for mcus with dual cpus, reading the receive buffer registers while the rxf ?g is cleared may result in a cpu fault condition. receive buffer full flag rxf is set by the mscan when a new message is shifted in the receiver fifo. this ?g indicates whether the shifted buffer is loaded with a correctly received message (matching identi?r, matching cyclic redundancy code (crc) and no other errors detected). after the cpu has read that message from the rxfg buffer in the receiver fifo, the rxf ?g must be cleared to release the buffer. a set rxf ?g prohibits the shifting of the next fifo entry into the foreground buffer (rxfg). if not masked, a receive interrupt is pending while this ?g is set. 0 no new message available within the rxfg 1 the receiver fifo is not empty. a new message is available in the rxfg 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 533 14.3.2.6 mscan receiver interrupt enable register (canrier) this register contains the interrupt enable bits for the interrupt ?gs described in the canrflg register. note the canrier register is held in the reset state when the initialization mode is active (initrq=1 and initak=1). this register is writable when not in initialization mode (initrq=0 and initak=0). the rstate[1:0], tstate[1:0] bits are not affected by initialization mode. read: anytime write: anytime when not in initialization mode module base + 0x0005 76543210 r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w reset: 00000000 figure 14-9. mscan receiver interrupt enable register (canrier) table 14-10. canrier register field descriptions field description 7 wupie 1 wake-up interrupt enable 0 no interrupt request is generated from this event. 1 a wake-up event causes a wake-up interrupt request. 6 cscie can status change interrupt enable 0 no interrupt request is generated from this event. 1 a can status change event causes an error interrupt request. 5:4 rstate[1:0] receiver status change enable these rstat enable bits control the sensitivity level in which receiver state changes are causing cscif interrupts. independent of the chosen sensitivity level the rstat ?gs continue to indicate the actual receiver state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by receiver state changes. 01 generate cscif interrupt only if the receiver enters or leaves ?us-off?state. discard other receiver state changes for generating cscif interrupt. 10 generate cscif interrupt only if the receiver enters or leaves ?xerr?or ?us-off 2 state. discard other receiver state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 3:2 tstate[1:0] transmitter status change enable these tstat enable bits control the sensitivity level in which transmitter state changes are causing cscif interrupts. independent of the chosen sensitivity level, the tstat ?gs continue to indicate the actual transmitter state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by transmitter state changes. 01 generate cscif interrupt only if the transmitter enters or leaves ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 10 generate cscif interrupt only if the transmitter enters or leaves ?xerr?or ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 534 freescale semiconductor 14.3.2.7 mscan transmitter flag register (cantflg) the transmit buffer empty ?gs each have an associated interrupt enable bit in the cantier register. note the cantflg register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: anytime write: anytime for txex ?gs when not in initialization mode; write of 1 clears ?g, write of 0 is ignored 1 ovrie overrun interrupt enable 0 no interrupt request is generated from this event. 1 an overrun event causes an error interrupt request. 0 rxfie receiver full interrupt enable 0 no interrupt request is generated from this event. 1 a receive buffer full (successful message reception) event causes a receiver interrupt request. 1 wupie and wupe (see section 14.3.2.1, ?scan control register 0 (canctl0) ? must both be enabled if the recovery mechanism from stop or wait is required. 2 bus-off state is de?ed by the can standard (see bosch can 2.0a/b protocol speci?ation: for only transmitters. because the only possible state change for the transmitter from bus-off to txok also forces the receiver to skip its current state to rxok, the coding of the rxstat[1:0] ?gs de?e an additional bus-off state for the receiver (see section 14.3.2.5, ?scan receiver flag register (canrflg) ?. module base + 0x0006 76543210 r0 0 0 00 txe2 txe1 txe0 w reset: 00000111 = unimplemented figure 14-10. mscan transmitter flag register (cantflg) table 14-10. canrier register field descriptions (continued) field description 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 535 14.3.2.8 mscan transmitter interrupt enable register (cantier) this register contains the interrupt enable bits for the transmit buffer empty interrupt ?gs. note the cantier register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: anytime write: anytime when not in initialization mode table 14-11. cantflg register field descriptions field description 2:0 txe[2:0] transmitter buffer empty this ?g indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. the cpu must clear the ?g after a message is set up in the transmit buffer and is due for transmission. the mscan sets the ?g after the message is sent successfully. the ?g is also set by the mscan when the transmission request is successfully aborted due to a pending abort request (see section 14.3.2.9, ?scan transmitter message abort request register (cantarq) ?. if not masked, a transmit interrupt is pending while this ?g is set. clearing a txex ?g also clears the corresponding abtakx (see section 14.3.2.10, ?scan transmitter message abort acknowledge register (cantaak) ?. when a txex ?g is set, the corresponding abtrqx bit is cleared (see section 14.3.2.9, ?scan transmitter message abort request register (cantarq) ?. when listen-mode is active (see section 14.3.2.2, ?scan control register 1 (canctl1) ? the txex ?gs cannot be cleared and no transmission is started. read and write accesses to the transmit buffer will be blocked, if the corresponding txex bit is cleared (txex = 0) and the buffer is scheduled for transmission. 0 the associated message buffer is full (loaded with a message due for transmission) 1 the associated message buffer is empty (not scheduled) module base + 0x0007 76543210 r00000 txeie2 txeie1 txeie0 w reset: 00000000 = unimplemented figure 14-11. mscan transmitter interrupt enable register (cantier) table 14-12. cantier register field descriptions field description 2:0 txeie[2:0] transmitter empty interrupt enable 0 no interrupt request is generated from this event. 1 a transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 536 freescale semiconductor 14.3.2.9 mscan transmitter message abort request register (cantarq) the cantarq register allows abort request of queued messages as described below. note the cantarq register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: anytime write: anytime when not in initialization mode module base + 0x0008 76543210 r00000 abtrq2 abtrq1 abtrq0 w reset: 00000000 = unimplemented figure 14-12. mscan transmitter message abort request register (cantarq) table 14-13. cantarq register field descriptions field description 2:0 abtrq[2:0] abort request ?the cpu sets the abtrqx bit to request that a scheduled message buffer (txex = 0) be aborted. the mscan grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). when a message is aborted, the associated txe (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ? and abort acknowledge ?gs (abtak, see section 14.3.2.10, ?scan transmitter message abort acknowledge register (cantaak) ? are set and a transmit interrupt occurs if enabled. the cpu cannot reset abtrqx. abtrqx is reset whenever the associated txe ?g is set. 0 no abort request 1 abort request pending 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 537 14.3.2.10 mscan transmitter message abort acknowledge register (cantaak) the cantaak register indicates the successful abort of a queued message, if requested by the appropriate bits in the cantarq register. note the cantaak register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). read: anytime write: unimplemented for abtakx ?gs module base + 0x0009 76543210 r00000 abtak2 abtak1 abtak0 w reset: 00000000 = unimplemented figure 14-13. mscan transmitter message abort acknowledge register (cantaak) table 14-14. cantaak register field descriptions field description 2:0 abtak[2:0] abort acknowledge ?this ?g acknowledges that a message was aborted due to a pending abort request from the cpu. after a particular message buffer is ?gged empty, this ?g can be used by the application software to identify whether the message was aborted successfully or was sent anyway. the abtakx ?g is cleared whenever the corresponding txe ?g is cleared. 0 the message was not aborted. 1 the message was aborted. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 538 freescale semiconductor 14.3.2.11 mscan transmit buffer selection register (cantbsel) the cantbsel register allows the selection of the actual transmit message buffer, which then will be accessible in the cantxfg register space. note the cantbsel register is held in the reset state when the initialization mode is active (initrq = 1 and initak=1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: find the lowest ordered bit set to 1, all other bits will be read as 0 write: anytime when not in initialization mode the following gives a short programming example of the usage of the cantbsel register: to get the next available transmit buffer, application software must read the cantflg register and write this value back into the cantbsel register. in this example tx buffers tx1 and tx2 are available. the value read from cantflg is therefore 0b0000_0110. when writing this value back to cantbsel, the tx buffer tx1 is selected in the cantxfg because the lowest numbered bit set to 1 is at bit position 1. reading back this value out of cantbsel results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. this mechanism eases the application software the selection of the next available tx buffer. ldd cantflg; value read is 0b0000_0110 std cantbsel; value written is 0b0000_0110 ldd cantbsel; value read is 0b0000_0010 if all transmit message buffers are deselected, no accesses are allowed to the cantxfg registers. module base + 0x000a 76543210 r00000 tx2 tx1 tx0 w reset: 00000000 = unimplemented figure 14-14. mscan transmit buffer selection register (cantbsel) table 14-15. cantbsel register field descriptions field description 2:0 tx[2:0] transmit buffer select ?the lowest numbered bit places the respective transmit buffer in the cantxfg register space (e.g., tx1 = 1 and tx0 = 1 selects transmit buffer tx0; tx1 = 1 and tx0 = 0 selects transmit buffer tx1). read and write accesses to the selected transmit buffer will be blocked, if the corresponding txex bit is cleared and the buffer is scheduled for transmission (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ?. 0 the associated message buffer is deselected 1 the associated message buffer is selected, if lowest numbered bit 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 539 14.3.2.12 mscan identi?r acceptance control register (canidac) the canidac register is used for identi?r acceptance control as described below. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1), except bits idhitx, which are read-only module base + 0x000b 76543210 r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w reset: 00000000 = unimplemented figure 14-15. mscan identi?r acceptance control register (canidac) table 14-16. canidac register field descriptions field description 5:4 idam[1:0] identi?r acceptance mode the cpu sets these ?gs to de?e the identi?r acceptance ?ter organization (see section 14.4.3, ?denti?r acceptance filter ?. table 14-17 summarizes the different settings. in ?ter closed mode, no message is accepted such that the foreground buffer is never reloaded. 2:0 idhit[2:0] identi?r acceptance hit indicator ?the mscan sets these ?gs to indicate an identi?r acceptance hit (see section 14.4.3, ?denti?r acceptance filter ?. table 14-18 summarizes the different settings. table 14-17. identi?r acceptance mode settings idam1 idam0 identi?r acceptance mode 0 0 two 32-bit acceptance ?ters 0 1 four 16-bit acceptance ?ters 1 0 eight 8-bit acceptance ?ters 1 1 filter closed table 14-18. identi?r acceptance hit indication idhit2 idhit1 idhit0 identi?r acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1 0 0 filter 4 hit 1 0 1 filter 5 hit 1 1 0 filter 6 hit 1 1 1 filter 7 hit 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 540 freescale semiconductor the idhitx indicators are always related to the message in the foreground buffer (rxfg). when a message gets shifted into the foreground buffer of the receiver fifo the indicators are updated as well. 14.3.2.13 mscan reserved register this register is reserved for factory testing of the mscan module and is not available in normal system operation modes. read: always read 0x0000 in normal system operation modes write: unimplemented in normal system operation modes note writing to this register when in special modes can alter the mscan functionality. 14.3.2.14 mscan miscellaneous register (canmisc) this register provides additional features. read: anytime write: anytime; write of ??clears ?g; write of ??ignored module base + 0x000c 76543210 r00000000 w reset: 00000000 = unimplemented figure 14-16. mscan reserved register module base + 0x000d 76543210 r0000000 bohold w reset: 00000000 = unimplemented figure 14-17. mscan miscellaneous register (canmisc) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 541 14.3.2.15 mscan receive error counter (canrxerr) this register re?cts the status of the mscan receive error counter. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented note reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. table 14-19. canmisc register field descriptions field description 0 bohold bus-off state hold until user request ?if borm is set in section 14.3.2.2, ?scan control register 1 (canctl1) , this bit indicates whether the module has entered the bus-off state. clearing this bit requests the recovery from bus-off. refer to section 14.5.2, ?us-off recovery , for details. 0 module is not bus-off or recovery has been requested by user in bus-off state 1 module is bus-off and holds this state until user request module base + 0x000e 76543210 r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w reset: 00000000 = unimplemented figure 14-18. mscan receive error counter (canrxerr) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 542 freescale semiconductor 14.3.2.16 mscan transmit error counter (cantxerr) this register re?cts the status of the mscan transmit error counter. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented note reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. module base + 0x000f 76543210 r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w reset: 00000000 = unimplemented figure 14-19. mscan transmit error counter (cantxerr) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 543 14.3.2.17 mscan identi?r acceptance registers (canidar0-7) on reception, each message is written into the background receive buffer. the cpu is only signalled to read the message if it passes the criteria in the identi?r acceptance and identi?r mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). the acceptance registers of the mscan are applied on the idr0?dr3 registers (see section 14.3.3.1, ?denti?r registers (idr0?dr3) ? of incoming messages in a bit by bit manner (see section 14.4.3, ?denti?r acceptance filter ?. for extended identi?rs, all four acceptance and mask registers are applied. for standard identi?rs, only the ?st two (canidar0/1, canidmr0/1) are applied. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) module base + 0x0010 (canidar0) 0x0011 (canidar1) 0x0012 (canidar2) 0x0013 (canidar3) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 figure 14-20. mscan identi?r acceptance registers (first bank) ?canidar0?anidar3 table 14-20. canidar0?anidar3 register field descriptions field description 7:0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 544 freescale semiconductor read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) module base + 0x0018 (canidar4) 0x0019 (canidar5) 0x001a (canidar6) 0x001b (canidar7) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 figure 14-21. mscan identi?r acceptance registers (second bank) ?canidar4?anidar7 table 14-21. canidar4?anidar7 register field descriptions field description 7:0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 545 14.3.2.18 mscan identi?r mask registers (canidmr0?anidmr7) the identi?r mask register speci?s which of the corresponding bits in the identi?r acceptance register are relevant for acceptance ?tering. to receive standard identi?rs in 32 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1 and canidmr5 to ?ont care. to receive standard identi?rs in 16 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1, canidmr3, canidmr5, and canidmr7 to ?ont care. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) module base + 0x0014 (canidmr0) 0x0015 (canidmr1) 0x0016 (canidmr2) 0x0017 (canidmr3) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 14-22. mscan identi?r mask registers (first bank) ?canidmr0?anidmr3 table 14-22. canidmr0?anidmr3 register field descriptions field description 7:0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 546 freescale semiconductor read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) module base + 0x001c (canidmr4) 0x001d (canidmr5) 0x001e (canidmr6) 0x001f (canidmr7) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 14-23. mscan identi?r mask registers (second bank) ?canidmr4?anidmr7 table 14-23. canidmr4?anidmr7 register field descriptions field description 7:0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 547 14.3.3 programmers model of message storage the following section details the organization of the receive and transmit message buffers and the associated control registers. to simplify the programmer interface, the receive and transmit message buffers have the same outline. each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. an additional transmit buffer priority register (tbpr) is de?ed for the transmit buffers. within the last two bytes of this memory map, the mscan stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. this feature is only available for transmit and receiver buffers, if the time bit is set (see section 14.3.2.1, ?scan control register 0 (canctl0) ?. the time stamp register is written by the mscan. the cpu can only read these registers. figure 14-24 shows the common 13-byte data structure of receive and transmit buffers for extended identi?rs. the mapping of standard identi?rs into the idr registers is shown in figure 14-25 . all bits of the receive and transmit buffers are ??out of reset because of ram-based implementation 1 . all reserved or unused bits of the receive and transmit buffers always read ?? table 14-24. message buffer organization offset address register access 0x00x0 identi?r register 0 0x00x1 identi?r register 1 0x00x2 identi?r register 2 0x00x3 identi?r register 3 0x00x4 data segment register 0 0x00x5 data segment register 1 0x00x6 data segment register 2 0x00x7 data segment register 3 0x00x8 data segment register 4 0x00x9 data segment register 5 0x00xa data segment register 6 0x00xb data segment register 7 0x00xc data length register 0x00xd transmit buffer priority register 1 1 not applicable for receive buffers 0x00xe time stamp register (high byte) 2 2 read-only for cpu 0x00xf time stamp register (low byte) 3 3 read-only for cpu 1. exception: the transmit priority registers are 0 out of reset. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 548 freescale semiconductor read: for transmit buffers, anytime when txex ?g is set (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 14.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. for receive buffers, only when rxf ?g is set (see section 14.3.2.5, ?scan receiver flag register (canrflg) ?. register name bit 7 654321 bit0 0x00x0 idr0 r id28 id27 id26 id25 id24 id23 id22 id21 w 0x00x1 idr1 r id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 w 0x00x2 idr2 r id14 id13 id12 id11 id10 id9 id8 id7 w 0x00x3 idr3 r id6 id5 id4 id3 id2 id1 id0 rtr w 0x00x4 dsr0 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x5 dsr1 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x6 dsr2 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x7 dsr3 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x8 dsr4 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x9 dsr5 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xa dsr6 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xb dsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xc dlr r dlc3 dlc2 dlc1 dlc0 w = unused, always read ? figure 14-24. receive/transmit message buffer ?extended identi?r mapping 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 549 write: for transmit buffers, anytime when txex ?g is set (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 14.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. unimplemented for receive buffers. reset: unde?ed (0x00xx) because of ram-based implementation 14.3.3.1 identi?r registers (idr0?dr3) the identi?r registers for an extended format identi?r consist of a total of 32 bits; id[28:0], srr, ide, and rtr bits. the identi?r registers for a standard format identi?r consist of a total of 13 bits; id[10:0], rtr, and ide bits. 14.3.3.1.1 idr0?dr3 for extended identi?r mapping register name bit 7 654321 bit 0 idr0 0x00x0 r id10 id9 id8 id7 id6 id5 id4 id3 w idr1 0x00x1 r id2 id1 id0 rtr ide (=0) w idr2 0x00x2 r w idr3 0x00x3 r w = unused, always read ? figure 14-25. receive/transmit message buffer ?standard identi?r mapping module base + 0x00x1 76543210 r id28 id27 id26 id25 id24 id23 id22 id21 w reset: xxxxxxxx figure 14-26. identi?r register 0 (idr0) ?extended identi?r mapping table 14-25. idr0 register field descriptions ?extended field description 7:0 id[28:21] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 550 freescale semiconductor module base + 0x00x1 76543210 r id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 w reset: xxxxxxxx figure 14-27. identi?r register 1 (idr1) ?extended identi?r mapping table 14-26. idr1 register field descriptions ?extended field description 7:5 id[20:18] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 4 srr substitute remote request ?this ?ed recessive bit is used only in extended format. it must be set to 1 by the user for transmission buffers and is stored as received on the can bus for receive buffers. 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit) 2:0 id[17:15] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. module base + 0x00x2 76543210 r id14 id13 id12 id11 id10 id9 id8 id7 w reset: xxxxxxxx figure 14-28. identi?r register 2 (idr2) ?extended identi?r mapping table 14-27. idr2 register field descriptions ?extended field description 7:0 id[14:7] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 551 14.3.3.1.2 idr0?dr3 for standard identi?r mapping module base + 0x00x3 76543210 r id6 id5 id4 id3 id2 id1 id0 rtr w reset: xxxxxxxx figure 14-29. identi?r register 3 (idr3) ?extended identi?r mapping table 14-28. idr3 register field descriptions ?extended field description 7:1 id[6:0] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 0 rtr remote transmission request ?this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame module base + 0x00x0 76543210 r id10 id9 id8 id7 id6 id5 id4 id3 w reset: xxxxxxxx figure 14-30. identi?r register 0 ?standard mapping table 14-29. idr0 register field descriptions ?standard field description 7:0 id[10:3] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 14-30 . 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 552 freescale semiconductor module base + 0x00x1 76543210 r id2 id1 id0 rtr ide (=0) w reset: xxxxxxxx = unused; always read ? figure 14-31. identi?r register 1 ?standard mapping table 14-30. idr1 register field descriptions field description 7:5 id[2:0] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 14-29 . 4 rtr remote transmission request this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit) module base + 0x00x2 76543210 r w reset: xxxxxxxx = unused; always read ? figure 14-32. identi?r register 2 ?standard mapping 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 553 14.3.3.2 data segment registers (dsr0-7) the eight data segment registers, each with bits db[7:0], contain the data to be transmitted or received. the number of bytes to be transmitted or received is determined by the data length code in the corresponding dlr register. module base + 0x00x3 76543210 r w reset: xxxxxxxx = unused; always read ? figure 14-33. identi?r register 3 ?standard mapping module base + 0x0004 (dsr0) 0x0005 (dsr1) 0x0006 (dsr2) 0x0007 (dsr3) 0x0008 (dsr4) 0x0009 (dsr5) 0x000a (dsr6) 0x000b (dsr7) 76543210 r db7 db6 db5 db4 db3 db2 db1 db0 w reset: xxxxxxxx figure 14-34. data segment registers (dsr0?sr7) ?extended identi?r mapping table 14-31. dsr0?sr7 register field descriptions field description 7:0 db[7:0] data bits 7:0 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 554 freescale semiconductor 14.3.3.3 data length register (dlr) this register keeps the data length ?ld of the can frame. 14.3.3.4 transmit buffer priority register (tbpr) this register de?es the local priority of the associated message buffer. the local priority is used for the internal prioritization process of the mscan and is de?ed to be highest for the smallest binary number. the mscan implements the following internal prioritization mechanisms: all transmission buffers with a cleared txex ?g participate in the prioritization immediately before the sof (start of frame) is sent. the transmission buffer with the lowest local priority ?ld wins the prioritization. module base + 0x00xb 76543210 r dlc3 dlc2 dlc1 dlc0 w reset: xxxxxxxx = unused; always read ? figure 14-35. data length register (dlr) ?extended identi?r mapping table 14-32. dlr register field descriptions field description 3:0 dlc[3:0] data length code bits the data length code contains the number of bytes (data byte count) of the respective message. during the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 14-33 shows the effect of setting the dlc bits. table 14-33. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 555 in cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. read: anytime when txex ?g is set (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 14.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. write: anytime when txex ?g is set (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 14.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. 14.3.3.5 time stamp register (tsrh?srl) if the time bit is enabled, the mscan will write a time stamp to the respective registers in the active transmit or receive buffer right after the eof of a valid message on the can bus (see section 14.3.2.1, ?scan control register 0 (canctl0) ?. in case of a transmission, the cpu can only read the time stamp after the respective transmit buffer has been ?gged empty. the timer value, which is used for stamping, is taken from a free running internal can bit clock. a timer overrun is not indicated by the mscan. the timer is reset (all bits set to 0) during initialization mode. the cpu can only read the time stamp registers. module base + 0xxxxd 76543210 r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w reset: 00000000 figure 14-36. transmit buffer priority register (tbpr) module base + 0xxxxe 76543210 r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w reset: xxxxxxxx figure 14-37. time stamp register ?high byte (tsrh) module base + 0xxxxf 76543210 r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w reset: xxxxxxxx figure 14-38. time stamp register ?low byte (tsrl) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 556 freescale semiconductor read: anytime when txex ?g is set (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 14.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. write: unimplemented 14.4 functional description 14.4.1 general this section provides a complete functional description of the mscan. it describes each of the features and modes listed in the introduction. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 557 14.4.2 message storage figure 14-39. user model for message buffer organization mscan facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. mscan rx0 rx1 can receive / transmit engine cpu12 memory mapped i/o cpu bus mscan tx2 txe2 prio receiver transmitter rxbg txbg tx0 txe0 prio txbg tx1 prio txe1 txfg cpu bus rx2 rx3 rx4 rxf rxfg 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 558 freescale semiconductor 14.4.2.1 message transmit background modern application layer software is built upon two fundamental assumptions: any can node is able to send out a stream of scheduled messages without releasing the can bus between the two messages. such nodes arbitrate for the can bus immediately after sending the previous message and only release the can bus in case of lost arbitration. the internal message queue within any can node is organized such that the highest priority message is sent out ?st, if more than one message is ready to be sent. the behavior described in the bullets above cannot be achieved with a single transmit buffer. that buffer must be reloaded immediately after the previous message is sent. this loading process lasts a ?ite amount of time and must be completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the cpu. problems can arise if the sending of a message is ?ished while the cpu re-loads the second buffer. no buffer would then be ready for transmission, and the can bus would be released. at least three transmit buffers are required to meet the ?st of the above requirements under all circumstances. the mscan has three transmit buffers. the second requirement calls for some sort of internal prioritization which the mscan implements with the ?ocal priority?concept described in section 14.4.2.2, ?ransmit structures . 14.4.2.2 transmit structures the mscan triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. the three buffers are arranged as shown in figure 14-39 . all three buffers have a 13-byte data structure similar to the outline of the receive buffers (see section 14.3.3, ?rogrammers model of message storage ?. an additional section 14.3.3.4, ?ransmit buffer priority register (tbpr) contains an 8-bit local priority ?ld (prio) (see section 14.3.3.4, ?ransmit buffer priority register (tbpr) ?. the remaining two bytes are used for time stamping of a message, if required (see section 14.3.3.5, ?ime stamp register (tsrh?srl) ?. to transmit a message, the cpu must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (txex) ?g (see section 14.3.2.7, ?scan transmitter flag register (cantflg) ?. if a transmit buffer is available, the cpu must set a pointer to this buffer by writing to the cantbsel register (see section 14.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. this makes the respective buffer accessible within the cantxfg address space (see section 14.3.3, ?rogrammers model of message storage ?. the algorithmic feature associated with the cantbsel register simpli?s the transmit buffer selection. in addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. the cpu then stores the identi?r, the control bits, and the data content into one of the transmit buffers. finally, the buffer is ?gged as ready for transmission by clearing the associated txe ?g. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 559 the mscan then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated txe ?g. a transmit interrupt (see section 14.4.7.2, ?ransmit interrupt ? is generated 1 when txex is set and can be used to drive the application software to re-load the buffer. if more than one buffer is scheduled for transmission when the can bus becomes available for arbitration, the mscan uses the local priority setting of the three buffers to determine the prioritization. for this purpose, every transmit buffer has an 8-bit local priority ?ld (prio). the application software programs this ?ld when the message is set up. the local priority re?cts the priority of this particular message relative to the set of messages being transmitted from this node. the lowest binary value of the prio ?ld is de?ed to be the highest priority. the internal scheduling process takes place whenever the mscan arbitrates for the can bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (abtrq) (see section 14.3.2.9, ?scan transmitter message abort request register (cantarq) ?) the mscan then grants the request, if possible, by: 1. setting the corresponding abort acknowledge ?g (abtak) in the cantaak register. 2. setting the associated txe ?g to release the buffer. 3. generating a transmit interrupt. the transmit interrupt handler software can determine from the setting of the abtak ?g whether the message was aborted (abtak = 1) or sent (abtak = 0). 14.4.2.3 receive structures the received messages are stored in a ve stage input fifo. the ve message buffers are alternately mapped into a single memory area (see figure 14-39 ). the background receive buffer (rxbg) is exclusively associated with the mscan, but the foreground receive buffer (rxfg) is addressable by the cpu (see figure 14-39 ). this scheme simpli?s the handler software because only one address area is applicable for the receive process. all receive buffers have a size of 15 bytes to store the can control bits, the identi?r (standard or extended), the data contents, and a time stamp, if enabled (see section 14.3.3, ?rogrammers model of message storage ?. the receiver full ?g (rxf) (see section 14.3.2.5, ?scan receiver flag register (canrflg) ? signals the status of the foreground receive buffer. when the buffer contains a correctly received message with a matching identi?r, this ?g is set. on reception, each message is checked to see whether it passes the ?ter (see section 14.4.3, ?denti?r acceptance filter ? and simultaneously is written into the active rxbg. after successful reception of a valid message, the mscan shifts the content of rxbg into the receiver fifo 2 , sets the rxf ?g, and generates a receive interrupt (see section 14.4.7.3, ?eceive interrupt ? to the cpu 3 . the users receive handler must read the received message from the rxfg and then reset the rxf ?g to acknowledge the interrupt and to release the foreground buffer. a new message, which can follow immediately after the ifs 1. the transmit interrupt occurs only if not masked. a polling scheme can be applied on txex also. 2. only if the rxf ?g is not set. 3. the receive interrupt occurs only if not masked. a polling scheme can be applied on rxf also. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 560 freescale semiconductor ?ld of the can frame, is received into the next available rxbg. if the mscan receives an invalid message in its rxbg (wrong identi?r, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. the buffer will then not be shifted into the fifo. when the mscan module is transmitting, the mscan receives its own transmitted messages into the background receive buffer, rxbg, but does not shift it into the receiver fifo, generate a receive interrupt, or acknowledge its own messages on the can bus. the exception to this rule is in loopback mode (see section 14.3.2.2, ?scan control register 1 (canctl1) ? where the mscan treats its own messages exactly like all other incoming messages. the mscan receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan must be prepared to become a receiver. an overrun condition occurs when all receive message buffers in the fifo are ?led with correctly received messages with accepted identi?rs and another message is correctly received from the can bus with an accepted identi?r. the latter message is discarded and an error interrupt with overrun indication is generated if enabled (see section 14.4.7.5, ?rror interrupt ?. the mscan remains able to transmit messages while the receiver fifo being ?led, but all incoming messages are discarded. as soon as a receive buffer in the fifo is available again, new valid messages will be accepted. 14.4.3 identi?r acceptance filter the mscan identi?r acceptance registers (see section 14.3.2.12, ?scan identi?r acceptance control register (canidac) ? de?e the acceptable patterns of the standard or extended identi?r (id[10:0] or id[28:0]). any of these bits can be marked ?ont care?in the mscan identi?r mask registers (see section 14.3.2.18, ?scan identi?r mask registers (canidmr0?anidmr7) ?. a ?ter hit is indicated to the application software by a set receive buffer full ?g (rxf = 1) and three bits in the canidac register (see section 14.3.2.12, ?scan identi?r acceptance control register (canidac) ?. these identi?r hit ?gs (idhit[2:0]) clearly identify the ?ter section that caused the acceptance. they simplify the application softwares task to identify the cause of the receiver interrupt. if more than one hit occurs (two or more ?ters match), the lower hit has priority. a very ?xible programmable generic identi?r acceptance ?ter has been introduced to reduce the cpu interrupt loading. the ?ter is programmable to operate in four different modes (see bosch can 2.0a/b protocol speci?ation): two identi?r acceptance ?ters, each to be applied to: the full 29 bits of the extended identi?r and to the following bits of the can 2.0b frame: remote transmission request (rtr) identi?r extension (ide) substitute remote request (srr) the 11 bits of the standard identi?r plus the rtr and ide bits of the can 2.0a/b messages 1 . this mode implements two ?ters for a full length can 2.0b compliant extended identi?r. figure 14-40 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces a ?ter 0 hit. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces a ?ter 1 hit. 1.although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 561 four identi?r acceptance ?ters, each to be applied to a) the 14 most signi?ant bits of the extended identi?r plus the srr and ide bits of can 2.0b messages or b) the 11 bits of the standard identi?r, the rtr and ide bits of can 2.0a/b messages. figure 14-41 shows how the ?st 32-bit ?ter bank (canidar0?anida3, canidmr0?canidmr) produces ?ter 0 and 1 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 2 and 3 hits. eight identi?r acceptance ?ters, each to be applied to the ?st 8 bits of the identi?r. this mode implements eight independent ?ters for the ?st 8 bits of a can 2.0a/b compliant standard identi?r or a can 2.0b compliant extended identi?r. figure 14-42 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces ?ter 0 to 3 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 4 to 7 hits. closed ?ter. no can message is copied into the foreground buffer rxfg, and the rxf ?g is never set. figure 14-40. 32-bit maskable identi?r acceptance filter id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 0 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 562 freescale semiconductor figure 14-41. 16-bit maskable identi?r acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 id accepted (filter 0 hit) ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 1 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 563 figure 14-42. 8-bit maskable identi?r acceptance filters can 2.0b extended identi?r can 2.0a/b standard identi?r ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 564 freescale semiconductor 14.4.3.1 protocol violation protection the mscan protects the user from accidentally violating the can protocol through programming errors. the protection logic implements the following features: the receive and transmit error counters cannot be written or otherwise manipulated. all registers which control the con?uration of the mscan cannot be modi?d while the mscan is on-line. the mscan has to be in initialization mode. the corresponding initrq/initak handshake bits in the canctl0/canctl1 registers (see section 14.3.2.1, ?scan control register 0 (canctl0) ? serve as a lock to protect the following registers: mscan control 1 register (canctl1) mscan bus timing registers 0 and 1 (canbtr0, canbtr1) mscan identi?r acceptance control register (canidac) mscan identi?r acceptance registers (canidar0?anidar7) mscan identi?r mask registers (canidmr0?anidmr7) the txcan pin is immediately forced to a recessive state when the mscan goes into the power down mode or initialization mode (see section 14.4.5.6, ?scan power down mode , and section 14.4.5.5, ?scan initialization mode ?. the mscan enable bit (cane) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the mscan. 14.4.3.2 clock system figure 14-43 shows the structure of the mscan clock generation circuitry. figure 14-43. mscan clocking scheme the clock source bit (clksrc) in the canctl1 register ( 14.3.2.2/14-526 ) de?es whether the internal canclk is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. the clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the can protocol are met. additionally, for high can bus rates (1 mbps), a 45% to 55% duty cycle of the clock is required. bus clock oscillator clock mscan canclk clksrc clksrc prescaler (1 .. 64) time quanta clock (tq) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 565 if the bus clock is generated from a pll, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster can bus rates. for microcontrollers without a clock and reset generator (crg), canclk is driven from the crystal oscillator (oscillator clock). a programmable prescaler generates the time quanta (tq) clock from canclk. a time quantum is the atomic unit of time handled by the mscan. eqn. 14-2 a bit time is subdivided into three segments as described in the bosch can speci?ation. (see figure 14-44 ): sync_seg: this segment has a ?ed length of one time quantum. signal edges are expected to happen within this section. time segment 1: this segment includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the parameter tseg1 to consist of 4 to 16 time quanta. time segment 2: this segment represents the phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. eqn. 14-3 figure 14-44. segments within the bit time tq f canclk prescaler value ( ) ---------------------------------------------------- -- = bit rate f tq number of time quanta () -------------------------------------------------------------------------------- - = sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) transmit point 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 566 freescale semiconductor the synchronization jump width (see the bosch can speci?ation for details) can be programmed in a range of 1 to 4 time quanta by setting the sjw parameter. the sync_seg, tseg1, tseg2, and sjw parameters are set by programming the mscan bus timing registers (canbtr0, canbtr1) (see section 14.3.2.3, ?scan bus timing register 0 (canbtr0) and section 14.3.2.4, ?scan bus timing register 1 (canbtr1) ?. table 14-35 gives an overview of the can compliant segment settings and the related parameter values. note it is the users responsibility to ensure the bit time settings are in compliance with the can standard. 14.4.4 modes of operation 14.4.4.1 normal modes the mscan module behaves as described within this speci?ation in all normal system operation modes. 14.4.4.2 special modes the mscan module behaves as described within this speci?ation in all special system operation modes. table 14-34. time segment syntax syntax description sync_seg system expects transitions to occur on the can bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node in receive mode samples the can bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 14-35. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchronization jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 567 14.4.4.3 emulation modes in all emulation modes, the mscan module behaves just like normal system operation modes as described within this speci?ation. 14.4.4.4 listen-only mode in an optional can bus monitoring mode (listen-only), the can node is able to receive valid data frames and valid remote frames, but it sends only ?ecessive?bits on the can bus. in addition, it cannot start a transmision. if the mac sub-layer is required to send a ?ominant bit (ack bit, overload ?g, or active error ?g), the bit is rerouted internally so that the mac sub-layer monitors this ?ominant bit, although the can bus may remain in recessive state externally. 14.4.4.5 security modes the mscan module has no security features. 14.4.5 low-power options if the mscan is disabled (cane = 0), the mscan clocks are stopped for power saving. if the mscan is enabled (cane = 1), the mscan has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. in sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the cpu side. in power down mode, all clocks are stopped and no power is consumed. table 14-36 summarizes the combinations of mscan and cpu modes. a particular combination of modes is entered by the given settings on the cswai and slprq/slpak bits. for all modes, an mscan wake-up interrupt can occur only if the mscan is in sleep mode (slprq = 1 and slpak = 1), wake-up functionality is enabled (wupe = 1), and the wake-up interrupt is enabled (wupie = 1). 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 568 freescale semiconductor 14.4.5.1 operation in run mode as shown in table 14-36 , only mscan sleep mode is available as low power option when the cpu is in run mode. 14.4.5.2 operation in wait mode the wai instruction puts the mcu in a low power consumption stand-by mode. if the cswai bit is set, additional power can be saved in power down mode because the cpu clocks are stopped. after leaving this power down mode, the mscan restarts its internal controllers and enters normal mode again. while the cpu is in wait mode, the mscan can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). the mscan can also operate in any of the low-power modes depending on the values of the slprq/slpak and cswai bits as seen in table 14-36 . 14.4.5.3 operation in stop mode the stop instruction puts the mcu in a low power consumption stand-by mode. in stop mode, the mscan is set in power down mode regardless of the value of the slprq/slpak and cswai bits ( table 14-36 ). 14.4.5.4 mscan sleep mode the cpu can request the mscan to enter this low power mode by asserting the slprq bit in the canctl0 register. the time when the mscan enters sleep mode depends on a ?ed synchronization delay and its current activity: table 14-36. cpu vs. mscan operating modes cpu mode mscan mode normal reduced power consumption sleep power down disabled (cane=0) run cswai = x 1 slprq = 0 slpak = 0 1 ??means don? care. cswai = x slprq = 1 slpak = 1 cswai = x slprq = x slpak = x wait cswai = 0 slprq = 0 slpak = 0 cswai = 0 slprq = 1 slpak = 1 cswai = 1 slprq = x slpak = x cswai = x slprq = x slpak = x stop cswai = x slprq = x slpak = x cswai = x slprq = x slpak = x 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 569 if there are one or more message buffers scheduled for transmission (txex = 0), the mscan will continue to transmit until all transmit message buffers are empty (txex = 1, transmitted successfully or aborted) and then goes into sleep mode. if the mscan is receiving, it continues to receive and goes into sleep mode as soon as the can bus next becomes idle. if the mscan is neither transmitting nor receiving, it immediately goes into sleep mode. figure 14-45. sleep request / acknowledge cycle note the application software must avoid setting up a transmission (by clearing one or more txex ?g(s)) and immediately request sleep mode (by setting slprq). whether the mscan starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. if sleep mode is active, the slprq and slpak bits are set ( figure 14-45 ). the application software must use slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode (slprq = 1 and slpak = 1), the mscan stops its internal clocks. however, clocks that allow register accesses from the cpu side continue to run. if the mscan is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. the txcan pin remains in a recessive state. if rxf = 1, the message can be read and rxf can be cleared. shifting a new message into the foreground buffer of the receiver fifo (rxfg) does not take place while in sleep mode. it is possible to access the transmit buffers and to clear the associated txe ?gs. no message abort takes place while in sleep mode. if the wupe bit in canctl0 is not asserted, the mscan will mask any activity it detects on can. the rxcan pin is therefore held internally in a recessive state. this locks the mscan in sleep mode. wupe must be set before entering sleep mode to take effect. the mscan is able to leave sleep mode (wake up) only when: can bus activity occurs and wupe = 1 sync sync bus cloc k domain can cloc k domain mscan in sleep mode cpu sleep request slprq flag slpak flag slprq sync. slpak sync. slprq slpak 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 570 freescale semiconductor or the cpu clears the slprq bit note the cpu cannot clear the slprq bit before sleep mode (slprq = 1 and slpak = 1) is active. after wake-up, the mscan waits for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, if the mscan is woken-up by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions will be executed upon wake-up; copying of rxbg into rxfg, message aborts and message transmissions. if the mscan remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 571 14.4.5.5 mscan initialization mode in initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the can bus is lost, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations, the mscan immediately drives the txcan pin into a recessive state. note the user is responsible for ensuring that the mscan is not active when initialization mode is entered. the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before setting the initrq bit in the canctl0 register. otherwise, the abort of an on-going message can cause an error condition and can impact other can bus devices. in initialization mode, the mscan is stopped. however, interface registers remain accessible. this mode is used to reset the canctl0, canrflg, canrier, cantflg, cantier, cantarq, cantaak, and cantbsel registers to their default values. in addition, the mscan enables the con?uration of the canbtr0, canbtr1 bit timing registers; canidac; and the canidar, canidmr message ?ters. see section 14.3.2.1, ?scan control register 0 (canctl0) , for a detailed description of the initialization mode. figure 14-46. initialization request/acknowledge cycle due to independent clock domains within the mscan, initrq must be synchronized to all domains by using a special handshake mechanism. this handshake causes additional synchronization delay (see section figure 14-46., ?nitialization request/acknowledge cycle ?. if there is no message transfer ongoing on the can bus, the minimum delay will be two additional bus clocks and three additional can clocks. when all parts of the mscan are in initialization mode, the initak ?g is set. the application software must use initak as a handshake indication for the request (initrq) to go into initialization mode. note the cpu cannot clear initrq before initialization mode (initrq = 1 and initak = 1) is active. sync sync bus cloc k domain can cloc k domain cpu init request init flag initak flag initrq sync. initak sync. initrq initak 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 572 freescale semiconductor 14.4.5.6 mscan power down mode the mscan is in power down mode ( table 14-36 ) when cpu is in stop mode or cpu is in wait mode and the cswai bit is set when entering the power down mode, the mscan immediately stops all ongoing transmissions and receptions, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations to the above rule, the mscan immediately drives the txcan pin into a recessive state. note the user is responsible for ensuring that the mscan is not active when power down mode is entered. the recommended procedure is to bring the mscan into sleep mode before the stop or wai instruction (if cswai is set) is executed. otherwise, the abort of an ongoing message can cause an error condition and impact other can bus devices. in power down mode, all clocks are stopped and no registers can be accessed. if the mscan was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. this causes some ?ed delay before the module enters normal mode again. 14.4.5.7 programmable wake-up function the mscan can be programmed to wake up the mscan as soon as can bus activity is detected (see control bit wupe in section 14.3.2.1, ?scan control register 0 (canctl0) ?. the sensitivity to existing can bus action can be modi?d by applying a low-pass ?ter function to the rxcan input line while in sleep mode (see control bit wupm in section 14.3.2.2, ?scan control register 1 (canctl1) ?. this feature can be used to protect the mscan from wake-up due to short glitches on the can bus lines. such glitches can result from?or example?lectromagnetic interference within noisy environments. 14.4.6 reset initialization the reset state of each individual bit is listed in section 14.3.2, ?egister descriptions , which details all the registers and their bit-?lds. 14.4.7 interrupts this section describes all interrupts originated by the mscan. it documents the enable bits and generated ?gs. each interrupt is listed and described separately. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 573 14.4.7.1 description of interrupt operation the mscan supports four interrupt vectors (see table 14-37 ), any of which can be individually masked (for details see sections from section 14.3.2.6, ?scan receiver interrupt enable register (canrier) , to section 14.3.2.8, ?scan transmitter interrupt enable register (cantier) ?. note the dedicated interrupt vector addresses are de?ed in the resets and interrupts chapter. 14.4.7.2 transmit interrupt at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. the txex ?g of the empty message buffer is set. 14.4.7.3 receive interrupt a message is successfully received and shifted into the foreground buffer (rxfg) of the receiver fifo. this interrupt is generated immediately after receiving the eof symbol. the rxf ?g is set. if there are multiple messages in the receiver fifo, the rxf ?g is set as soon as the next message is shifted to the foreground buffer. 14.4.7.4 wake-up interrupt a wake-up interrupt is generated if activity on the can bus occurs during mscan internal sleep mode. wupe (see section 14.3.2.1, ?scan control register 0 (canctl0) ? must be enabled. 14.4.7.5 error interrupt an error interrupt is generated if an overrun of the receiver fifo, error, warning, or bus-off condition occurrs. section 14.3.2.5, ?scan receiver flag register (canrflg) indicates one of the following conditions: overrun an overrun condition of the receiver fifo as described in section 14.4.2.3, ?eceive structures , occurred. can status change ?the actual value of the transmit and receive error counters control the can bus state of the mscan. as soon as the error counters skip into a critical range (tx/rx-warning, tx/rx-error, bus-off) the mscan ?gs an error condition. the status change, which caused the error condition, is indicated by the tstat and rstat ?gs (see table 14-37. interrupt vectors interrupt source ccr mask local enable wake-up interrupt (wupif) i bit canrier (wupie) error interrupts interrupt (cscif, ovrif) i bit canrier (cscie, ovrie) receive interrupt (rxf) i bit canrier (rxfie) transmit interrupts (txe[2:0]) i bit cantier (txeie[2:0]) 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 574 freescale semiconductor section 14.3.2.5, ?scan receiver flag register (canrflg) and section 14.3.2.6, ?scan receiver interrupt enable register (canrier) ?. 14.4.7.6 interrupt acknowledge interrupts are directly associated with one or more status ?gs in either the section 14.3.2.5, ?scan receiver flag register (canrflg) ?or the section 14.3.2.7, ?scan transmitter flag register (cantflg) . interrupts are pending as long as one of the corresponding ?gs is set. the ?gs in canrflg and cantflg must be reset within the interrupt handler to handshake the interrupt. the ?gs are reset by writing a 1 to the corresponding bit position. a ?g cannot be cleared if the respective condition prevails. note it must be guaranteed that the cpu clears only the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt ?gs. these instructions may cause accidental clearing of interrupt ?gs which are set after entering the current interrupt service routine. 14.4.7.7 recovery from stop or wait the mscan can recover from stop or wait via the wake-up interrupt. this interrupt can only occur if the mscan was in sleep mode (slprq = 1 and slpak = 1) before entering power down mode, the wake-up option is enabled (wupe = 1), and the wake-up interrupt is enabled (wupie = 1). 14.5 initialization/application information 14.5.1 mscan initialization the procedure to initially start up the mscan module out of reset is as follows: 1. assert cane 2. write to the con?uration registers in initialization mode 3. clear initrq to leave initialization mode and enter normal mode if the con?uration of registers which are writable in initialization mode needs to be changed only when the mscan module is in normal mode: 1. bring the module into sleep mode by setting slprq and awaiting slpak to assert after the can bus becomes idle. 2. enter initialization mode: assert initrq and await initak 3. write to the con?uration registers in initialization mode 4. clear initrq to leave initialization mode and continue in normal mode 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 575 14.5.2 bus-off recovery the bus-off recovery is user con?urable. the bus-off state can either be left automatically or on user request. for reasons of backwards compatibility, the mscan defaults to automatic recovery after reset. in this case, the mscan will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the can bus (see the bosch can speci?ation for details). if the mscan is con?ured for user request (borm set in section 14.3.2.2, ?scan control register 1 (canctl1) ?, the recovery from bus-off starts after both independent events have become true: 128 occurrences of 11 consecutive recessive bits on the can bus have been monitored bohold in section 14.3.2.14, ?scan miscellaneous register (canmisc) has been cleared by the user these two events may occur in any order. 4 .com u datasheet
chapter 14 freescales scalable controller area network (mscanv3) MC9S12XHZ512 data sheet, rev. 1.02 576 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 577 chapter 15 serial communication interface (sciv5) 15.1 introduction this block guide provides an overview of the serial communication interface (sci) module. the sci allows asynchronous serial communications with peripheral devices and other cpus. 15.1.1 glossary ir: infrared irda: infrared design associate irq: interrupt request lin: local interconnect network lsb: least signi?ant bit msb: most signi?ant bit nrz: non-return-to-zero rzi: return-to-zero-inverted rxd: receive pin sci : serial communication interface txd: transmit pin 15.1.2 features the sci includes these distinctive features: full-duplex or single-wire operation standard mark/space non-return-to-zero (nrz) format selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse widths 13-bit baud rate selection programmable 8-bit or 9-bit data format separately enabled transmitter and receiver programmable polarity for transmitter and receiver 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 578 freescale semiconductor programmable transmitter output parity two receiver wakeup methods: idle line wakeup address mark wakeup interrupt-driven operation with eight flags: transmitter empty transmission complete receiver full idle receiver input receiver overrun noise error framing error parity error receive wakeup on active edge transmit collision detect supporting lin break detect supporting lin receiver framing error detection hardware parity checking 1/16 bit-time noise detection 15.1.3 modes of operation the sci functions the same in normal, special, and emulation modes. it has two low power modes, wait and stop modes. run mode wait mode stop mode 15.1.4 block diagram figure 15-1 is a high level block diagram of the sci module, showing the interaction of various function blocks. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 579 figure 15-1. sci block diagram sci data register rxd data in data out txd receive shift register infrared decoder receive & wakeup control data format control transmit control baud rate generator bus clock 1/16 transmit shift register sci data register receive interrupt generation transmit interrupt generation infrared encoder idle rdrf/or tc tdre brkd berr rxedg sci interrupt request 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 580 freescale semiconductor 15.2 external signal description the sci module has a total of two external pins. 15.2.1 txd ?transmit pin the txd pin transmits sci (standard or infrared) data. it will idle high in either mode and is high impedance anytime the transmitter is disabled. 15.2.2 rxd ?receive pin the rxd pin receives sci (standard or infrared) data. an idle line is detected as a line high. this input is ignored when the receiver is disabled and should be terminated to a known voltage. 15.3 memory map and register de?ition this section provides a detailed description of all the sci registers. 15.3.1 module memory map and register de?ition the memory map for the sci module is given below in figure 15-2 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the sci module and the address offset for each register. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 581 15.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. writes to a reserved register locations do not have any effect and reads of these locations return a zero. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 6 5 4 3 2 1 bit 0 scibdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w scibdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w scicr1 1 r loops sciswai rsrc m wake ilt pe pt w sciasr1 2 r rxedgif 0000 berrv berrif bkdif w sciacr1 2 r rxedgie 00000 berrie bkdie w sciacr2 2 r00000 berrm1 berrm0 bkdfe w scicr2 r tie tcie rie ilie te re rwu sbk w scisr1 r tdre tc rdrf idle or nf fe pf w scisr2 r amap 00 txpol rxpol brk13 txdir raf w scidrh r r8 t8 000000 w scidrl r r7 r6 r5 r4 r3 r2 r1 r0 wt7t6t5t4t3t2t1t0 1.these registers are accessible if the amap bit in the scisr2 register is set to zero. 2,these registers are accessible if the amap bit in the scisr2 register is set to one. = unimplemented or reserved figure 15-2. sci register summary 1 those registers are accessible if the amap bit in the scisr2 register is set to zero 2 those registers are accessible if the amap bit in the scisr2 register is set to one 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 582 freescale semiconductor 15.3.2.1 sci baud rate registers (scibdh, scibdl) read: anytime, if amap = 0. if only scibdh is written to, a read will not return the correct data until scibdl is written to as well, following a write to scibdh. write: anytime, if amap = 0. note those two registers are only visible in the memory map if amap = 0 (reset condition). the sci baud rate register is used by to determine the baud rate of the sci, and to control the infrared modulation/demodulation submodule. 76543210 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset 0 0 0 00000 figure 15-3. sci baud rate register (scibdh) 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset 0 0 0 00000 figure 15-4. sci baud rate register (scibdl) table 15-1. scibdh and scibdl field descriptions field description 7 iren infrared enable bit ?this bit enables/disables the infrared modulation/demodulation submodule. 0 ir disabled 1 ir enabled 6:5 tnp[1:0] transmitter narrow pulse bits these bits enable whether the sci transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. see table 15-2 . 4:0 7:0 sbr[12:0] sci baud rate bits ?the baud rate for the sci is determined by the bits in this register. the baud rate is calculated two different ways depending on the state of the iren bit. the formulas for calculating the baud rate are: when iren = 0 then, sci baud rate = sci bus clock / (16 x sbr[12:0]) when iren = 1 then, sci baud rate = sci bus clock / (32 x sbr[12:1]) note: the baud rate generator is disabled after reset and not started until the te bit or the re bit is set for the ?st time. the baud rate generator is disabled when (sbr[12:0] = 0 and iren = 0) or (sbr[12:1] = 0 and iren = 1). note: writing to scibdh has no effect without writing to scibdl, because writing to scibdh puts the data in a temporary location until scibdl is written to. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 583 15.3.2.2 sci control register 1 (scicr1) read: anytime, if amap = 0. write: anytime, if amap = 0. note this register is only visible in the memory map if amap = 0 (reset condition). table 15-2. irsci transmit pulse width tnp[1:0] narrow pulse width 11 1/4 10 1/32 01 1/16 00 3/16 76543210 r loops sciswai rsrc m wake ilt pe pt w reset 0 0 0 00000 figure 15-5. sci control register 1 (scicr1) table 15-3. scicr1 field descriptions field description 7 loops loop select bit loops enables loop operation. in loop operation, the rxd pin is disconnected from the sci and the transmitter output is internally connected to the receiver input. both the transmitter and the receiver must be enabled to use the loop function. 0 normal operation enabled 1 loop operation enabled the receiver input is determined by the rsrc bit. 6 sciswai sci stop in wait mode bit ?sciswai disables the sci in wait mode. 0 sci enabled in wait mode 1 sci disabled in wait mode 5 rsrc receiver source bit ?when loops = 1, the rsrc bit determines the source for the receiver shift register input. see table 15-4 . 0 receiver input internally connected to transmitter output 1 receiver input connected externally to transmitter 4 m data format mode bit ?mode determines whether data characters are eight or nine bits long. 0 one start bit, eight data bits, one stop bit 1 one start bit, nine data bits, one stop bit 3 wake wakeup condition bit wake determines which condition wakes up the sci: a logic 1 (address mark) in the most signi?ant bit position of a received data character or an idle condition on the rxd pin. 0 idle line wakeup 1 address mark wakeup 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 584 freescale semiconductor 2 ilt idle line type bit ?ilt determines when the receiver starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 idle character bit count begins after start bit 1 idle character bit count begins after stop bit 1 pe parity enable bit pe enables the parity function. when enabled, the parity function inserts a parity bit in the most signi?ant bit position. 0 parity function disabled 1 parity function enabled 0 pt parity type bit pt determines whether the sci generates and checks for even parity or odd parity. with even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. with odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 1 even parity 1 odd parity table 15-4. loop functions loops rsrc function 0 x normal operation 1 0 loop mode with transmitter output internally connected to receiver input 1 1 single-wire mode with txd pin connected to receiver input table 15-3. scicr1 field descriptions (continued) field description 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 585 15.3.2.3 sci alternative status register 1 (sciasr1) read: anytime, if amap = 1 write: anytime, if amap = 1 76543210 r rxedgif 0 0 0 0 berrv berrif bkdif w reset 0 0 0 00000 = unimplemented or reserved figure 15-6. sci alternative status register 1 (sciasr1) table 15-5. sciasr1 field descriptions field description 7 rxedgif receive input active edge interrupt flag ?rxedgif is asserted, if an active edge (falling if rxpol = 0, rising if rxpol = 1) on the rxd input occurs. rxedgif bit is cleared by writing a ??to it. 0 no active receive on the receive input has occurred 1 an active edge on the receive input has occurred 2 berrv bit error value berrv re?cts the state of the rxd input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. the value is only meaningful, if berrif = 1. 0 a low input was sampled, when a high was expected 1 a high input reassembled, when a low was expected 1 berrif bit error interrupt flag ?berrif is asserted, when the bit error detect circuitry is enabled and if the value sampled at the rxd input does not match the transmitted value. if the berrie interrupt enable bit is set an interrupt will be generated. the berrif bit is cleared by writing a ??to it. 0 no mismatch detected 1 a mismatch has occurred 0 bkdif break detect interrupt flag bkdif is asserted, if the break detect circuitry is enabled and a break signal is received. if the bkdie interrupt enable bit is set an interrupt will be generated. the bkdif bit is cleared by writing a ??to it. 0 no break signal was received 1 a break signal was received 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 586 freescale semiconductor 15.3.2.4 sci alternative control register 1 (sciacr1) read: anytime, if amap = 1 write: anytime, if amap = 1 76543210 r rxedgie 00000 berrie bkdie w reset 0 0 0 00000 = unimplemented or reserved figure 15-7. sci alternative control register 1 (sciacr1) table 15-6. sciacr1 field descriptions field description 7 rsedgie receive input active edge interrupt enable rxedgie enables the receive input active edge interrupt ?g, rxedgif, to generate interrupt requests. 0 rxedgif interrupt requests disabled 1 rxedgif interrupt requests enabled 1 berrie bit error interrupt enable ?berrie enables the bit error interrupt ?g, berrif, to generate interrupt requests. 0 berrif interrupt requests disabled 1 berrif interrupt requests enabled 0 bkdie break detect interrupt enable ?bkdie enables the break detect interrupt ?g, bkdif, to generate interrupt requests. 0 bkdif interrupt requests disabled 1 bkdif interrupt requests enabled 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 587 15.3.2.5 sci alternative control register 2 (sciacr2) read: anytime, if amap = 1 write: anytime, if amap = 1 76543210 r00000 berrm1 berrm0 bkdfe w reset 0 0 0 00000 = unimplemented or reserved figure 15-8. sci alternative control register 2 (sciacr2) table 15-7. sciacr2 field descriptions field description 2:1 berrm[1:0] bit error mode ?those two bits determines the functionality of the bit error detect feature. see table 15-8 . 0 bkdfe break detect feature enable ?bkdfe enables the break detect circuitry. 0 break detect circuit disabled 1 break detect circuit enabled table 15-8. bit error mode coding berrm1 berrm0 function 0 0 bit error detect circuit is disabled 0 1 receive input sampling occurs during the 9th time tick of a transmitted bit (refer to figure 15-19 ) 1 0 receive input sampling occurs during the 13th time tick of a transmitted bit (refer to figure 15-19 ) 1 1 reserved 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 588 freescale semiconductor 15.3.2.6 sci control register 2 (scicr2) read: anytime write: anytime 76543210 r tie tcie rie ilie te re rwu sbk w reset 0 0 0 00000 figure 15-9. sci control register 2 (scicr2) table 15-9. scicr2 field descriptions field description 7 tie transmitter interrupt enable bit ?tie enables the transmit data register empty ?g, tdre, to generate interrupt requests. 0 tdre interrupt requests disabled 1 tdre interrupt requests enabled 6 tcie transmission complete interrupt enable bit tcie enables the transmission complete ?g, tc, to generate interrupt requests. 0 tc interrupt requests disabled 1 tc interrupt requests enabled 5 rie receiver full interrupt enable bit rie enables the receive data register full ?g, rdrf, or the overrun ?g, or, to generate interrupt requests. 0 rdrf and or interrupt requests disabled 1 rdrf and or interrupt requests enabled 4 ilie idle line interrupt enable bit ?ilie enables the idle line ?g, idle, to generate interrupt requests. 0 idle interrupt requests disabled 1 idle interrupt requests enabled 3 te transmitter enable bit ?te enables the sci transmitter and con?ures the txd pin as being controlled by the sci. the te bit can be used to queue an idle preamble. 0 transmitter disabled 1 transmitter enabled 2 re receiver enable bit ?re enables the sci receiver. 0 receiver disabled 1 receiver enabled 1 rwu receiver wakeup bit ?standby state 0 normal operation. 1 rwu enables the wakeup function and inhibits further receiver interrupt requests. normally, hardware wakes the receiver by automatically clearing rwu. 0 sbk send break bit ?toggling sbk sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if brk13 is set). toggling implies clearing the sbk bit before the break character has ?ished transmitting. as long as sbk is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 no break characters 1 transmit break characters 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 589 15.3.2.7 sci status register 1 (scisr1) the scisr1 and scisr2 registers provides inputs to the mcu for generation of sci interrupts. also, these registers can be polled by the mcu to check the status of these bits. the ?g-clearing procedures require that the status register be read followed by a read or write to the sci data register.it is permissible to execute other instructions between the two steps as long as it does not compromise the handling of i/o, but the order of operations is important for ?g clearing. read: anytime write: has no meaning or effect 76543210 r tdre tc rdrf idle or nf fe pf w reset 1 1 0 00000 = unimplemented or reserved figure 15-10. sci status register 1 (scisr1) table 15-10. scisr1 field descriptions field description 7 tdre transmit data register empty flag ?tdre is set when the transmit shift register receives a byte from the sci data register. when tdre is 1, the transmit data register (scidrh/l) is empty and can receive a new value to transmit.clear tdre by reading sci status register 1 (scisr1), with tdre set and then writing to sci data register low (scidrl). 0 no byte transferred to transmit shift register 1 byte transferred to transmit shift register; transmit data register empty 6 tc transmit complete flag tc is set low when there is a transmission in progress or when a preamble or break character is loaded. tc is set high when the tdre ?g is set and no data, preamble, or break character is being transmitted.when tc is set, the txd pin becomes idle (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data register low (scidrl). tc is cleared automatically when data, preamble, or break is queued and ready to be sent. tc is cleared in the event of a simultaneous set and clear of the tc ?g (transmission not complete). 0 transmission in progress 1 no transmission in progress 5 rdrf receive data register full flag rdrf is set when the data in the receive shift register transfers to the sci data register. clear rdrf by reading sci status register 1 (scisr1) with rdrf set and then reading sci data register low (scidrl). 0 data not available in sci data register 1 received data available in sci data register 4 idle idle line flag idle is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m =1) appear on the receiver input. once the idle ?g is cleared, a valid frame must again set the rdrf ?g before an idle condition can set the idle ?g.clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl). 0 receiver input is either active now or has never become active since the idle ?g was last cleared 1 receiver input has become idle note: when the receiver wakeup bit (rwu) is set, an idle line condition does not set the idle ?g. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 590 freescale semiconductor 3 or overrun flag ?or is set when software fails to read the sci data register before the receive shift register receives the next frame. the or bit is set immediately after the stop bit has been completely received for the second frame. the data in the shift register is lost, but the data already in the sci data registers is not affected. clear or by reading sci status register 1 (scisr1) with or set and then reading sci data register low (scidrl). 0 no overrun 1 overrun note: or ?g may read back as set when rdrf ?g is clear. this may happen if the following sequence of events occurs: 1. after the ?st frame is received, read status register scisr1 (returns rdrf set and or ?g clear); 2. receive second frame without reading the ?st frame in the data register (the second frame is not received and or ?g is set); 3. read data register scidrl (returns ?st frame and clears rdrf ?g in the status register); 4. read status register scisr1 (returns rdrf clear and or set). event 3 may be at exactly the same time as event 2 or any time after. when this happens, a dummy scidrl read following event 4 will be required to clear the or ?g if further frames are to be received. 2 nf noise flag nf is set when the sci detects noise on the receiver input. nf bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. clear nf by reading sci status register 1(scisr1), and then reading sci data register low (scidrl). 0 no noise 1 noise 1 fe framing error flag fe is set when a logic 0 is accepted as the stop bit. fe bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading sci status register 1 (scisr1) with fe set and then reading the sci data register low (scidrl). 0 no framing error 1 framing error 0 pf parity error flag pf is set when the parity enable bit (pe) is set and the parity of the received data does not match the parity type bit (pt). pf bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. clear pf by reading sci status register 1 (scisr1), and then reading sci data register low (scidrl). 0 no parity error 1 parity error table 15-10. scisr1 field descriptions (continued) field description 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 591 15.3.2.8 sci status register 2 (scisr2) read: anytime write: anytime 76543210 r amap 00 txpol rxpol brk13 txdir raf w reset 0 0 0 00000 = unimplemented or reserved figure 15-11. sci status register 2 (scisr2) table 15-11. scisr2 field descriptions field description 7 amap alternative map this bit controls which registers sharing the same address space are accessible. in the reset condition the sci behaves as previous versions. setting amap=1 allows the access to another set of control and status registers and hides the baud rate and sci control register 1. 0 the registers labelled scibdh (0x0000),scibdl (0x0001), scicr1 (0x0002) are accessible 1 the registers labelled sciasr1 (0x0000),sciacr1 (0x0001), sciacr2 (0x00002) are accessible 4 txpol transmit polarity this bit control the polarity of the transmitted data. in nrz format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 normal polarity 1 inverted polarity 3 rxpol receive polarity ?this bit control the polarity of the received data. in nrz format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 normal polarity 1 inverted polarity 2 brk13 break transmit character length this bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. the detection of a framing error is not affected by this bit. 0 break character is 10 or 11 bit long 1 break character is 13 or 14 bit long 1 txdir transmitter pin data direction in single-wire mode ?this bit determines whether the txd pin is going to be used as an input or output, in the single-wire mode of operation. this bit is only relevant in the single-wire mode of operation. 0 txd pin to be used as an input in single-wire mode 1 txd pin to be used as an output in single-wire mode 0 raf receiver active flag raf is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. raf is cleared when the receiver detects an idle character. 0 no reception in progress 1 reception in progress 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 592 freescale semiconductor 15.3.2.9 sci data registers (scidrh, scidrl) read: anytime; reading accesses sci receive data register write: anytime; writing accesses sci transmit data register; writing to r8 has no effect note if the value of t8 is the same as in the previous transmission, t8 does not have to be rewritten.the same value is transmitted until t8 is rewritten in 8-bit data format, only sci data register low (scidrl) needs to be accessed. when transmitting in 9-bit data format and using 8-bit write instructions, write ?st to sci data register high (scidrh), then scidrl. 76543210 rr8 t8 000000 w reset 0 0 0 00000 = unimplemented or reserved figure 15-12. sci data registers (scidrh) 76543210 rr7r6r5r4r3r2r1r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 00000 figure 15-13. sci data registers (scidrl) table 15-12. scidrh and scidrl field descriptions field description scidrh 7 r8 received bit 8 ?r8 is the ninth data bit received when the sci is con?ured for 9-bit data format (m = 1). scidrh 6 t8 transmit bit 8 ?t8 is the ninth data bit transmitted when the sci is con?ured for 9-bit data format (m = 1). scidrl 7:0 r[7:0] t[7:0] r7:r0 ?received bits seven through zero for 9-bit or 8-bit data formats t7:t0 ?transmit bits seven through zero for 9-bit or 8-bit formats 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 593 15.4 functional description this section provides a complete functional description of the sci block, detailing the operation of the design from the end user perspective in a number of subsections. figure 15-14 shows the structure of the sci module. the sci allows full duplex, asynchronous, serial communication between the cpu and remote devices, including other cpus. the sci transmitter and receiver operate independently, although they use the same baud rate generator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 15-14. detailed sci block diagram sci data receive shift register sci data register transmit shift register register baud rate generator sbr12:sbr0 bus transmit control 16 receive and wakeup data format control control t8 pf fe nf rdrf idle tie or tcie tdre tc r8 raf loops rwu re pe ilt pt wake m clock ilie rie rxd rsrc sbk loops te rsrc iren r16xclk ir_rxd txd ir_txd r16xclk r32xclk tnp[1:0] iren transmit encoder receive decoder scrxd sctxd infrared infrared tc tdre rdrf/or idle active edge detect break detect rxd bkdfe berrm[1:0] bkdie bkdif rxedgie rxedgif berrie berrif sci interrupt request lin transmit collision detect 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 594 freescale semiconductor 15.4.1 infrared interface submodule this module provides the capability of transmitting narrow pulses to an ir led and receiving narrow pulses and transforming them to serial bits, which are sent to the sci. the irda physical layer speci?ation de?es a half-duplex infrared communication link for exchange data. the full standard includes data rates up to 16 mbits/s. this design covers only data rates between 2.4 kbits/s and 115.2 kbits/s. the infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. the sci transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. no pulse is transmitted for every one bit. when receiving data, the ir pulses should be detected using an ir photo diode and transformed to cmos levels by the ir receive decoder (external from the mcu). the narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the sci.the polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external irda transceiver modules that uses active low pulses. the infrared submodule receives its clock sources from the sci. one of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. the infrared block receives two clock sources from the sci, r16xclk and r32xclk, which are con?ured to generate the narrow pulse width during transmission. the r16xclk and r32xclk are internal clocks with frequencies 16 and 32 times the baud rate respectively. both r16xclk and r32xclk clocks are used for transmitting data. the receive decoder uses only the r16xclk clock. 15.4.1.1 infrared transmit encoder the infrared transmit encoder converts serial bits of data from transmit shift register to the txd pin. a narrow pulse is transmitted for a zero bit and no pulse for a one bit. the narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. a narrow high pulse is transmitted for a zero bit when txpol is cleared, while a narrow low pulse is transmitted for a zero bit when txpol is set. 15.4.1.2 infrared receive decoder the infrared receive block converts data from the rxd pin to the receive shift register. a narrow pulse is expected for each zero received and no pulse is expected for each one received. a narrow high pulse is expected for a zero bit when rxpol is cleared, while a narrow low pulse is expected for a zero bit when rxpol is set. this receive decoder meets the edge jitter requirement as de?ed by the irda serial infrared physical layer speci?ation. 15.4.2 lin support this module provides some basic support for the lin protocol. at ?st this is a break detect circuitry making it easier for the lin software to distinguish a break character from an incoming data stream. as a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 595 15.4.3 data format the sci uses the standard nrz mark/space data format. when infrared is enabled, the sci uses rzi data format where zeroes are represented by light pulses and ones remain low. see figure 15-15 below. figure 15-15. sci data formats each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. clearing the m bit in sci control register 1 con?ures the sci for 8-bit data characters. a frame with eight data bits has a total of 10 bits. setting the m bit con?ures the sci for nine-bit data characters. a frame with nine data bits has a total of 11 bits. when the sci is con?ured for 9-bit data characters, the ninth data bit is the t8 bit in sci data register high (scidrh). it remains unchanged after transmission and can be used repeatedly without rewriting it. a frame with nine data bits has a total of 11 bits. table 15-13. example of 8-bit data formats start bit data bits address bits parity bits stop bit 18001 17011 17 1 1 1 the address bit identi?s the frame as an address character. see section 15.4.6.6, ?eceiver wakeup . 01 table 15-14. example of 9-bit data formats start bit data bits address bits parity bits stop bit 19001 18011 18 1 1 01 bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scicr1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scicr1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit standard sci data infrared sci data standard sci data infrared sci data 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 596 freescale semiconductor 15.4.4 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value from 0 to 8191 written to the sbr12:sbr0 bits determines the bus clock divisor. the sbr bits are in the sci baud rate registers (scibdh and scibdl). the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisition rate of 16 samples per bit time. baud rate generation is subject to one source of error: integer division of the bus clock may not give the exact target frequency. table 15-15 lists some examples of achieving target baud rates with a bus clock frequency of 25 mhz. when iren = 0 then, sci baud rate = sci bus clock / (16 * scibr[12:0]) 1 the address bit identi?s the frame as an address character. see section 15.4.6.6, ?eceiver wakeup . table 15-15. baud rates (example: bus clock = 25 mhz) bits sbr[12:0] receiver clock (hz) transmitter clock (hz) target baud rate error (%) 41 609,756.1 38,109.8 38,400 .76 81 308,642.0 19,290.1 19,200 .47 163 153,374.2 9585.9 9,600 .16 326 76,687.1 4792.9 4,800 .15 651 38,402.5 2400.2 2,400 .01 1302 19,201.2 1200.1 1,200 .01 2604 9600.6 600.0 600 .00 5208 4800.0 300.0 300 .00 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 597 15.4.5 transmitter figure 15-16. transmitter block diagram 15.4.5.1 transmitter character length the sci transmitter can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when transmitting 9-bit data, bit t8 in sci data register high (scidrh) is the ninth bit (bit 8). 15.4.5.2 character transmission to transmit data, the mcu writes the data bits to the sci data registers (scidrh/scidrl), which in turn are transferred to the transmitter shift register. the transmit shift register then shifts a frame out through the txd pin, after it has prefaced them with a start bit and appended them with a stop bit. the sci data registers (scidrh and scidrl) are the write-only buffers between the internal data bus and the transmit shift register. pe pt h876543210l 11-bit transmit register stop start t8 tie tdre tcie sbk tc parity generation msb sci data registers load from scidr shift enable preamble (all 1s) break (all 0s) transmitter control m internal bus sbr12:sbr0 baud divider 16 bus clock te sctxd txpol loops loop rsrc control to receiver transmit collision detect tdre irq tc irq sctxd scrxd (from receiver) tcie berrif ber irq berrm[1:0] 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 598 freescale semiconductor the sci also sets a ?g, the transmit data register empty ?g (tdre), every time it transfers data from the buffer (scidrh/l) to the transmitter shift register.the transmit driver routine may respond to this ?g by writing another byte to the transmitter buffer (scidrh/scidrl), while the shift register is still shifting out the ?st byte. to initiate an sci transmission: 1. con?ure the sci: a) select a baud rate. write this value to the sci baud registers (scibdh/l) to begin the baud rate generator. remember that the baud rate generator is disabled when the baud rate is zero. writing to the scibdh has no effect without also writing to scibdl. b) write to scicr1 to con?ure word length, parity, and other con?uration bits (loops,rsrc,m,wake,ilt,pe,pt). c) enable the transmitter, interrupts, receive, and wake up as required, by writing to the scicr2 register bits (tie,tcie,rie,ilie,te,re,rwu,sbk). a preamble or idle character will now be shifted out of the transmitter shift register. 2. transmit procedure for each byte: a) poll the tdre ?g by reading the scisr1 or responding to the tdre interrupt. keep in mind that the tdre bit resets to one. b) if the tdre ?g is set, write the data to be transmitted to scidrh/l, where the ninth bit is written to the t8 bit in scidrh if the sci is in 9-bit data format. a new transmission will not result until the tdre ?g has been cleared. 3. repeat step 2 for each subsequent transmission. note the tdre ?g is set when the shift register is loaded with the next data to be transmitted from scidrh/l, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. speci?ally, this transfer occurs 9/16ths of a bit time after the start of the stop bit of the previous frame. writing the te bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if m = 0) or 11 logic 1s (if m = 1). after the preamble shifts out, control logic transfers the data from the sci data register into the transmit shift register. a logic 0 start bit automatically goes into the least signi?ant bit position of the transmit shift register. a logic 1 stop bit goes into the most signi?ant bit position. hardware supports odd or even parity. when parity is enabled, the most signi?ant bit (msb) of the data character is the parity bit. the transmit data register empty ?g, tdre, in sci status register 1 (scisr1) becomes set when the sci data register transfers a byte to the transmit shift register. the tdre ?g indicates that the sci data register can accept new data from the internal data bus. if the transmit interrupt enable bit, tie, in sci control register 2 (scicr2) is also set, the tdre ?g generates a transmitter interrupt request. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 599 when the transmit shift register is not transmitting a frame, the txd pin goes to the idle condition, logic 1. if at any time software clears the te bit in sci control register 2 (scicr2), the transmitter enable signal goes low and the transmit signal goes idle. if software clears te while a transmission is in progress (tc = 0), the frame in the transmit shift register continues to shift out. to avoid accidentally cutting off the last frame in a message, always wait for tdre to go high after the last frame before clearing te. to separate messages with preambles with minimum idle line time, use this sequence between messages: 1. write the last byte of the ?st message to scidrh/l. 2. wait for the tdre ?g to go high, indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the ?st byte of the second message to scidrh/l. 15.4.5.3 break characters writing a logic 1 to the send break bit, sbk, in sci control register 2 (scicr2) loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in sci control register 1 (scicr1). as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register ?ishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. the sci recognizes a break character when there are 10 or 11(m = 0 or m = 1) consecutive zero received. depending if the break detect feature is enabled or not receiving a break character has these effects on sci registers. if the break detect feature is disabled (bkdfe = 0): sets the framing error flag, fe sets the receive data register full flag, rdrf clears the sci data registers (scidrh/l) may set the overrun flag, or, noise flag, nf, parity error flag, pe, or the receiver active flag, raf (see 3.4.4 and 3.4.5 sci status register 1 and 2) if the break detect feature is enabled (bkdfe = 1) there are two scenarios 1 the break is detected right from a start bit or is detected during a byte reception. sets the break detect interrupt flag, bldif does not change the data register full flag, rdrf or overrun flag or does not change the framing error flag fe, parity error flag pe. does not clear the sci data registers (scidrh/l) may set noise flag nf, or receiver active flag raf. 1. a break character in this context are either 10 or 11 consecutive zero received bits 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 600 freescale semiconductor figure 15-17 shows two cases of break detect. in trace rxd_1 the break symbol starts with the start bit, while in rxd_2 the break starts in the middle of a transmission. if brkdfe = 1, in rxd_1 case there will be no byte transferred to the receive buffer and the rdrf ?g will not be modi?d. also no framing error or parity error will be ?gged from this transfer. in rxd_2 case, however the break signal starts later during the transmission. at the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full ?g will be set, a framing error and if enabled and appropriate a parity error will be set. once the break is detected the brkdif ?g will be set. figure 15-17. break detection if brkdfe = 1 (m = 0) 15.4.5.4 idle characters an idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in sci control register 1 (scicr1). the preamble is a synchronizing idle character that begins the ?st transmission initiated after writing the te bit from 0 to 1. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the frame currently being transmitted. note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current frame shifts out through the txd pin. setting te after the stop bit appears on txd causes data previously written to the sci data register to be lost. toggle the te bit for a queued idle character while the tdre ?g is set and immediately before writing the next byte to the sci data register. if the te bit is clear and the transmission is complete, the sci is not the master of the txd pin start bit position stop bit position brkdif = 1 fe = 1 brkdif = 1 rxd_1 rxd_2 1 23 4567 8 910 1 23 4567 8 910 zero bit counter zero bit counter . . . . . . 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 601 15.4.5.5 lin transmit collision detection this module allows to check for collisions on the lin bus. figure 15-18. collision detect principle if the bit error circuit is enabled (berrm[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and ?g any mismatch. the timing checks run when transmitter is active (not idle). as soon as a mismatch between the transmitted data and the received data is detected the following happens: the next bit transmitted will have a high level (txpol = 0) or low level (txpol = 1) the transmission is aborted and the byte in transmit buffer is discarded. the transmit data register empty and the transmission complete flag will be set the bit error interrupt flag, berrif, will be set. no further transmissions will take place until the berrif is cleared. figure 15-19. timing diagram bit error detection if the bit error detect feature is disabled, the bit error interrupt ?g is cleared. note the rxpol and txpol bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ?g may be set incorrectly. txd pin rxd pin lin physical interface synchronizer stage bus clock receive shift register transmit shift register lin bus compare sample bit error point output transmit shift register 01234567891011121314150 input receive shift register berrm[1:0] = 0:1 berrm[1:0] = 1:1 compare sample points sampling begin sampling begin sampling end sampling end 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 602 freescale semiconductor 15.4.6 receiver figure 15-20. sci receiver block diagram 15.4.6.1 receiver character length the sci receiver can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when receiving 9-bit data, bit r8 in sci data register high (scidrh) is the ninth bit (bit 8). 15.4.6.2 character reception during an sci reception, the receive shift register shifts a frame in from the rxd pin. the sci data register is the read-only buffer between the internal data bus and the receive shift register. after a complete frame shifts into the receive shift register, the data portion of the frame transfers to the sci data register. the receive data register full ?g, rdrf, in sci status register 1 (scisr1) becomes set, all 1s m wake ilt pe pt re h876543210l 11-bit receive shift register stop start data wakeup parity checking msb sci data register r8 ilie rwu rdrf or nf fe pe internal bus bus sbr12:sbr0 baud divider clock idle raf recovery logic rxpol loops loop rsrc control scrxd from txd pin or transmitter idle irq rdrf/or irq break detect logic active edge detect logic brkdfe brkdie brkdif rxedgie rxedgif break irq rx active edge irq rie 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 603 indicating that the received byte can be read. if the receive interrupt enable bit, rie, in sci control register 2 (scicr2) is also set, the rdrf ?g generates an rdrf interrupt request. 15.4.6.3 data sampling the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock (see figure 15-21 ) is re-synchronized: after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 15-21. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. figure 15-16 summarizes the results of the start bit veri?ation samples. if start bit veri?ation is not successful, the rt clock is reset and a new search for a start bit begins. table 15-16. start bit veri?ation rt3, rt5, and rt7 samples start bit veri?ation noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit quali?ation start bit data sampling 11 1 1 1 1 110000 0 00 lsb veri?ation 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 604 freescale semiconductor to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 15-17 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit veri?ation. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit veri?ation, the noise ?g (nf) is set and the receiver assumes that the bit is a start bit (logic 0). to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 15-18 summarizes the results of the stop bit samples. table 15-17. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 15-18. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 605 in figure 15-22 the veri?ation samples rt3 and rt5 determine that the ?st low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the noise ?g is not set because the noise occurred before the start bit was found. figure 15-22. start bit search example 1 in figure 15-23 , veri?ation sample at rt3 is high. the rt3 sample sets the noise ?g. although the perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 15-23. start bit search example 2 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 606 freescale semiconductor in figure 15-24 , a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 is high. the rt5 sample sets the noise ?g. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 15-24. start bit search example 3 figure 15-25 shows the effect of noise early in the start bit time. although this noise does not affect proper synchronization with the start bit time, it does set the noise ?g. figure 15-25. start bit search example 4 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 607 figure 15-26 shows a burst of noise near the beginning of the start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error ?g. figure 15-26. start bit search example 5 in figure 15-27 , a noise burst makes the majority of data samples rt8, rt9, and rt10 high. this sets the noise ?g but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. figure 15-27. start bit search example 6 15.4.6.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error ?g, fe, in sci status register 1 (scisr1). a break character also sets the fe ?g because a break character has no stop bit. the fe ?g is set at the same time that the rdrf ?g is set. reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 608 freescale semiconductor 15.4.6.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples (rt8, rt9, and rt10) to fall outside the actual stop bit. a noise error will occur if the rt8, rt9, and rt10 samples are not all the same logical values. a framing error will occur if the receiver clock is misaligned in such a way that the majority of the rt8, rt9, and rt10 stop bit samples are a logic zero. as the receiver samples an incoming frame, it re-synchronizes the rt clock on any valid falling edge within the frame. re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 15.4.6.5.1 slow data tolerance figure 15-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 15-28. slow data lets take rtr as receiver rt clock and rtt as transmitter rt clock. for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles +7 rtr cycles = 151 rtr cycles to start data sampling of the stop bit. with the misaligned character shown in figure 15-28 , the receiver counts 151 rtr cycles at the point when the count of the transmitting device is 9 bit times x 16 rtt cycles = 144 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 ?144) / 151) x 100 = 4.63% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 7 rtr cycles = 167 rtr cycles to start data sampling of the stop bit. with the misaligned character shown in figure 15-28 , the receiver counts 167 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 ?160) / 167) x 100 = 4.19% msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 609 15.4.6.5.2 fast data tolerance figure 15-29 shows how much a fast received frame can be misaligned. the fast stop bit ends at rt10 instead of rt16 but is still sampled at rt8, rt9, and rt10. figure 15-29. fast data for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles + 10 rtr cycles = 154 rtr cycles to ?ish data sampling of the stop bit. with the misaligned character shown in figure 15-29 , the receiver counts 154 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 ?154) / 160) x 100 = 3.75% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 10 rtr cycles = 170 rtr cycles to ?ish data sampling of the stop bit. with the misaligned character shown in figure 15-29 , the receiver counts 170 rtr cycles at the point when the count of the transmitting device is 11 bit times x 16 rtt cycles = 176 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 ?170) /176) x 100 = 3.40% 15.4.6.6 receiver wakeup to enable the sci to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in sci control register 2 (scicr2) puts the receiver into standby state during which receiver interrupts are disabled.the sci will still load the receive data into the scidrh/l registers, but it will not set the rdrf ?g. the transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. the wake bit in sci control register 1 (scicr1) determines how the sci is brought out of the standby state to process an incoming message. the wake bit enables either idle line wakeup or address mark wakeup. idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 610 freescale semiconductor 15.4.6.6.1 idle input line wakeup (wake = 0) in this wakeup method, an idle condition on the rxd pin clears the rwu bit and wakes up the sci. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another idle character appears on the rxd pin. idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. the idle character that wakes a receiver does not set the receiver idle bit, idle, or the receive data register full ?g, rdrf. the idle line type bit, ilt, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ilt is in sci control register 1 (scicr1). 15.4.6.6.2 address mark wakeup (wake = 1) in this wakeup method, a logic 1 in the most signi?ant bit (msb) position of a frame clears the rwu bit and wakes up the sci. the logic 1 in the msb position marks a frame as an address frame that contains addressing information. all receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another address frame appears on the rxd pin. the logic 1 msb of an address frame clears the receivers rwu bit before the stop bit is received and sets the rdrf ?g. address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. 15.4.7 single-wire operation normally, the sci uses two pins for transmitting and receiving. in single-wire operation, the rxd pin is disconnected from the sci. the sci uses the txd pin for both receiving and transmitting. figure 15-30. single-wire operation (loops = 1, rsrc = 1) rxd transmitter receiver txd 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 611 enable single-wire operation by setting the loops bit and the receiver source bit, rsrc, in sci control register 1 (scicr1). setting the loops bit disables the path from the rxd pin to the receiver. setting the rsrc bit connects the txd pin to the receiver. both the transmitter and receiver must be enabled (te = 1 and re = 1).the txdir bit (scisr2[1]) determines whether the txd pin is going to be used as an input (txdir = 0) or an output (txdir = 1) in this mode of operation. note in single-wire operation data from the txd pin is inverted if rxpol is set. 15.4.8 loop operation in loop operation the transmitter output goes to the receiver input. the rxd pin is disconnected from the sci. figure 15-31. loop operation (loops = 1, rsrc = 0) enable loop operation by setting the loops bit and clearing the rsrc bit in sci control register 1 (scicr1). setting the loops bit disables the path from the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (te = 1 and re = 1). note in loop operation data from the transmitter is not recognized by the receiver if rxpol and txpol are not the same. 15.5 initialization/application information 15.5.1 reset initialization see section 15.3.2, ?egister descriptions . 15.5.2 modes of operation 15.5.2.1 run mode normal mode of operation. to initialize a sci transmission, see section 15.4.5.2, ?haracter transmission . rxd transmitter receiver txd 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 612 freescale semiconductor 15.5.2.2 wait mode sci operation in wait mode depends on the state of the sciswai bit in the sci control register 1 (scicr1). if sciswai is clear, the sci operates normally when the cpu is in wait mode. if sciswai is set, sci clock generation ceases and the sci module enters a power-conservation state when the cpu is in wait mode. setting sciswai does not affect the state of the receiver enable bit, re, or the transmitter enable bit, te. if sciswai is set, any transmission or reception in progress stops at wait mode entry. the transmission or reception resumes when either an internal or external interrupt brings the cpu out of wait mode. exiting wait mode by reset aborts any transmission or reception in progress and resets the sci. 15.5.2.3 stop mode the sci is inactive during stop mode for reduced power consumption. the stop instruction does not affect the sci register states, but the sci bus clock will be disabled. the sci operation resumes from where it left off after an external interrupt brings the cpu out of stop mode. exiting stop mode by reset aborts any transmission or reception in progress and resets the sci. the receive input active edge detect circuit is still active in stop mode. an active edge on the receive input can be used to bring the cpu out of stop mode. 15.5.3 interrupt operation this section describes the interrupt originated by the sci block.the mcu must service the interrupt requests. table 15-19 lists the eight interrupt sources of the sci. table 15-19. sci interrupt sources interrupt source local enable description tdre scisr1[7] tie active high level. indicates that a byte was transferred from scidrh/l to the transmit shift register. tc scisr1[6] tcie active high level. indicates that a transmit is complete. rdrf scisr1[5] rie active high level. the rdrf interrupt indicates that received data is available in the sci data register. or scisr1[3] active high level. this interrupt indicates that an overrun condition has occurred. idle scisr1[4] ilie active high level. indicates that receiver input has become idle. rxedgif sciasr1[7] rxedgie active high level. indicates that an active edge (falling for rxpol = 0, rising for rxpol = 1) was detected. berrif sciasr1[1] berrie active high level. indicates that a mismatch between transmitted and received data in a single wire application has happened. bkdif sciasr1[0] brkdie active high level. indicates that a break character has been received. 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 613 15.5.3.1 description of interrupt operation the sci only originates interrupt requests. the following is a description of how the sci makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt number are chip dependent. the sci only has a single interrupt line (sci interrupt signal, active high operation) and all the following interrupts, when generated, are ored together and issued through that port. 15.5.3.1.1 tdre description the tdre interrupt is set high by the sci when the transmit shift register receives a byte from the sci data register. a tdre interrupt indicates that the transmit data register (scidrh/l) is empty and that a new byte can be written to the scidrh/l for transmission.clear tdre by reading sci status register 1 with tdre set and then writing to sci data register low (scidrl). 15.5.3.1.2 tc description the tc interrupt is set by the sci when a transmission has been completed. transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. no stop bit is transmitted when sending a break character and the tc ?g is set (providing there is no more data queued for transmission) when the break character has been shifted out. a tc interrupt indicates that there is no transmission in progress. tc is set high when the tdre ?g is set and no data, preamble, or break character is being transmitted. when tc is set, the txd pin becomes idle (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data register low (scidrl).tc is cleared automatically when data, preamble, or break is queued and ready to be sent. 15.5.3.1.3 rdrf description the rdrf interrupt is set when the data in the receive shift register transfers to the sci data register. a rdrf interrupt indicates that the received data has been transferred to the sci data register and that the byte can now be read by the mcu. the rdrf interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 15.5.3.1.4 or description the or interrupt is set when software fails to read the sci data register before the receive shift register receives the next frame. the newly acquired data in the shift register will be lost in this case, but the data already in the sci data registers is not affected. the or interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 15.5.3.1.5 idle description the idle interrupt is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. once the idle is cleared, a valid frame must again set the rdrf ?g before an idle condition can set the idle ?g. clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl). 4 .com u datasheet
chapter 15 serial communication interface (sciv5) MC9S12XHZ512 data sheet, rev. 1.02 614 freescale semiconductor 15.5.3.1.6 rxedgif description the rxedgif interrupt is set when an active edge (falling if rxpol = 0, rising if rxpol = 1) on the rxd pin is detected. clear rxedgif by writing a ??to the sciasr1 sci alternative status register 1. 15.5.3.1.7 berrif description the berrif interrupt is set when a mismatch between the transmitted and the received data in a single wire application like lin was detected. clear berrif by writing a ??to the sciasr1 sci alternative status register 1. this ?g is also cleared if the bit error detect feature is disabled. 15.5.3.1.8 bkdif description the bkdif interrupt is set when a break signal was received. clear bkdif by writing a ??to the sciasr1 sci alternative status register 1. this ?g is also cleared if break detect feature is disabled. 15.5.4 recovery from wait mode the sci interrupt request can be used to bring the cpu out of wait mode. 15.5.5 recovery from stop mode an active edge on the receive input can be used to bring the cpu out of stop mode. 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 615 chapter 16 serial peripheral interface (spiv4) 16.1 introduction the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status ?gs or the spi operation can be interrupt driven. 16.1.1 glossary of terms 16.1.2 features the spi includes these distinctive features: master mode and slave mode bidirectional mode slave select output mode fault error ?g with cpu interrupt capability double-buffered data register serial clock with programmable polarity and phase control of spi operation during wait mode 16.1.3 modes of operation the spi functions in three modes: run, wait, and stop. run mode this is the basic mode of operation. wait mode spi serial peripheral interface ss slave select sck serial clock mosi master output, slave input miso master input, slave output momi master output, master input siso slave input, slave output 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 616 freescale semiconductor spi operation in wait mode is a con?urable low power mode, controlled by the spiswai bit located in the spicr2 register. in wait mode, if the spiswai bit is clear, the spi operates like in run mode. if the spiswai bit is set, the spi goes into a power conservative state, with the spi clock generation turned off. if the spi is con?ured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is con?ured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. stop mode the spi is inactive in stop mode for reduced power consumption. if the spi is con?ured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is con?ured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. this is a high level description only, detailed descriptions of operating modes are contained in section 16.4.7, ?ow power mode options . 16.1.4 block diagram figure 16-1 gives an overview on the spi architecture. the main parts of the spi are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 617 figure 16-1. spi block diagram 16.2 external signal description this section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. the spi module has a total of four external pins. 16.2.1 mosi ?master out/slave in pin this pin is used to transmit data out of the spi module when it is con?ured as a master and receive data when it is con?ured as slave. 16.2.2 miso ?master in/slave out pin this pin is used to transmit data out of the spi module when it is con?ured as a slave and receive data when it is con?ured as master. spi control register 1 spi control register 2 spi baud rate register spi status register spi data register shifter port control logic mosi sck interrupt control spi msb lsb lsbfe=1 lsbfe=0 lsbfe=0 lsbfe=1 data in lsbfe=1 lsbfe=0 data out 8 8 baud rate generator prescaler bus clock counter clock select sppr 3 3 spr baud rate phase + polarity control master slave sck in sck out master baud rate slave baud rate phase + polarity control control control cpol cpha 2 bidiroe spc0 2 shift sample clock clock modf spif sptef spi request interrupt ss 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 618 freescale semiconductor 16.2.3 ss ?slave select pin this pin is used to output the select signal from the spi module to another peripheral with which a data transfer is to take place when it is con?ured as a master and it is used as an input to receive the slave select signal when the spi is con?ured as slave. 16.2.4 sck ?serial clock pin in master mode, this is the synchronous output clock. in slave mode, this is the synchronous input clock. 16.3 memory map and register de?ition this section provides a detailed description of address space and registers used by the spi. 16.3.1 module memory map the memory map for the spi is given in figure 16-2 . the address listed for each register is the sum of a base address and an address offset. the base address is de?ed at the soc level and the address offset is de?ed at the module level. reads from the reserved bits return zeros and writes to the reserved bits have no effect. register name bit 7 6 5 4 3 2 1 bit 0 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w spicr2 r 0 0 0 modfen bidiroe 0 spiswai spc0 w spibr r 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w spisr r spif 0 sptef modf 0 0 0 0 w reserved r w spidr r bit 7 6 5 4 3 2 1 bit 0 w reserved r w reserved r w = unimplemented or reserved figure 16-2. spi register summary 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 619 16.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 620 freescale semiconductor 16.3.2.1 spi control register 1 (spicr1) read: anytime write: anytime 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset 0 0 0 00100 figure 16-3. spi control register 1 (spicr1) table 16-1. spicr1 field descriptions field description 7 spie spi interrupt enable bit ?this bit enables spi interrupt requests, if spif or modf status ?g is set. 0 spi interrupts disabled. 1 spi interrupts enabled. 6 spe spi system enable bit ?this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disabled and forced into idle state, status bits in spisr register are reset. 0 spi disabled (lower power consumption). 1 spi enabled, port pins are dedicated to spi functions. 5 sptie spi transmit interrupt enable ?this bit enables spi interrupt requests, if sptef ?g is set. 0 sptef interrupt disabled. 1 sptef interrupt enabled. 4 mstr spi master/slave mode select bit ?this bit selects whether the spi operates in master or slave mode. switching the spi from master to slave or vice versa forces the spi system into idle state. 0 spi is in slave mode. 1 spi is in master mode. 3 cpol spi clock polarity bit this bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 active-high clocks selected. in idle state sck is low. 1 active-low clocks selected. in idle state sck is high. 2 cpha spi clock phase bit this bit is used to select the spi clock format. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 sampling of data occurs at odd edges (1,3,5,...,15) of the sck clock. 1 sampling of data occurs at even edges (2,4,6,...,16) of the sck clock. 1 ssoe slave select output enable ?the ss output feature is enabled only in master mode, if modfen is set, by asserting the ssoe as shown in table 16-2 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 lsbfe lsb-first enable ?this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in bit 7. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 data is transferred most signi?ant bit ?st. 1 data is transferred least signi?ant bit ?st. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 621 16.3.2.2 spi control register 2 (spicr2) read: anytime write: anytime; writes to the reserved bits have no effect table 16-2. ss input / output selection modfen ssoe master mode slave mode 00 ss not used by spi ss input 01 ss not used by spi ss input 10 ss input with modf feature ss input 11 ss is slave select output ss input 76543210 r000 modfen bidiroe 0 spiswai spc0 w reset 0 0 0 00000 = unimplemented or reserved figure 16-4. spi control register 2 (spicr2) table 16-3. spicr2 field descriptions field description 4 modfen mode fault enable bit ?this bit allows the modf failure to be detected. if the spi is in master mode and modfen is cleared, then the ss port pin is not used by the spi. in slave mode, the ss is available only as an input regardless of the value of modfen. for an overview on the impact of the modfen bit on the ss port pin con?uration, refer to table 16-4 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 ss port pin is not used by the spi. 1 ss port pin with modf feature. 3 bidiroe output enable in the bidirectional mode of operation this bit controls the mosi and miso output buffer of the spi, when in bidirectional mode of operation (spc0 is set). in master mode, this bit controls the output buffer of the mosi port, in slave mode it controls the output buffer of the miso port. in master mode, with spc0 set, a change of this bit will abort a transmission in progress and force the spi into idle state. 0 output buffer disabled. 1 output buffer enabled. 1 spiswai spi stop in wait mode bit ?this bit is used for power conservation while in wait mode. 0 spi clock operates normally in wait mode. 1 stop spi clock generation when in wait mode. 0 spc0 serial pin control bit 0 ?this bit enables bidirectional pin con?urations as shown in table 16-4 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 622 freescale semiconductor 16.3.2.3 spi baud rate register (spibr) read: anytime write: anytime; writes to the reserved bits have no effect the baud rate divisor equation is as follows: baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 16-1 the baud rate can be calculated with the following equation: baud rate = busclock / baudratedivisor eqn. 16-2 note for maximum allowed baud rates, please refer to the spi electrical speci?ation in the electricals chapter of this data sheet. table 16-4. bidirectional pin con?urations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in bidirectional 1 0 slave in mosi not used by spi 1 slave i/o 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset 0 0 0 00000 = unimplemented or reserved figure 16-5. spi baud rate register (spibr) table 16-5. spibr field descriptions field description 6? sppr[2:0] spi baud rate preselection bits these bits specify the spi baud rates as shown in table 16-6 . in master mode, a change of these bits will abort a transmission in progress and force the spi system into idle state. 2? spr[2:0] spi baud rate selection bits these bits specify the spi baud rates as shown in table 16-6 . in master mode, a change of these bits will abort a transmission in progress and force the spi system into idle state. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 623 table 16-6. example spi baud rate selection (25 mhz bus clock) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 0 0 0 0 0 0 2 12.5 mhz 0 0 0 0 0 1 4 6.25 mhz 0 0 0 0 1 0 8 3.125 mhz 0 0 0 0 1 1 16 1.5625 mhz 0 0 0 1 0 0 32 781.25 khz 0 0 0 1 0 1 64 390.63 khz 0 0 0 1 1 0 128 195.31 khz 0 0 0 1 1 1 256 97.66 khz 0 0 1 0 0 0 4 6.25 mhz 0 0 1 0 0 1 8 3.125 mhz 0 0 1 0 1 0 16 1.5625 mhz 0 0 1 0 1 1 32 781.25 khz 0 0 1 1 0 0 64 390.63 khz 0 0 1 1 0 1 128 195.31 khz 0 0 1 1 1 0 256 97.66 khz 0 0 1 1 1 1 512 48.83 khz 0 1 0 0 0 0 6 4.16667 mhz 0 1 0 0 0 1 12 2.08333 mhz 0 1 0 0 1 0 24 1.04167 mhz 0 1 0 0 1 1 48 520.83 khz 0 1 0 1 0 0 96 260.42 khz 0 1 0 1 0 1 192 130.21 khz 0 1 0 1 1 0 384 65.10 khz 0 1 0 1 1 1 768 32.55 khz 0 1 1 0 0 0 8 3.125 mhz 0 1 1 0 0 1 16 1.5625 mhz 0 1 1 0 1 0 32 781.25 khz 0 1 1 0 1 1 64 390.63 khz 0 1 1 1 0 0 128 195.31 khz 0 1 1 1 0 1 256 97.66 khz 0 1 1 1 1 0 512 48.83 khz 0 1 1 1 1 1 1024 24.41 khz 1 0 0 0 0 0 10 2.5 mhz 1 0 0 0 0 1 20 1.25 mhz 1 0 0 0 1 0 40 625 khz 1 0 0 0 1 1 80 312.5 khz 1 0 0 1 0 0 160 156.25 khz 1 0 0 1 0 1 320 78.13 khz 1 0 0 1 1 0 640 39.06 khz 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 624 freescale semiconductor 1 0 0 1 1 1 1280 19.53 khz 1 0 1 0 0 0 12 2.08333 mhz 1 0 1 0 0 1 24 1.04167 mhz 1 0 1 0 1 0 48 520.83 khz 1 0 1 0 1 1 96 260.42 khz 1 0 1 1 0 0 192 130.21 khz 1 0 1 1 0 1 384 65.10 khz 1 0 1 1 1 0 768 32.55 khz 1 0 1 1 1 1 1536 16.28 khz 1 1 0 0 0 0 14 1.78571 mhz 1 1 0 0 0 1 28 892.86 khz 1 1 0 0 1 0 56 446.43 khz 1 1 0 0 1 1 112 223.21 khz 1 1 0 1 0 0 224 111.61 khz 1 1 0 1 0 1 448 55.80 khz 1 1 0 1 1 0 896 27.90 khz 1 1 0 1 1 1 1792 13.95 khz 1 1 1 0 0 0 16 1.5625 mhz 1 1 1 0 0 1 32 781.25 khz 1 1 1 0 1 0 64 390.63 khz 1 1 1 0 1 1 128 195.31 khz 1 1 1 1 0 0 256 97.66 khz 1 1 1 1 0 1 512 48.83 khz 1 1 1 1 1 0 1024 24.41 khz 1 1 1 1 1 1 2048 12.21 khz table 16-6. example spi baud rate selection (25 mhz bus clock) (continued) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 625 16.3.2.4 spi status register (spisr) read: anytime write: has no effect 76543210 r spif 0 sptef modf 0000 w reset 0 0 1 00000 = unimplemented or reserved figure 16-6. spi status register (spisr) table 16-7. spisr field descriptions field description 7 spif spif interrupt flag this bit is set after a received data byte has been transferred into the spi data register. this bit is cleared by reading the spisr register (with spif set) followed by a read access to the spi data register. 0 transfer not yet complete. 1 new data copied to spidr. 5 sptef spi transmit empty interrupt flag if set, this bit indicates that the transmit data register is empty. to clear this bit and place data into the transmit data register, spisr must be read with sptef = 1, followed by a write to spidr. any write to the spi data register without reading sptef = 1, is effectively ignored. 0 spi data register not empty. 1 spi data register empty. 4 modf mode fault flag this bit is set if the ss input becomes low while the spi is con?ured as a master and mode fault detection is enabled, modfen bit of spicr2 register is set. refer to modfen bit description in section 16.3.2.2, ?pi control register 2 (spicr2) . the ?g is cleared automatically by a read of the spi status register (with modf set) followed by a write to the spi control register 1. 0 mode fault has not occurred. 1 mode fault has occurred. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 626 freescale semiconductor 16.3.2.5 spi data register (spidr) read: anytime; normally read only when spif is set write: anytime the spi data register is both the input and output register for spi data. a write to this register allows a data byte to be queued and transmitted. for an spi con?ured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty ?g sptef in the spisr register indicates when the spi data register is ready to accept new data. received data in the spidr is valid when spif is set. if spif is cleared and a byte has been received, the received byte is transferred from the receive shift register to the spidr and spif is set. if spif is set and not serviced, and a second byte has been received, the second received byte is kept as valid byte in the receive shift register until the start of another transmission. the byte in the spidr does not change. if spif is set and a valid byte is in the receive shift register, and spif is serviced before the start of a third transmission, the byte in the receive shift register is transferred into the spidr and spif remains set (see figure 16-8 ). if spif is set and a valid byte is in the receive shift register, and spif is serviced after the start of a third transmission, the byte in the receive shift register has become invalid and is not transferred into the spidr (see figure 16-9 ). 76543210 r bit 7 6 5 4322 bit 0 w reset 0 0 0 00000 figure 16-7. spi data register (spidr) 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 627 figure 16-8. reception with spif serviced in time figure 16-9. reception with spif serviced too late receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b = unspeci?d = reception in progress receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b lost = unspeci?d = reception in progress 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 628 freescale semiconductor 16.4 functional description the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status ?gs or spi operation can be interrupt driven. the spi system is enabled by setting the spi enable (spe) bit in spi control register 1. while spe is set, the four associated spi port pins are dedicated to the spi function as: slave select ( ss) serial clock (sck) master out/slave in (mosi) master in/slave out (miso) the main element of the spi system is the spi data register. the 8-bit data register in the master and the 8-bit data register in the slave are linked by the mosi and miso pins to form a distributed 16-bit register. when a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the s-clock from the master, so data is exchanged between the master and the slave. data written to the master spi data register becomes the output data for the slave, and data read from the master spi data register after a transfer operation is the input data from the slave. a read of spisr with sptef = 1 followed by a write to spidr puts data into the transmit data register. when a transfer is complete and spif is cleared, received data is moved into the receive data register. this 8-bit data register acts as the spi receive data register for reads and as the spi transmit data register for writes. a single spi register address is used for reading data from the read data buffer and for writing data to the transmit data register. the clock phase control bit (cpha) and a clock polarity control bit (cpol) in the spi control register 1 (spicr1) select one of four possible clock formats to be used by the spi system. the cpol bit simply selects a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered sck edges or on even numbered sck edges (see section 16.4.3, ?ransmission formats ). the spi can be con?ured to operate as a master or as a slave. when the mstr bit in spi control register1 is set, master mode is selected, when the mstr bit is clear, slave mode is selected. note a change of cpol or mstr bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 629 16.4.1 master mode the spi operates in master mode when the mstr bit is set. only a master spi module can initiate transmissions. a transmission begins by writing to the master spi data register. if the shift register is empty, the byte immediately transfers to the shift register. the byte begins shifting out on the mosi pin under the control of the serial clock. serial clock the spr2, spr1, and spr0 baud rate selection bits, in conjunction with the sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate register, control the baud rate generator and determine the speed of the transmission. the sck pin is the spi clock output. through the sck pin, the baud rate generator of the master controls the shift register of the slave peripheral. mosi, miso pin in master mode, the function of the serial data output pin (mosi) and the serial data input pin (miso) is determined by the spc0 and bidiroe control bits. ss pin if modfen and ssoe are set, the ss pin is con?ured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. if modfen is set and ssoe is cleared, the ss pin is con?ured as input for detecting mode fault error. if the ss input becomes low this indicates a mode fault error where another master tries to drive the mosi and sck lines. in this case, the spi immediately switches to slave mode, by clearing the mstr bit and also disables the slave output buffer miso (or siso in bidirectional mode). so the result is that all outputs are disabled and sck, mosi, and miso are inputs. if a transmission is in progress when the mode fault occurs, the transmission is aborted and the spi is forced into idle state. this mode fault error also sets the mode fault (modf) ?g in the spi status register (spisr). if the spi interrupt enable bit (spie) is set when the modf ?g becomes set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master occurs, there is a half sck-cycle delay. after the delay, sck is started within the master. the rest of the transfer operation differs slightly, depending on the clock format speci?d by the spi clock phase bit, cpha, in spi control register 1 (see section 16.4.3, ?ransmission formats? . note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, or bidiroe with spc0 set, sppr2-sppr0 and spr2-spr0 in master mode will abort a transmission in progress and force the spi into idle state. the remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 630 freescale semiconductor 16.4.2 slave mode the spi operates in slave mode when the mstr bit in spi control register 1 is clear. serial clock in slave mode, sck is the spi clock input from the master. miso, mosi pin in slave mode, the function of the serial data output pin (miso) and serial data input pin (mosi) is determined by the spc0 bit and bidiroe bit in spi control register 2. ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the serial data output pin, if ss is high (not selected), the serial data output pin is high impedance, and, if ss is low, the ?st bit in the spi data register is driven out of the serial data output pin. also, if the slave is not selected ( ss is high), then the sck input is ignored and no internal shifting of the spi shift register occurs. although the spi is capable of duplex operation, some spi peripherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin. note when peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slaves serial data output line. as long as no more than one slave device drives the system slaves serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. if the cpha bit in spi control register 1 is clear, odd numbered edges on the sck input cause the data at the serial data input pin to be latched. even numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. if the cpha bit is set, even numbered edges on the sck input cause the data at the serial data input pin to be latched. odd numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the ?st edge is used to get the ?st data bit onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the ?st bit of the spi data is driven out of the serial data output pin. after the eighth shift, the transfer is considered complete and the received data is transferred into the spi data register. to indicate transfer is complete, the spif ?g in the spi status register is set. note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, or bidiroe with spc0 set in slave mode will corrupt a transmission in progress and must be avoided. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 631 16.4.3 transmission formats during an spi transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. the serial clock (sck) synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. optionally, on a master spi device, the slave select line can be used to indicate multiple-master bus contention. figure 16-10. master/slave transfer block diagram 16.4.3.1 clock phase and polarity controls using two bits in the spi control register 1, software selects one of four combinations of serial clock phase and polarity. the cpol clock polarity control bit speci?s an active high or low clock and has no signi?ant effect on the transmission format. the cpha clock phase control bit selects one of two fundamentally different transmission formats. clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 16.4.3.2 cpha = 0 transfer format the ?st edge on the sck line is used to clock the ?st data bit of the slave into the master and the ?st data bit of the master into the slave. in some peripherals, the ?st bit of the slaves data is available at the slaves data out pin as soon as the slave is selected. in this format, the ?st sck edge is issued a half cycle after ss has become low. a half sck cycle later, the second edge appears on the sck line. when this second edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the shift register, depending on lsbfe bit. after this second edge, the next bit of the spi master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of 16 edges on the sck line, with data being latched on odd numbered edges and shifted on even numbered edges. shift register shift register baud rate generator master spi slave spi mosi mosi miso miso sck sck ss ss v dd 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 632 freescale semiconductor data reception is double buffered. data is shifted serially into the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after the 16th (last) sck edge: data that was previously in the master spi data register should now be in the slave data register and the data that was in the slave data register should be in the master. the spif ?g in the spi status register is set, indicating that the transfer is complete. figure 16-11 is a timing diagram of an spi transfer where cpha = 0. sck waveforms are shown for cpol = 0 and cpol = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave and the mosi signal is the output from the master. the ss pin of the master must be either high or recon?ured as a general-purpose output not affecting the spi. figure 16-11. spi clock format 0 (cpha = 0) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0): lsb ?st (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 633 in slave mode, if the ss line is not deasserted between the successive transmissions then the content of the spi data register is not transmitted; instead the last received byte is transmitted. if the ss line is deasserted for at least minimum idle time (half sck cycle) between successive transmissions, then the content of the spi data register is transmitted. in master mode, with slave select output enabled the ss line is always deasserted and reasserted between successive transfers for at least minimum idle time. 16.4.3.3 cpha = 1 transfer format some peripherals require the ?st sck edge before the ?st data bit becomes available at the data out pin, the second edge clocks data into the system. in this format, the ?st sck edge is issued by setting the cpha bit at the beginning of the 8-cycle transfer operation. the ?st edge of sck occurs immediately after the half sck clock cycle synchronization delay. this ?st edge commands the slave to transfer its ?st data bit to the serial data input pin of the master. a half sck cycle later, the second edge appears on the sck pin. this is the latching edge for both the master and slave. when the third edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the spi shift register, depending on lsbfe bit. after this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of 16 edges on the sck line with data being latched on even numbered edges and shifting taking place on odd numbered edges. data reception is double buffered, data is serially shifted into the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after the 16th sck edge: data that was previously in the spi data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. the spif ?g bit in spisr is set indicating that the transfer is complete. figure 16-12 shows two clocking variations for cpha = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the ss pin of the master must be either high or recon?ured as a general-purpose output not affecting the spi. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 634 freescale semiconductor figure 16-12. spi clock format 1 (cpha = 1) the ss line can remain active low between successive transfers (can be tied low at all times). this format is sometimes preferred in systems having a single ?ed master and a single slave that drive the miso data line. back-to-back transfers in master mode in master mode, if a transmission has completed and a new data byte is available in the spi data register, this byte is sent out immediately without a trailing and minimum idle time. the spi interrupt request ?g (spif) is common to both the master and slave modes. spif gets set one half sck cycle after the last sck edge. t l t t for t t , t l , t l minimum 1/2 sck t i t l if next transfer begins here begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0): lsb ?st (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t l = minimum leading time before the ?st sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 635 16.4.4 spi baud rate generation baud rate generation consists of a series of divider stages. six bits in the spi baud rate register (sppr2, sppr1, sppr0, spr2, spr1, and spr0) determine the divisor to the spi module clock which results in the spi baud rate. the spi clock rate is determined by the product of the value in the baud rate preselection bits (sppr2?ppr0) and the value in the baud rate selection bits (spr2?pr0). the module clock divisor equation is shown in equation 16-3 . baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 16-3 when all bits are clear (the default condition), the spi module clock is divided by 2. when the selection bits (spr2?pr0) are 001 and the preselection bits (sppr2?ppr0) are 000, the module clock divisor becomes 4. when the selection bits are 010, the module clock divisor becomes 8, etc. when the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. when the preselection bits are 010, the divisor is multiplied by 3, etc. see table 16-6 for baud rate calculations for all bit conditions, based on a 25 mhz bus clock. the two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. the baud rate generator is activated only when the spi is in master mode and a serial transfer is taking place. in the other cases, the divider is disabled to decrease i dd current. note for maximum allowed baud rates, please refer to the spi electrical speci?ation in the electricals chapter of this data sheet. 16.4.5 special features 16.4.5.1 ss output the ss output feature automatically drives the ss pin low during transmission to select external devices and drives it high during idle to deselect external devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in master mode during normal spi operation by asserting ssoe and modfen bit as shown in table 16-2 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 636 freescale semiconductor 16.4.5.2 bidirectional mode (momi or siso) the bidirectional mode is selected when the spc0 bit is set in spi control register 2 (see table 16-8 ). in this mode, the spi uses only one serial data pin for the interface with external device(s). the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (momi) pin for the master mode, and the miso pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pin in slave mode are not used by the spi. the direction of each serial i/o pin depends on the bidiroe bit. if the pin is con?ured as an output, serial data from the shift register is driven out on the pin. the same pin is also the serial input to the shift register. the sck is output for the master mode and input for the slave mode. the ss is the input or output for the master mode, and it is always the input for the slave mode. the bidirectional mode does not affect sck and ss functions. note in bidirectional master mode, with mode fault enabled, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirectional mode and miso is not used by the spi. if a mode fault occurs, the spi is automatically switched to slave mode. in this case miso becomes occupied by the spi and mosi is not used. this must be considered, if the miso pin is used for another purpose. table 16-8. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out bidiroe 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 637 16.4.6 error conditions the spi has one error condition: mode fault error 16.4.6.1 mode fault error if the ss input becomes low while the spi is con?ured as a master, it indicates a system error where more than one master may be trying to drive the mosi and sck lines simultaneously. this condition is not permitted in normal operation, the modf bit in the spi status register is set automatically, provided the modfen bit is set. in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf remains cleared. in case the spi system is con?ured as a slave, the ss pin is a dedicated input pin. mode fault error doesnt occur in slave mode. if a mode fault error occurs, the spi is switched to slave mode, with the exception that the slave output buffer is disabled. so sck, miso, and mosi pins are forced to be high impedance inputs to avoid any possibility of con?ct with another output driver. a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in the bidirectional mode for a spi system con?ured in master mode, output enable of the momi (mosi in bidirectional mode) is cleared if it was set. no mode fault error occurs in the bidirectional mode for spi system con?ured in slave mode. the mode fault ?g is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi control register 1. if the mode fault ?g is cleared, the spi becomes a normal master or slave again. note if a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 16.4.7 low power mode options 16.4.7.1 spi in run mode in run mode with the spi system enable (spe) bit in the spi control register clear, the spi system is in a low-power, disabled state. spi registers remain accessible, but clocks to the core of this module are disabled. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 638 freescale semiconductor 16.4.7.2 spi in wait mode spi operation in wait mode depends upon the state of the spiswai bit in spi control register 2. if spiswai is clear, the spi operates normally when the cpu is in wait mode if spiswai is set, spi clock generation ceases and the spi module enters a power conservation state when the cpu is in wait mode. if spiswai is set and the spi is configured for master, any transmission and reception in progress stops at wait mode entry. the transmission and reception resumes when the spi exits wait mode. if spiswai is set and the spi is configured as a slave, any transmission and reception in progress continues if the sck continues to be driven from the master. this keeps the slave synchronized to the master and the sck. if the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its spidr to the master, it will continue to send the same byte. else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). note care must be taken when expecting data from a master while the slave is in wait or stop mode. even though the shift register will continue to operate, the rest of the spi is shut down (i.e., a spif interrupt will not be generated until exiting stop or wait mode). also, the byte from the shift register will not be copied into the spidr register until after the slave spi has exited wait or stop mode. in slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. an spif ?g and spidr copy is generated only if wait mode is entered or exited during a tranmission. if the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a spif nor a spidr copy will occur. 16.4.7.3 spi in stop mode stop mode is dependent on the system. the spi enters stop mode when the module clock is disabled (held high or low). if the spi is in master mode and exchanging data when the cpu enters stop mode, the transmission is frozen until the cpu exits stop mode. after stop, data to and from the external spi is exchanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 639 16.4.7.4 reset the reset values of registers and signals are described in section 16.3, ?emory map and register de?ition , which details the registers and their bit ?lds. if a data transmission occurs in slave mode after reset without a write to spidr, it will transmit garbage, or the byte last received from the master before the reset. reading from the spidr after reset will always read a byte of zeros. 16.4.7.5 interrupts the spi only originates interrupt requests when spi is enabled (spe bit in spicr1 set). the following is a description of how the spi makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt priority are chip dependent. the interrupt ?gs modf, spif, and sptef are logically ored to generate an interrupt request. 16.4.7.5.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be con?ured for the modf feature (see table 16-2 ). after modf is set, the current transfer is aborted and the following bit is changed: mstr = 0, the master bit in spicr1 resets. the modf interrupt is re?cted in the status register modf ?g. clearing the ?g will also clear the interrupt. this interrupt will stay active while the modf ?g is set. modf has an automatic clearing process which is described in section 16.3.2.4, ?pi status register (spisr) . 16.4.7.5.2 spif spif occurs when new data has been received and copied to the spi data register. after spif is set, it does not clear until it is serviced. spif has an automatic clearing process, which is described in section 16.3.2.4, ?pi status register (spisr) . 16.4.7.5.3 sptef sptef occurs when the spi data register is ready to accept new data. after sptef is set, it does not clear until it is serviced. sptef has an automatic clearing process, which is described in section 16.3.2.4, ?pi status register (spisr) . 4 .com u datasheet
chapter 16 serial peripheral interface (spiv4) MC9S12XHZ512 data sheet, rev. 1.02 640 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 641 chapter 17 periodic interrupt timer (pit24b4cv1) 17.1 introduction the period interrupt timer (pit) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. refer to figure 17-1 for a simpli?d block diagram. 17.1.1 glossary 17.1.2 features the pit includes these features: four timers implemented as modulus down-counters with independent time-out periods. time-out periods selectable between 1 and 2 24 bus clock cycles. time-out equals m*n bus clock cycles with 1 <= m <= 256 and 1 <= n <= 65536. timers that can be enabled individually. four time-out interrupts. four time-out trigger output signals available to trigger peripheral modules. start of timer channels can be aligned to each other. 17.1.3 modes of operation refer to the soc guide for a detailed explanation of the chip modes. run mode this is the basic mode of operation. wait mode acronyms and abbreviations pit periodic interrupt timer isr interrupt service routine ccr condition code register soc system on chip micro time bases clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit modulus down-counters. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 642 freescale semiconductor pit operation in wait mode is controlled by the pitswai bit located in the pitcflmt register. in wait mode, if the bus clock is globally enabled and if the pitswai bit is clear, the pit operates like in run mode. in wait mode, if the pitswai bit is set, the pit module is stalled. stop mode in full stop mode or pseudo stop mode, the pit module is stalled. freeze mode pit operation in freeze mode is controlled by the pitfrz bit located in the pitcflmt register. in freeze mode, if the pitfrz bit is clear, the pit operates like in run mode. in freeze mode, if the pitfrz bit is set, the pit module is stalled. 17.1.4 block diagram figure 17-1 shows a block diagram of the pit. figure 17-1. pit block diagram 17.2 external signal description the pit module has no external pins. time-out 0 time-out 1 time-out 2 time-out 3 16-bit timer 1 16-bit timer 3 16-bit timer 0 16-bit timer 2 bus clock micro time base 0 micro time base 1 interrupt 0 trigger 0 interface interrupt 1 trigger 1 interface interrupt 2 trigger 2 interface interrupt 3 trigger 3 interface 8-bit micro timer 0 8-bit micro timer 1 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 643 17.3 memory map and register de?ition this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 6 5 4 3 2 1 bit 0 pitcflmt r pite pitswai pitfrz 00000 w pflmt1 pflmt0 pitflt r 00000000 w pflt3 pflt2 pflt1 pflt0 pitce r 0000 pce3 pce2 pce1 pce0 w pitmux r 0000 pmux3 pmux2 pmux1 pmux0 w pitinte r 0000 pinte3 pinte2 pinte1 pinte0 w pittf r 0000 ptf3 ptf2 ptf1 ptf0 w pitmtld0 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w pitmtld1 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w pitld0 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w pitld0 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w pitcnt0 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w pitcnt0 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w pitld1 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w = unimplemented or reserved figure 17-2. pit register summary (sheet 1 of 2) 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 644 freescale semiconductor pitld1 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w pitcnt1 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w pitcnt1 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w pitld2 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w pitld2 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w pitcnt2 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w pitcnt2 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w pitld3 (high) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w pitld3 (low) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w pitcnt3 (high) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w pitcnt3 (low) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 17-2. pit register summary (sheet 2 of 2) 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 645 17.3.0.1 pit control and force load micro timer register (pitcflmt) read: anytime write: anytime; writes to the reserved bits have no effect 76543210 r pite pitswai pitfrz 00000 w pflmt1 pflmt0 reset 0 0 0 00000 = unimplemented or reserved figure 17-3. pit control and force load micro timer register (pitcflmt) table 17-1. pitcflmt field descriptions field description 7 pite pit module enable bit ?this bit enables the pit module. if pite is cleared, the pit module is disabled and ?g bits in the pittf register are cleared. when pite is set, individually enabled timers (pce set) start down-counting with the corresponding load register values. 0 pit disabled (lower power consumption). 1 pit is enabled. 6 pitswai pit stop in wait mode bit ?this bit is used for power conservation while in wait mode. 0 pit operates normally in wait mode 1 pit clock generation stops and freezes the pit module when in wait mode 5 pitfrz pit counter freeze while in freeze mode bit ?when during debugging a breakpoint (freeze mode) is encountered it is useful in many cases to freeze the pit counters to avoid e.g. interrupt generation. the pitfrz bit controls the pit operation while in freeze mode. 0 pit operates normally in freeze mode 1 pit counters are stalled when in freeze mode 1:0 pflmt[1:0] pit force load bits for micro timer 1:0 these bits have only an effect if the corresponding micro timer is active and if the pit module is enabled (pite set). writing a one into a pflmt bit loads the corresponding 8-bit micro timer load register into the 8-bit micro timer down-counter. writing a zero has no effect. reading these bits will always return zero. note: a micro timer force load affects all timer channels that use the corresponding micro time base. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 646 freescale semiconductor 17.3.0.2 pit force load timer register (pitflt) read: anytime write: anytime; writes to the reserved bits have no effect 17.3.0.3 pit channel enable register (pitce) read: anytime write: anytime; writes to the reserved bits have no effect 76543210 r00000000 w pflt3 pflt2 pflt1 pflt0 reset 0 0 0 00000 = unimplemented or reserved figure 17-4. pit force load timer register (pitflt) table 17-2. pitflt field descriptions field description 3:0 pflt[3:0] pit force load bits for timer 3-0 ?these bits have only an effect if the corresponding timer channel (pce set) is enabled and if the pit module is enabled (pite set). writing a one into a pflt bit loads the corresponding 16-bit timer load register into the 16-bit timer down-counter. writing a zero has no effect. reading these bits will always return zero. 76543210 r0000 pce3 pce2 pce1 pce0 w reset 0 0 0 00000 = unimplemented or reserved figure 17-5. pit channel enable register (pitce) table 17-3. pitce field descriptions field description 3:0 pce[3:0] pit enable bits for timer channel 3:0 ?these bits enable the pit channels 3-0. if pce is cleared, the pit channel is disabled and the corresponding ?g bit in the pittf register is cleared. when pce is set, and if the pit module is enabled (pite = 1) the 16-bit timer counter is loaded with the start count value and starts down-counting. 0 the corresponding pit channel is disabled. 1 the corresponding pit channel is enabled. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 647 17.3.0.4 pit multiplex register (pitmux) read: anytime write: anytime; writes to the reserved bits have no effect 17.3.0.5 pit interrupt enable register (pitinte) read: anytime write: anytime; writes to the reserved bits have no effect 76543210 r0000 pmux3 pmux2 pmux1 pmux0 w reset 0 0 0 00000 = unimplemented or reserved figure 17-6. pit multiplex register (pitmux) table 17-4. pitmux field descriptions field description 3:0 pmux[3:0] pit multiplex bits for timer channel 3:0 these bits select if the corresponding 16-bit timer is connected to micro time base 1 or 0. if pmux is modi?d, the corresponding 16-bit timer is immediately switched to the other micro time base. 0 the corresponding 16-bit timer counts with micro time base 0. 1 the corresponding 16-bit timer counts with micro time base 1. 76543210 r0000 pinte3 pinte2 pinte1 pinte0 w reset 0 0 0 00000 = unimplemented or reserved figure 17-7. pit interrupt enable register (pitinte) table 17-5. pitinte field descriptions field description 3:0 pinte[3:0] pit time-out interrupt enable bits for timer channel 3:0 ?these bits enable an interrupt service request whenever the time-out ?g ptf of the corresponding pit channel is set. when an interrupt is pending (ptf set) enabling the interrupt will immediately cause an interrupt. to avoid this, the corresponding ptf ?g has to be cleared ?st. 0 interrupt of the corresponding pit channel is disabled. 1 interrupt of the corresponding pit channel is enabled. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 648 freescale semiconductor 17.3.0.6 pit time-out flag register (pittf) read: anytime write: anytime (write to clear); writes to the reserved bits have no effect 17.3.0.7 pit micro timer load register 0 to 1 (pitmtld0?) read: anytime write: anytime 76543210 r0000 ptf3 ptf2 ptf1 ptf0 w reset 0 0 0 00000 = unimplemented or reserved figure 17-8. pit time-out flag register (pittf) table 17-6. pittf field descriptions field description 3:0 ptf[3:0] pit time-out flag bits for timer channel 3:0 ?ptf is set when the corresponding 16-bit timer modulus down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. the ?g can be cleared by writing a one to the ?g bit. writing a zero has no effect. if ?g clearing by writing a one and ?g setting happen in the same bus clock cycle, the ?g remains set. the ?g bits are cleared if the pit module is disabled or if the corresponding timer channel is disabled. 0 time-out of the corresponding pit channel has not yet occurred. 1 time-out of the corresponding pit channel has occurred. 76543210 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w reset 0 0 0 00000 figure 17-9. pit micro timer load register 0 (pitmtld0) 76543210 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w reset 0 0 0 00000 figure 17-10. pit micro timer load register 1 (pitmtld1) table 17-7. pitmtld0? field descriptions field description 7:0 pmtld[7:0] pit micro timer load bits 7:0 these bits set the 8-bit modulus down-counter load value of the micro timers. writing a new value into the pitmtld register will not restart the timer. when the micro timer has counted down to zero, the pmtld register value will be loaded. the pflmt bits in the pitcflmt register can be used to immediately update the count register with the new value if an immediate load is desired. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 649 17.3.0.8 pit load register 0 to 3 (pitld0?) read: anytime write: anytime 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 17-11. pit load register 0 (pitld0) 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 17-12. pit load register 1 (pitld1) 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 17-13. pit load register 2 (pitld2) 15 14 13 12 11 10 9876543210 r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w reset 000000 0000000000 figure 17-14. pit load register 3 (pitld3) table 17-8. pitld0? field descriptions field description 15:0 pld[15:0] pit load bits 15:0 these bits set the 16-bit modulus down-counter load value. writing a new value into the pitld register must be a 16-bit access, to ensure data consistency. it will not restart the timer. when the timer has counted down to zero the ptf time-out ?g will be set and the register value will be loaded. the pflt bits in the pitflt register can be used to immediately update the count register with the new value if an immediate load is desired. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 650 freescale semiconductor 17.3.0.9 pit count register 0 to 3 (pitcnt0?) read: anytime write: has no meaning or effect 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 17-15. pit count register 0 (pitcnt0) 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 17-16. pit count register 1 (pitcnt1) 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 17-17. pit count register 2 (pitcnt2) 15 14 13 12 11 10 9876543210 r pcnt 15 pcnt 14 pcnt 13 pcnt 12 pcnt 11 pcnt 10 pcnt 9 pcnt 8 pcnt 7 pcnt 6 pcnt 5 pcnt 4 pcnt 3 pcnt 2 pcnt 1 pcnt 0 w reset 000000 0000000000 figure 17-18. pit count register 3 (pitcnt3) table 17-9. pitcnt0? field descriptions field description 15:0 pcnt[15:0] pit count bits 15-0 ?these bits represent the current 16-bit modulus down-counter value. the read access for the count register must take place in one clock cycle as a 16-bit access. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 651 17.4 functional description figure 17-19 shows a detailed block diagram of the pit module. the main parts of the pit are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface. figure 17-19. pit detailed block diagram 17.4.1 timer as shown in figure 17-1 and figure 17-19 , the 24-bit timers are built in a two-stage architecture with four 16-bit modulus down-counters and two 8-bit modulus down-counters. the 16-bit timers are clocked with two selectable micro time bases which are generated with 8-bit modulus down-counters. each 16-bit timer is connected to micro time base 0 or 1 via the pmux[3:0] bit setting in the pit multiplex (pitmux) register. a timer channel is enabled if the module enable bit pite in the pit control and force load micro timer (pitcflmt) register is set and if the corresponding pce bit in the pit channel enable (pitce) register is set. two 8-bit modulus down-counters are used to generate two micro time bases. as soon as a micro time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter will load its start value as speci?d in the pitmtld0 or pitmtld1 register and will start down-counting. whenever the micro timer down-counter has counted to zero the pitmtld register is reloaded and the connected 16-bit modulus down-counters count one cycle. pitmld0 register 8-bit micro timer 0 pitcflmt register pitld0 register pitmld1 register 8-bit micro timer 1 pitmux register pitflt register pitcnt0 register timer 0 pmux0 pflt0 4 4 pittf register pitinte register interrupt / hardware trigger 4 interrupt request 4 pitld1 register pitcnt1 register timer 1 [1] pflt1 pitld2 register pitcnt2 register timer 2 [2] pflt2 pitld3 register pitcnt3 register timer 3 pmux3 pflt3 time-out 0 time- out 1 time- out 2 time-out 3 pflmt [1] [0] pmux trigger interface bus clock pit_24b4c 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 652 freescale semiconductor whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the pitld register is reloaded and the corresponding time-out ?g ptf in the pit time-out ?g (pittf) register is set, as shown in figure 17-20 . the time-out period is a function of the timer load (pitld) and micro timer load (pitmtld) registers and the bus clock f bus : time-out period = (pitmtld + 1) * (pitld + 1) / f bus . for example, for a 40 mhz bus clock, the maximum time-out period equals: 256 * 65536 * 25 ns = 419.43 ms. the current 16-bit modulus down-counter value can be read via the pitcnt register. the micro timer down-counter values cannot be read. the 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro timer pflmt bits in the pit control and force load micro timer (pitcflmt) register. the 16-bit timers can individually be restarted by writing a one to the corresponding force load timer pflt bits in the pit forceload timer (pitflt) register. if desired, any group of timers and micro timers can be restarted at the same time by using one 16-bit write to the adjacent pitcflmt and pitflt registers with the relevant bits set, as shown in figure 17-20 . figure 17-20. pit trigger and flag signal timing 17.4.2 interrupt interface each time-out event can be used to trigger an interrupt service request. for each timer channel, an individual bit pinte in the pit interrupt enable (pitinte) register exists to enable this feature. if pinte bus clock 02 1 0 8-bit micro 2 1 0 2 1 0 2 1 2 1 0 pitcnt register 0001 0000 00 0001 0000 8-bit force load 2 1 0 2 1 0 ptf flag 1 pittrig 16-bit force load 0001 0000 0001 2 time-out period time-out period after restart timer counter note 1. the ptf ?g clearing depends on the software 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 653 is set, an interrupt service is requested whenever the corresponding time-out ?g ptf in the pit time-out ?g (pittf) register is set. the ?g can be cleared by writing a one to the ?g bit. note be careful when resetting the pite, pinte or pitce bits in case of pending pit interrupt requests, to avoid spurious interrupt requests. 17.4.3 hardware trigger the pit module contains four hardware trigger signal lines pittrig[3:0], one for each timer channel. these signals can be connected on soc level to peripheral modules enabling e.g. periodic atd conversion (please refer to the soc guide for the mapping of pittrig[3:0] signals to peripheral modules). whenever a timer channel time-out is reached, the corresponding ptf ?g is set and the corresponding trigger signal pittrig triggers a rising edge. the trigger feature requires a minimum time-out period of two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. for load register values pitld = 0x0001 and pitmtld = 0x0002 the ?g setting, trigger timing and a restart with force load is shown in figure 17-20 . 17.5 initialization/application information 17.5.1 startup set the con?uration registers before the pite bit in the pitcflmt register is set. before pite is set, the con?uration registers can be written in arbitrary order. 17.5.2 shutdown when the pitce register bits, the pitinte register bits or the pite bit in the pitcflmt register are cleared, the corresponding pit interrupt ?gs are cleared. in case of a pending pit interrupt request, a spurious interrupt can be generated. two strategies, which avoid spurious interrupts, are recommended: 1. reset the pit interrupt ?gs only in an isr. when entering the isr, the i mask bit in the ccr is set automatically. the i mask bit must not be cleared before the pit interrupt ?gs are cleared. 2. after setting the i mask bit with the sei instruction, the pit interrupt ?gs can be cleared. then clear the i mask bit with the cli instruction to re-enable interrupts. 17.5.3 flag clearing a ?g is cleared by writing a one to the ?g bit. always use store or move instructions to write a one in certain bit positions. do not use the bset instructions. do not use any c-constructs that compile to bset instructions. ?set ?g_register, #mask?must not be used for ?g clearing because bset is a read-modify-write instruction which writes back the ?it-wise or?of the ?g_register and the mask into the ?g_register. bset would clear all ?g bits that were set, independent from the mask. for example, to clear ?g bit 0 use: movb #$01,pittf. 4 .com u datasheet
chapter 17 periodic interrupt timer (pit24b4cv1) MC9S12XHZ512 data sheet, rev. 1.02 654 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 655 chapter 18 pulse-width modulator (pwm8b8cv1) 18.1 introduction the pwm de?ition is based on the hc12 pwm de?itions. it contains the basic features from the hc11 with some of the enhancements incorporated on the hc12: center aligned output mode and four available clock sources.the pwm module has eight channels with independent control of left and center aligned outputs on each channel. each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. a ?xible clock select scheme allows a total of four different clock sources to be used with the counters. each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. the pwm outputs can be programmed as left aligned outputs or center aligned outputs. 18.1.1 features the pwm block includes these distinctive features: eight independent pwm channels with programmable period and duty cycle dedicated counter for each pwm channel programmable pwm enable/disable for each channel software selection of pwm duty pulse polarity for each channel period and duty cycle are double buffered. change takes effect when the end of the effective period is reached (pwm counter reaches zero) or when the channel is disabled. programmable center or left aligned outputs on individual channels eight 8-bit channel or four 16-bit channel pwm resolution four clock sources (a, b, sa, and sb) provide for a wide range of frequencies programmable clock select logic emergency shutdown 18.1.2 modes of operation there is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. in freeze mode there is a software programmable option to disable the input clock to the prescaler. this is useful for emulation. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 656 freescale semiconductor 18.1.3 block diagram figure 18-1 shows the block diagram for the 8-bit 8-channel pwm block. figure 18-1. pwm block diagram 18.2 external signal description the pwm module has a total of 8 external pins. 18.2.1 pwm7 ?pwm channel 7 this pin serves as waveform output of pwm channel 7 and as an input for the emergency shutdown feature. 18.2.2 pwm6 ?pwm channel 6 this pin serves as waveform output of pwm channel 6. period and duty counter channel 6 clock select pwm clock period and duty counter channel 5 period and duty counter channel 4 period and duty counter channel 3 period and duty counter channel 2 period and duty counter channel 1 alignment polarity control pwm8b8c pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 enable pwm channels period and duty counter channel 7 period and duty counter channel 0 pwm0 pwm7 bus clock 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 657 18.2.3 pwm5 ?pwm channel 5 this pin serves as waveform output of pwm channel 5. 18.2.4 pwm4 ?pwm channel 4 this pin serves as waveform output of pwm channel 4. 18.2.5 pwm3 ?pwm channel 3 this pin serves as waveform output of pwm channel 3. 18.2.6 pwm3 ?pwm channel 2 this pin serves as waveform output of pwm channel 2. 18.2.7 pwm3 ?pwm channel 1 this pin serves as waveform output of pwm channel 1. 18.2.8 pwm3 ?pwm channel 0 this pin serves as waveform output of pwm channel 0. 18.3 memory map and register de?ition this section describes in detail all the registers and register bits in the pwm module. the special-purpose registers and register bit functions that are not normally available to device end users, such as factory test control registers and reserved registers, are clearly identi?d by means of shading the appropriate portions of address maps and register diagrams. notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions. 18.3.1 module memory map this section describes the content of the registers in the pwm module. the base address of the pwm module is determined at the mcu level when the mcu is de?ed. the register decode map is ?ed and begins at the ?st address of the module address offset. the ?ure below shows the registers associated with the pwm and their relative offset from the base address. the register detail description follows the order they appear in the register map. reserved bits within a register will always read as 0 and the write will be unimplemented. unimplemented functions are indicated by shading the bit. . 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 658 freescale semiconductor note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. 18.3.2 register descriptions this section describes in detail all the registers and register bits in the pwm module. register name bit 7 6 5 4 3 2 1 bit 0 pwme r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w pwmclk r pclk7 pclkl6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w pwmprclk r 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w pwmcae r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w pwmctl r con67 con45 con23 con01 pswai pfrz 00 w pwmtst 1 r00 0 00000 w pwmprsc 1 r00 0 00000 w pwmscla r bit 7 6 5 4 3 2 1 bit 0 w pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w pwmscnta 1 r00 0 00000 w pwmscntb 1 r00 0 00000 w = unimplemented or reserved figure 18-2. pwm register summary (sheet 1 of 3) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 659 pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt2 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt3 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt4 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt5 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt6 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmcnt7 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w pwmper6 r bit 7 6 5 4 3 2 1 bit 0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 18-2. pwm register summary (sheet 2 of 3) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 660 freescale semiconductor 18.3.2.1 pwm enable register (pwme) each pwm channel has an enable bit (pwmex) to start its waveform output. when any of the pwmex bits are set (pwmex = 1), the associated pwm output is enabled immediately. however, the actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle due to the synchronization of pwmex and the clock source. note the ?st pwm cycle after enabling the channel can be irregular. an exception to this is when channels are concatenated. once concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the pwmper7 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty6 r bit 7 6 5 4 3 2 1 bit 0 w pwmdty7 r bit 7 6 5 4 3 2 1 bit 0 w pwmsdn r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena w pwmrstrt 1 intended for factory test purposes only. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 18-2. pwm register summary (sheet 3 of 3) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 661 low order pwmex bit.in this case, the high order bytes pwmex bits have no effect and their corresponding pwm output lines are disabled. while in run mode, if all eight pwm channels are disabled (pwme7? = 0), the prescaler counter shuts off for power savings. read: anytime write: anytime 76543210 r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w reset 0 0 0 00000 figure 18-3. pwm enable register (pwme) table 18-1. pwme field descriptions field description 7 pwme7 pulse width channel 7 enable 0 pulse width channel 7 is disabled. 1 pulse width channel 7 is enabled. the pulse modulated signal becomes available at pwm output bit 7 when its clock source begins its next cycle. 6 pwme6 pulse width channel 6 enable 0 pulse width channel 6 is disabled. 1 pulse width channel 6 is enabled. the pulse modulated signal becomes available at pwm output bit6 when its clock source begins its next cycle. if con67=1, then bit has no effect and pwm output line 6 is disabled. 5 pwme5 pulse width channel 5 enable 0 pulse width channel 5 is disabled. 1 pulse width channel 5 is enabled. the pulse modulated signal becomes available at pwm output bit 5 when its clock source begins its next cycle. 4 pwme4 pulse width channel 4 enable 0 pulse width channel 4 is disabled. 1 pulse width channel 4 is enabled. the pulse modulated signal becomes available at pwm, output bit 4 when its clock source begins its next cycle. if con45 = 1, then bit has no effect and pwm output bit4 is disabled. 3 pwme3 pulse width channel 3 enable 0 pulse width channel 3 is disabled. 1 pulse width channel 3 is enabled. the pulse modulated signal becomes available at pwm, output bit 3 when its clock source begins its next cycle. 2 pwme2 pulse width channel 2 enable 0 pulse width channel 2 is disabled. 1 pulse width channel 2 is enabled. the pulse modulated signal becomes available at pwm, output bit 2 when its clock source begins its next cycle. if con23 = 1, then bit has no effect and pwm output bit2 is disabled. 1 pwme1 pulse width channel 1 enable 0 pulse width channel 1 is disabled. 1 pulse width channel 1 is enabled. the pulse modulated signal becomes available at pwm, output bit 1 when its clock source begins its next cycle. 0 pwme0 pulse width channel 0 enable 0 pulse width channel 0 is disabled. 1 pulse width channel 0 is enabled. the pulse modulated signal becomes available at pwm, output bit 0 when its clock source begins its next cycle. if con01 = 1, then bit has no effect and pwm output line0 is disabled. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 662 freescale semiconductor 18.3.2.2 pwm polarity register (pwmpol) the starting polarity of each pwm channel waveform is determined by the associated ppolx bit in the pwmpol register. if the polarity bit is one, the pwm channel output is high at the beginning of the cycle and then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. read: anytime write: anytime note ppolx register bits can be written anytime. if the polarity is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition 18.3.2.3 pwm clock select register (pwmclk) each pwm channel has a choice of two clocks to use as the clock source for that channel as described below. read: anytime write: anytime 76543210 r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w reset 0 0 0 00000 figure 18-4. pwm polarity register (pwmpol) table 18-2. pwmpol field descriptions field description 7? ppol[7:0] p ulse width channel 7? polarity bits 0 pwm channel 7? outputs are low at the beginning of the period, then go high when the duty count is reached. 1 pwm channel 7? outputs are high at the beginning of the period, then go low when the duty count is reached. 76543210 r pclk7 pclkl6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w reset 0 0 0 00000 figure 18-5. pwm clock select register (pwmclk) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 663 note register bits pclk0 to pclk7 can be written anytime. if a clock select is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 18.3.2.4 pwm prescale clock select register (pwmprclk) this register selects the prescale clock source for clocks a and b independently. read: anytime write: anytime table 18-3. pwmclk field descriptions field description 7 pclk7 pulse width channel 7 clock select 0 clock b is the clock source for pwm channel 7. 1 clock sb is the clock source for pwm channel 7. 6 pclk6 pulse width channel 6 clock select 0 clock b is the clock source for pwm channel 6. 1 clock sb is the clock source for pwm channel 6. 5 pclk5 pulse width channel 5 clock select 0 clock a is the clock source for pwm channel 5. 1 clock sa is the clock source for pwm channel 5. 4 pclk4 pulse width channel 4 clock select 0 clock a is the clock source for pwm channel 4. 1 clock sa is the clock source for pwm channel 4. 3 pclk3 pulse width channel 3 clock select 0 clock b is the clock source for pwm channel 3. 1 clock sb is the clock source for pwm channel 3. 2 pclk2 pulse width channel 2 clock select 0 clock b is the clock source for pwm channel 2. 1 clock sb is the clock source for pwm channel 2. 1 pclk1 pulse width channel 1 clock select 0 clock a is the clock source for pwm channel 1. 1 clock sa is the clock source for pwm channel 1. 0 pclk0 pulse width channel 0 clock select 0 clock a is the clock source for pwm channel 0. 1 clock sa is the clock source for pwm channel 0. 76543210 r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w reset 0 0 0 00000 = unimplemented or reserved figure 18-6. pwm prescale clock select register (pwmprclk) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 664 freescale semiconductor note pckb2? and pcka2? register bits can be written anytime. if the clock pre-scale is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. s 18.3.2.5 pwm center align enable register (pwmcae) the pwmcae register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each pwm channel. if the caex bit is set to a one, the corresponding pwm output will be center aligned. if the caex bit is cleared, the corresponding pwm output will be left aligned. see section 18.4.2.5, ?eft aligned outputs and section 18.4.2.6, ?enter aligned outputs for a more detailed description of the pwm output modes. table 18-4. pwmprclk field descriptions field description 6? pckb[2:0] prescaler select for clock b clock b is one of two clock sources which can be used for channels 2, 3, 6, or 7. these three bits determine the rate of clock b, as shown in table 18-5 . 2? pcka[2:0] prescaler select for clock a clock a is one of two clock sources which can be used for channels 0, 1, 4 or 5. these three bits determine the rate of clock a, as shown in table 18-6 . table 18-5. clock b prescaler selects pckb2 pckb1 pckb0 value of clock b 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 table 18-6. clock a prescaler selects pcka2 pcka1 pcka0 value of clock a 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 76543210 r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w reset 0 0 0 00000 figure 18-7. pwm center align enable register (pwmcae) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 665 read: anytime write: anytime note write these bits only when the corresponding channel is disabled. 18.3.2.6 pwm control register (pwmctl) the pwmctl register provides for various control of the pwm module. read: anytime write: anytime there are three control bits for concatenation, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. when channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. when channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. when channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. see section 18.4.2.7, ?wm 16-bit functions for a more detailed description of the concatenation pwm function. note change these bits only when both corresponding channels are disabled. table 18-7. pwmcae field descriptions field description 7? cae[7:0] center aligned output modes on channels 7? 0 channels 7? operate in left aligned output mode. 1 channels 7? operate in center aligned output mode. 76543210 r con67 con45 con23 con01 pswai pfrz 00 w reset 0 0 0 00000 = unimplemented or reserved figure 18-8. pwm control register (pwmctl) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 666 freescale semiconductor 18.3.2.7 reserved register (pwmtst) this register is reserved for factory testing of the pwm module and is not available in normal modes. table 18-8. pwmctl field descriptions field description 7 con67 concatenate channels 6 and 7 0 channels 6 and 7 are separate 8-bit pwms. 1 channels 6 and 7 are concatenated to create one 16-bit pwm channel. channel 6 becomes the high order byte and channel 7 becomes the low order byte. channel 7 output pin is used as the output for this 16-bit pwm (bit 7 of port pwmp). channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. 6 con45 concatenate channels 4 and 5 0 channels 4 and 5 are separate 8-bit pwms. 1 channels 4 and 5 are concatenated to create one 16-bit pwm channel. channel 4 becomes the high order byte and channel 5 becomes the low order byte. channel 5 output pin is used as the output for this 16-bit pwm (bit 5 of port pwmp). channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. 5 con23 concatenate channels 2 and 3 0 channels 2 and 3 are separate 8-bit pwms. 1 channels 2 and 3 are concatenated to create one 16-bit pwm channel. channel 2 becomes the high order byte and channel 3 becomes the low order byte. channel 3 output pin is used as the output for this 16-bit pwm (bit 3 of port pwmp). channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. 4 con01 concatenate channels 0 and 1 0 channels 0 and 1 are separate 8-bit pwms. 1 channels 0 and 1 are concatenated to create one 16-bit pwm channel. channel 0 becomes the high order byte and channel 1 becomes the low order byte. channel 1 output pin is used as the output for this 16-bit pwm (bit 1 of port pwmp). channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. 3 pswai pwm stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 allow the clock to the prescaler to continue while in wait mode. 1 stop the input clock to the prescaler whenever the mcu is in wait mode. 2 pfrez pwm counters stop in freeze mode ?in freeze mode, there is an option to disable the input clock to the prescaler by setting the pfrz bit in the pwmctl register. if this bit is set, whenever the mcu is in freeze mode, the input clock to the prescaler is disabled. this feature is useful during emulation as it allows the pwm function to be suspended. in this way, the counters of the pwm can be stopped while in freeze mode so that once normal program ow is continued, the counters are re-enabled to simulate real-time operations. since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the pfrz bit or exit freeze mode. 0 allow pwm to continue while in freeze mode. 1 disable pwm input clock to the prescaler whenever the part is in freeze mode. this is useful for emulation. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 667 read: always read $00 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 18.3.2.8 reserved register (pwmprsc) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read $00 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 18.3.2.9 pwm scale a register (pwmscla) pwmscla is the programmable scale value used in scaling clock a to generate clock sa. clock sa is generated by taking clock a, dividing it by the value in the pwmscla register and dividing that by two. clock sa = clock a / (2 * pwmscla) note when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmscla). 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 18-9. reserved register (pwmtst) 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 18-10. reserved register (pwmprsc) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 668 freescale semiconductor read: anytime write: anytime (causes the scale counter to load the pwmscla value) 18.3.2.10 pwm scale b register (pwmsclb) pwmsclb is the programmable scale value used in scaling clock b to generate clock sb. clock sb is generated by taking clock b, dividing it by the value in the pwmsclb register and dividing that by two. clock sb = clock b / (2 * pwmsclb) note when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmsclb). read: anytime write: anytime (causes the scale counter to load the pwmsclb value). 18.3.2.11 reserved registers (pwmscntx) the registers pwmscnta and pwmscntb are reserved for factory testing of the pwm module and are not available in normal modes. read: always read $00 in normal modes write: unimplemented in normal modes 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 0 0 0 00000 figure 18-11. pwm scale a register (pwmscla) 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 0 0 0 00000 figure 18-12. pwm scale b register (pwmsclb) 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 18-13. reserved registers (pwmscntx) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 669 note writing to these registers when in special modes can alter the pwm functionality. 18.3.2.12 pwm channel counter registers (pwmcntx) each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. the counter can be read at any time without affecting the count or the operation of the pwm channel. in left aligned output mode, the counter counts from 0 to the value in the period register - 1. in center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. the counter is also cleared at the end of the effective period (see section 18.4.2.5, ?eft aligned outputs and section 18.4.2.6, ?enter aligned outputs for more details). when the channel is disabled (pwmex = 0), the pwmcntx register does not count. when a channel becomes enabled (pwmex = 1), the associated pwm counter starts at the count in the pwmcntx register. for more detailed information on the operation of the counters, see section 18.4.2.4, ?wm timer counters . in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. read: anytime write: anytime (any value written causes pwm counter to be reset to $00). 18.3.2.13 pwm channel period registers (pwmperx) there is a dedicated period register for each channel. the value in this register determines the period of the associated pwm channel. the period registers for each channel are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset 0 0 0 00000 figure 18-14. pwm channel counter registers (pwmcntx) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 670 freescale semiconductor in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active period due to the double buffering scheme. see section 18.4.2.3, ?wm period and duty for more information. to calculate the output period, take the selected clock source period for the channel of interest (a, b, sa, or sb) and multiply it by the value in the period register for that channel: left aligned output (caex = 0) pwmx period = channel clock period * pwmperx center aligned output (caex = 1) pwmx period = channel clock period * (2 * pwmperx) for boundary case programming values, please refer to section 18.4.2.8, ?wm boundary cases . read: anytime write: anytime 18.3.2.14 pwm channel duty registers (pwmdtyx) there is a dedicated duty register for each channel. the value in this register determines the duty of the associated pwm channel. the duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. the duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old duty waveform or the new duty waveform, not some variation in between. if the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 1 1 1 11111 figure 18-15. pwm channel period registers (pwmperx) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 671 note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active duty due to the double buffering scheme. see section 18.4.2.3, ?wm period and duty for more information. note depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. if the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. if the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. to calculate the output duty cycle (high time as a% of period) for a particular channel: polarity = 0 (ppol x =0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% for boundary case programming values, please refer to section 18.4.2.8, ?wm boundary cases . read: anytime write: anytime 18.3.2.15 pwm shutdown register (pwmsdn) the pwmsdn register provides for the shutdown functionality of the pwm module in the emergency cases. for proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. read: anytime write: anytime 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 1 1 1 11111 figure 18-16. pwm channel duty registers (pwmdtyx) 76543210 r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena w pwmrstrt reset 0 0 0 00000 = unimplemented or reserved figure 18-17. pwm shutdown register (pwmsdn) 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 672 freescale semiconductor 18.4 functional description 18.4.1 pwm clock select there are four available clocks: clock a, clock b, clock sa (scaled a), and clock sb (scaled b). these four clocks are based on the bus clock. clock a and b can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. clock sa uses clock a as an input and divides it further with a reloadable counter. similarly, clock sb uses clock b as an input and divides it further with a reloadable counter. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for clock sb. each pwm channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock a or b) or the scaled clock (clock sa or sb). the block diagram in figure 18-18 shows the four different clocks and how the scaled clocks are created. table 18-9. pwmsdn field descriptions field description 7 pwmif pwm interrupt flag ?any change from passive to asserted (active) state or from active to passive state will be ?gged by setting the pwmif ?g = 1. the ?g is cleared by writing a logic 1 to it. writing a 0 has no effect. 0 no change on pwm7in input. 1 change on pwm7in input 6 pwmie pwm interrupt enable ?if interrupt is enabled an interrupt to the cpu is asserted. 0 pwm interrupt is disabled. 1 pwm interrupt is enabled. 5 pwmrstrt pwm restart the pwm can only be restarted if the pwm channel input 7 is de-asserted. after writing a logic 1 to the pwmrstrt bit (trigger event) the pwm channels start running after the corresponding counter passes next ?ounter == 0?phase. also, if the pwm7ena bit is reset to 0, the pwm do not start before the counter passes $00. the bit is always read as ?? 4 pwmlvl pwm shutdown output level if active level as de?ed by the pwm7in input, gets asserted all enabled pwm channels are immediately driven to the level de?ed by pwmlvl. 0 pwm outputs are forced to 0 1 outputs are forced to 1. 2 pwm7in pwm channel 7 input status ?this re?cts the current status of the pwm7 pin. 1 pwm7inl pwm shutdown active input level for channel 7 ?if the emergency shutdown feature is enabled (pwm7ena = 1), this bit determines the active level of the pwm7channel. 0 active level is low 1 active level is high 0 pwm7ena pwm emergency shutdown enable if this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled. all the other bits in this register are meaningful only if pwm7ena = 1. 0 pwm emergency feature disabled. 1 pwm emergency feature is enabled. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 673 18.4.1.1 prescale the input clock to the pwm prescaler is the bus clock. it can be disabled whenever the part is in freeze mode by setting the pfrz bit in the pwmctl register. if this bit is set, whenever the mcu is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. this is useful for emulation in order to freeze the pwm. the input clock can also be disabled when all eight pwm channels are disabled (pwme7-0 = 0). this is useful for reducing power by disabling the prescale counter. clock a and clock b are scaled values of the input clock. the value is software selectable for both clock a and clock b and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. the value selected for clock a is determined by the pcka2, pcka1, pcka0 bits in the pwmprclk register. the value selected for clock b is determined by the pckb2, pckb1, pckb0 bits also in the pwmprclk register. 18.4.1.2 clock scale the scaled a clock uses clock a as an input and divides it further with a user programmable value and then divides this by 2. the scaled b clock uses clock b as an input and divides it further with a user programmable value and then divides this by 2. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for clock sb. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 674 freescale semiconductor figure 18-18. pwm clock select block diagram 128 248163264 pckb2 pckb1 pckb0 m u x clock a clock b clock sa clock a/2, a/4, a/6,....a/512 prescale scale divide by pfrz freeze mode signal bus clock clock select m u x pclk0 clock to pwm ch 0 m u x pclk2 clock to pwm ch 2 m u x pclk1 clock to pwm ch 1 m u x pclk4 clock to pwm ch 4 m u x pclk5 clock to pwm ch 5 m u x pclk6 clock to pwm ch 6 m u x pclk7 clock to pwm ch 7 m u x pclk3 clock to pwm ch 3 load div 2 pwmsclb clock sb clock b/2, b/4, b/6,....b/512 m u x pcka2 pcka1 pcka0 pwme7-0 count = 1 load div 2 pwmscla count = 1 8-bit down counter 8-bit down counter prescaler taps: 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 675 clock a is used as an input to an 8-bit down counter. this down counter loads a user programmable scale value from the scale register (pwmscla). when the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. the output signal from this circuit is further divided by two. this gives a greater range with only a slight reduction in granularity. clock sa equals clock a divided by two times the value in the pwmscla register. note clock sa = clock a / (2 * pwmscla) when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. similarly, clock b is used as an input to an 8-bit down counter followed by a divide by two producing clock sb. thus, clock sb equals clock b divided by two times the value in the pwmsclb register. note clock sb = clock b / (2 * pwmsclb) when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. as an example, consider the case in which the user writes $ff into the pwmscla register. clock a for this case will be e divided by 4. a pulse will occur at a rate of once every 255x4 e cycles. passing this through the divide by two circuit produces a clock signal at an e divided by 2040 rate. similarly, a value of $01 in the pwmscla register when clock a is e divided by 4 will produce a clock at an e divided by 8 rate. writing to pwmscla or pwmsclb causes the associated 8-bit down counter to be re-loaded. otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. forcing the associated counter to re-load the scale register value every time pwmscla or pwmsclb is written prevents this. note writing to the scale registers while channels are operating can cause irregularities in the pwm outputs. 18.4.1.3 clock select each pwm channel has the capability of selecting one of two clocks. for channels 0, 1, 4, and 5 the clock choices are clock a or clock sa. for channels 2, 3, 6, and 7 the choices are clock b or clock sb. the clock selection is done with the pclkx control bits in the pwmclk register. note changing clock control bits while channels are operating can cause irregularities in the pwm outputs. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 676 freescale semiconductor 18.4.2 pwm channel timers the main part of the pwm module are the actual timers. each of the timer channels has a counter, a period register and a duty register (each are 8-bit). the waveform output period is controlled by a match between the period register and the value in the counter. the duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. the starting polarity of the output is also selectable on a per channel basis. shown below in figure 18-19 is the block diagram for the pwm timer. figure 18-19. pwm timer channel block diagram 18.4.2.1 pwm enable each pwm channel has an enable bit (pwmex) to start its waveform output. when any of the pwmex bits are set (pwmex = 1), the associated pwm output signal is enabled immediately. however, the actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle due to the synchronization of pwmex and the clock source. an exception to this is when channels are concatenated. refer to section 18.4.2.7, ?wm 16-bit functions for more detail. note the ?st pwm cycle after enabling the channel can be irregular. clock source t r q q ppolx from port pwmp data register pwmex to pin driver gate 8-bit compare = pwmdtyx 8-bit compare = pwmperx caex t r q q 8-bit counter pwmcntx m u x m u x (clock edge sync) up/down reset 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 677 on the front end of the pwm timer, the clock is enabled to the pwm circuit by the pwmex bit being high. there is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. when the channel is disabled (pwmex = 0), the counter for the channel does not count. 18.4.2.2 pwm polarity each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. this is shown on the block diagram as a mux select of either the q output or the q output of the pwm output ?p ?p. when one of the bits in the pwmpol register is set, the associated pwm channel output is high at the beginning of the waveform, then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. 18.4.2.3 pwm period and duty dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. a change in duty or period can be forced into effect ?mmediately?by writing the new value to the duty and/or period registers and then writing to the counter. this forces the counter to reset and the new duty and/or period values to be latched. in addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments note when forcing a new period or duty into effect immediately, an irregular pwm cycle can occur. depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. 18.4.2.4 pwm timer counters each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see section 18.4.1, ?wm clock select for the available clock sources and rates). the counter compares to two registers, a duty register and a period register as shown in figure 18-19 . when the pwm counter matches the duty register, the output ?p-?p changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register behaves differently depending on what output mode is selected as shown in figure 18-19 and described in section 18.4.2.5, ?eft aligned outputs and section 18.4.2.6, ?enter aligned outputs . 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 678 freescale semiconductor each channel counter can be read at anytime without affecting the count or the operation of the pwm channel. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. when the channel is disabled (pwmex = 0), the counter stops. when a channel becomes enabled (pwmex = 1), the associated pwm counter continues from the count in the pwmcntx register. this allows the waveform to continue where it left off when the channel is re-enabled. when the channel is disabled, writing ? to the period register will cause the counter to reset on the next selected clock. note if the user wants to start a new ?lean?pwm waveform without any ?istory?from the old waveform, the user must write to channel counter (pwmcntx) prior to enabling the pwm channel (pwmex = 1). generally, writes to the counter are done prior to enabling a channel in order to start from a known state. however, writing a counter can also be done while the pwm channel is enabled (counting). the effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. the counter is cleared at the end of the effective period (see section 18.4.2.5, ?eft aligned outputs and section 18.4.2.6, ?enter aligned outputs for more details). 18.4.2.5 left aligned outputs the pwm timer provides the choice of two types of outputs, left aligned or center aligned. they are selected with the caex bits in the pwmcae register. if the caex bit is cleared (caex = 0), the corresponding pwm output will be left aligned. in left aligned output mode, the 8-bit counter is con?ured as an up counter only. it compares to two registers, a duty register and a period register as shown in the block diagram in figure 18-19 . when the pwm counter matches the duty register the output ?p-?p changes state causing the pwm waveform to also change state. a match between the pwm counter and the period register resets the counter and the output ?p-?p, as shown in figure 18-19 , as well as performing a load from the double buffer period and duty register to the associated registers, as described in section 18.4.2.3, ?wm period and duty . the counter counts from 0 to the value in the period register ?1. table 18-10. pwm timer counter conditions counter clears ($00) counter counts counter stops when pwmcntx register written to any value when pwm channel is enabled (pwmex = 1). counts from last value in pwmcntx. when pwm channel is disabled (pwmex = 0) effective period ends 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 679 note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 18-20. pwm left aligned output waveform to calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by the value in the period register for that channel. pwmx frequency = clock (a, b, sa, or sb) / pwmperx pwmx duty cycle (high time as a% of period): polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a left aligned output, consider the following case: clock source = e, where e = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/4 = 2.5 mhz pwmx period = 400 ns pwmx duty cycle = 3/4 *100% = 75% the output waveform generated is shown in figure 18-21 . pwmdtyx period = pwmperx ppolx = 0 ppolx = 1 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 680 freescale semiconductor figure 18-21. pwm left aligned output example waveform 18.4.2.6 center aligned outputs for center aligned output mode selection, set the caex bit (caex = 1) in the pwmcae register and the corresponding pwm output will be center aligned. the 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. the counter compares to two registers, a duty register and a period register as shown in the block diagram in figure 18-19 . when the pwm counter matches the duty register, the output ?p-?p changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register changes the counter direction from an up-count to a down-count. when the pwm counter decrements and matches the duty register again, the output ?p-?p changes state causing the pwm output to also change state. when the pwm counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described in section 18.4.2.3, ?wm period and duty . the counter counts from 0 up to the value in the period register and then back down to 0. thus the effective period is pwmperx*2. note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 18-22. pwm center aligned output waveform period = 400 ns e = 100 ns duty cycle = 75% ppolx = 0 ppolx = 1 pwmdtyx pwmdtyx period = pwmperx*2 pwmperx pwmperx 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 681 to calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by twice the value in the period register for that channel. pwmx frequency = clock (a, b, sa, or sb) / (2*pwmperx) pwmx duty cycle (high time as a% of period): polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 682 freescale semiconductor as an example of a center aligned output, consider the following case: clock source = e, where e = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/8 = 1.25 mhz pwmx period = 800 ns pwmx duty cycle = 3/4 *100% = 75% shown in figure 18-23 is the output waveform generated. figure 18-23. pwm center aligned output example waveform 18.4.2.7 pwm 16-bit functions the pwm timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater pwm resolution. this 16-bit channel option is achieved through the concatenation of two 8-bit channels. the pwmctl register contains four control bits, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. channels 6 and 7 are concatenated with the con67 bit, channels 4 and 5 are concatenated with the con45 bit, channels 2 and 3 are concatenated with the con23 bit, and channels 0 and 1 are concatenated with the con01 bit. note change these bits only when both corresponding channels are disabled. when channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in figure 18-24 . similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. when channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. when channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. when using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. that is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. the resulting pwm is output to the pins of the corresponding low order 8-bit channel as also shown in figure 18-24 . the polarity of the resulting pwm output is controlled by the ppolx bit of the corresponding low order 8-bit channel as well. e = 100 ns duty cycle = 75% e = 100 ns period = 800 ns 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 683 figure 18-24. pwm 16-bit mode once concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the low order pwmex bit. in this case, the high order bytes pwmex bits have no effect and their corresponding pwm output is disabled. in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. pwmcnt6 pwcnt7 pwm7 clock source 7 high low period/duty compare pwmcnt4 pwcnt5 pwm5 clock source 5 high low period/duty compare pwmcnt2 pwcnt3 pwm3 clock source 3 high low period/duty compare pwmcnt0 pwcnt1 pwm1 clock source 1 high low period/duty compare 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 684 freescale semiconductor either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order caex bit. the high order caex bit has no effect. table 18-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. 18.4.2.8 pwm boundary cases table 18-12 summarizes the boundary conditions for the pwm regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation). 18.5 resets the reset state of each individual bit is listed within the section 18.3.2, ?egister descriptions which details the registers and their bit-?lds. all special functions or modes which are initialized during or just following reset are described within this section. the 8-bit up/down counter is con?ured as an up counter out of reset. all the channels are disabled and all the counters do not count. table 18-11. 16-bit concatenation mode summary conxx pwmex ppolx pclkx caex pwmx output con67 pwme7 ppol7 pclk7 cae7 pwm7 con45 pwme5 ppol5 pclk5 cae5 pwm5 con23 pwme3 ppol3 pclk3 cae3 pwm3 con01 pwme1 ppol1 pclk1 cae1 pwm1 table 18-12. pwm boundary cases pwmdtyx pwmperx ppolx pwmx output $00 (indicates no duty) >$00 1 always low $00 (indicates no duty) >$00 0 always high xx $00 1 (indicates no period) 1 counter = $00 and does not count. 1 always high xx $00 1 (indicates no period) 0 always low >= pwmperx xx 1 always high >= pwmperx xx 0 always low 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 685 18.6 interrupts the pwm module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (pwmie) is set. this bit is the enable for the interrupt. the interrupt ?g pwmif is set whenever the input level of the pwm7 channel changes while pwm7ena = 1 or when pwmena is being asserted while the level at pwm7 is active. in stop mode or wait mode (with the pswai bit set), the emergency shutdown feature will drive the pwm outputs to their shutdown output levels but the pwmif ?g will not be set. a description of the registers involved and affected due to this interrupt is explained in section 18.3.2.15, ?wm shutdown register (pwmsdn) . the pwm block only generates the interrupt and does not service it. the interrupt signal name is pwm interrupt signal. 4 .com u datasheet
chapter 18 pulse-width modulator (pwm8b8cv1) MC9S12XHZ512 data sheet, rev. 1.02 686 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 687 chapter 19 enhanced capture timer (ect16b8cv3) 19.1 introduction the hcs12 enhanced capture timer module has the features of the hcs12 standard timer module enhanced by additional features in order to enlarge the ?ld of applications, in particular for automotive abs applications. this design speci?ation describes the standard timer as well as the additional features. the basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. a full access for the counter registers or the input capture/output compare registers will take place in one clock cycle. accessing high byte and low byte separately for all of these registers will not yield the same result as accessing them in one word. 19.1.1 features 16-bit buffer register for four input capture (ic) channels. four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered ic channels. con?urable also as two 16-bit pulse accumulators. 16-bit modulus down-counter with 8-bit prescaler. four user-selectable delay counters for input noise immunity increase. 19.1.2 modes of operation stop ?timer and modulus counter are off since clocks are stopped. freeze timer and modulus counter keep on running, unless the tsfrz bit in the tscr1 register is set to one. wait ?counters keep on running, unless the tswai bit in the tscr1 register is set to one. normal timer and modulus counter keep on running, unless the ten bit in the tscr1 register or the mcen bit in the mcctl register are cleared. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 688 freescale semiconductor 19.1.3 block diagram figure 19-1. ect block diagram prescaler 16-bit counter 16-bit pulse accumulator b ioc0 ioc2 ioc1 ioc5 ioc3 ioc4 ioc6 ioc7 pa input interrupt pa overflow interrupt timer overflow interrupt timer channel 0 interrupt timer channel 7 interrupt registers bus clock channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 16-bit pulse accumulator a pb overflow interrupt modulus counter interrupt 16-bit modulus counter input capture output compare input capture input capture input capture input capture input capture input capture input capture output compare output compare output compare output compare output compare output compare output compare 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 689 19.2 external signal description the ect module has a total of eight external pins. 19.2.1 ioc7 ?input capture and output compare channel 7 this pin serves as input capture or output compare for channel 7. 19.2.2 ioc6 ?input capture and output compare channel 6 this pin serves as input capture or output compare for channel 6. 19.2.3 ioc5 ?input capture and output compare channel 5 this pin serves as input capture or output compare for channel 5. 19.2.4 ioc4 ?input capture and output compare channel 4 this pin serves as input capture or output compare for channel 4. 19.2.5 ioc3 ?input capture and output compare channel 3 this pin serves as input capture or output compare for channel 3. 19.2.6 ioc2 ?input capture and output compare channel 2 this pin serves as input capture or output compare for channel 2. 19.2.7 ioc1 ?input capture and output compare channel 1 this pin serves as input capture or output compare for channel 1. 19.2.8 ioc0 ?input capture and output compare channel 0 this pin serves as input capture or output compare for channel 0. note for the description of interrupts see section 19.4.3, ?nterrupts? 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 690 freescale semiconductor 19.3 memory map and register de?ition this section provides a detailed description of all memory and registers. 19.3.1 module memory map the memory map for the ect module is given below in table 19-1 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the ect module and the address offset for each register. table 19-1. ect memory map address offset register access 0x0000 timer input capture/output compare select (tios) r/w 0x0001 timer compare force register (cforc) r/w 1 0x0002 output compare 7 mask register (oc7m) r/w 0x0003 output compare 7 data register (oc7d) r/w 0x0004 timer count register high (tcnt) r/w 2 0x0005 timer count register low (tcnt) r/w 2 0x0006 timer system control register 1 (tscr1) r/w 0x0007 timer toggle over?w register (ttov) r/w 0x0008 timer control register 1 (tctl1) r/w 0x0009 timer control register 2 (tctl2) r/w 0x000a timer control register 3 (tctl3) r/w 0x000b timer control register 4 (tctl4) r/w 0x000c timer interrupt enable register (tie) r/w 0x000d timer system control register 2 (tscr2) r/w 0x000e main timer interrupt flag 1 (tflg1) r/w 0x000f main timer interrupt flag 2 (tflg2) r/w 0x0010 timer input capture/output compare register 0 high (tc0) r/w 3 0x0011 timer input capture/output compare register 0 low (tc0) r/w 3 0x0012 timer input capture/output compare register 1 high (tc1) r/w 3 0x0013 timer input capture/output compare register 1 low (tc1) r/w 3 0x0014 timer input capture/output compare register 2 high (tc2) r/w 3 0x0015 timer input capture/output compare register 2 low (tc2) r/w 3 0x0016 timer input capture/output compare register 3 high (tc3) r/w 3 0x0017 timer input capture/output compare register 3 low (tc3) r/w 3 0x0018 timer input capture/output compare register 4 high (tc4) r/w 3 0x0019 timer input capture/output compare register 4 low (tc4) r/w 3 0x001a timer input capture/output compare register 5 high (tc5) r/w 3 0x001b timer input capture/output compare register 5 low (tc5) r/w 3 0x001c timer input capture/output compare register 6 high (tc6) r/w 3 0x001d timer input capture/output compare register 6 low (tc6) r/w 3 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 691 0x001e timer input capture/output compare register 7 high (tc7) r/w 3 0x001f timer input capture/output compare register 7 low (tc7) r/w 3 0x0020 16-bit pulse accumulator a control register (pactl) r/w 0x0021 pulse accumulator a flag register (paflg) r/w 0x0022 pulse accumulator count register 3 (pacn3) r/w 0x0023 pulse accumulator count register 2 (pacn2) r/w 0x0024 pulse accumulator count register 1 (pacn1) r/w 0x0025 pulse accumulator count register 0 (pacn0) r/w 0x0026 16-bit modulus down counter register (mcctl) r/w 0x0027 16-bit modulus down counter flag register (mcflg) r/w 0x0028 input control pulse accumulator register (icpar) r/w 0x0029 delay counter control register (dlyct) r/w 0x002a input control overwrite register (icovw) r/w 0x002b input control system control register (icsys) r/w 4 0x002c output compare pin disconnect register(ocpd) r/w 0x002d timer test register (timtst) r/w 2 0x002e precision timer prescaler select register (ptpsr) r/w 0x002f precision timer modulus counter prescaler select register (ptmcpsr) r/w 0x0030 16-bit pulse accumulator b control register (pbctl) r/w 0x0031 16-bit pulse accumulator b flag register (pbflg) r/w 0x0032 8-bit pulse accumulator holding register 3 (pa3h) r/w 5 0x0033 8-bit pulse accumulator holding register 2 (pa2h) r/w 5 0x0034 8-bit pulse accumulator holding register 1 (pa1h) r/w 5 0x0035 8-bit pulse accumulator holding register 0 (pa0h) r/w 5 0x0036 modulus down-counter count register high (mccnt) r/w 0x0037 modulus down-counter count register low (mccnt) r/w 0x0038 timer input capture holding register 0 high (tc0h) r/w 5 0x0039 timer input capture holding register 0 low (tc0h) r/w 5 0x003a timer input capture holding register 1 high(tc1h) r/w 5 0x003b timer input capture holding register 1 low (tc1h) r/w 5 0x003c timer input capture holding register 2 high (tc2h) r/w 5 0x003d timer input capture holding register 2 low (tc2h) r/w 5 0x003e timer input capture holding register 3 high (tc3h) r/w 5 0x003f timer input capture holding register 3 low (tc3h) r/w 5 1 always read 0x0000. 2 only writable in special modes (test_mode = 1). 3 writes to these registers have no meaning or effect during input capture. 4 may be written once when not in test00mode but writes are always permitted when test00mode is enabled. 5 writes have no effect. table 19-1. ect memory map (continued) address offset register access 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 692 freescale semiconductor 19.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 654321 bit 0 0x0000 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x0001 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0002 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x0003 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0004 tcnt (high) r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w 0x0005 tcnt (low) r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w 0x0006 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x0007 ttof r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0008 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0009 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x000a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x000b tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x000c tie r c7i c6i c5i c4i c3i c2i c1i c0i w = unimplemented or reserved figure 19-2. ect register summary (sheet 1 of 5) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 693 0x000d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x000e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x000f tflg2 r tof 0000000 w 0x0010 tc0 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0011 tc0 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0012 tc1 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0013 tc1 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0014 tc2 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0015 tc2 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0016 tc3 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0017 tc3 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0018 tc4 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0019 tc4 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x001a tc5 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x001b tc5 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w register name bit 7 654321 bit 0 = unimplemented or reserved figure 19-2. ect register summary (sheet 2 of 5) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 694 freescale semiconductor 0x001c tc6 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x001d tc6 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x001e tc7 (high) r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x001f tc7 (low) r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0020 pactl r0 paen pamod pedge clk1 clk0 pa0vi pai w 0x0021 paflg r000000 pa0vf paif w 0x0022 pacn3 r pacnt7(15) pacnt6(14) pacnt5(13) pacnt4(12) pacnt3(11) pacnt2(10) pacnt1(9) pacnt0(8) w 0x0023 pacn2 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0024 pacn1 r pacnt7(15) pacnt6(14) pacnt5(13) pacnt4(12) pacnt3(11) pacnt2(10) pacnt1(9) pacnt0(8) w 0x0025 pacn0 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0026 mcctl r mczi modmc rdmcl 00 mcen mcpr1 mcpr0 w iclat flmc 0x0027 mcflg r mczf 0 0 0 polf3 polf2 polf1 polf0 w 0x0028 icpar r0000 pa3en pa2en pa1en pa0en w 0x0029 dlyct r dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 w 0x002a icovw r novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 w register name bit 7 654321 bit 0 = unimplemented or reserved figure 19-2. ect register summary (sheet 3 of 5) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 695 0x002b icsys r sh37 sh26 sh15 sh04 tfmod pacmx bufen latq w 0x002c ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x002d timtst r timer test register w 0x002e ptpsr r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w 0x002f ptmcpsr r ptmps7 ptmps6 ptmps5 ptmps4 ptmps3 ptmps2 ptmps1 ptmps0 w 0x0030 pbctl r0 pben 0000 pbovi 0 w 0x0031 pbflg r000000 pbovf 0 w 0x0032 pa3h r pa3h7 pa3h6 pa3h5 pa3h4 pa3h3 pa3h2 pa3h1 pa3h0 w 0x0033 pa2h r pa2h7 pa2h6 pa2h5 pa2h4 pa2h3 pa2h2 pa2h1 pa2h0 w 0x0034 pa1h r pa1h7 pa1h6 pa1h5 pa1h4 pa1h3 pa1h2 pa1h1 pa1h0 w 0x0035 pa0h r pa0h7 pa0h6 pa0h5 pa0h4 pa0h3 pa0h2 pa0h1 pa0h0 w 0x0036 mccnt (high) r mccnt15 mccnt14 mccnt13 mccnt12 mccnt11 mccnt10 mccnt9 mccnt8 w 0x0037 mccnt (low) r mccnt7 mccnt6 mccnt5 mccnt4 mccnt3 mccnt2 mccnt1 mccnt9 w 0x0038 tc0h (high) r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w 0x0039 tc0h (low) r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 register name bit 7 654321 bit 0 = unimplemented or reserved figure 19-2. ect register summary (sheet 4 of 5) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 696 freescale semiconductor 19.3.2.1 timer input capture/output compare select register (tios) read or write: anytime all bits reset to zero. 0x003a tc1h (high) r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w 0x003b tc1h (low) r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w 0x003c tc2h (high) r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w 0x003d tc2h (low) r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w 0x003e tc3h (high) r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w 0x003f tc3h (low) r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w module base + 0x0000 76543210 r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w reset 0 0 0 00000 figure 19-3. timer input capture/output compare register (tios) table 19-2. tios field descriptions field description 7:0 ios[7:0] input capture or output compare channel con?uration 0 the corresponding channel acts as an input capture. 1 the corresponding channel acts as an output compare. register name bit 7 654321 bit 0 = unimplemented or reserved figure 19-2. ect register summary (sheet 5 of 5) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 697 19.3.2.2 timer compare force register (cforc) read or write: anytime but reads will always return 0x0000 (1 state is transient). all bits reset to zero. 19.3.2.3 output compare 7 mask register (oc7m) read or write: anytime all bits reset to zero. module base + 0x0001 76543210 r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 reset 0 0 0 00000 figure 19-4. timer compare force register (cforc) table 19-3. cforc field descriptions field description 7:0 foc[7:0] force output compare action for channel 7:0 a write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare ??to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcx register except the interrupt ?g does not get set. note: a successful channel 7 output compare overrides any channel 6:0 compares. if a forced output compare on any channel occurs at the same time as the successful output compare, then the forced output compare action will take precedence and the interrupt ?g will not get set. module base + 0x0002 76543210 r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w reset 0 0 0 00000 figure 19-5. output compare 7 mask register (oc7m) table 19-4. oc7m field descriptions field description 7:0 oc7m[7:0] output compare mask action for channel 7:0 0 the corresponding oc7dx bit in the output compare 7 data register will not be transferred to the timer port on a successful channel 7 output compare, even if the corresponding pin is setup for output compare. 1 the corresponding oc7dx bit in the output compare 7 data register will be transferred to the timer port on a successful channel 7 output compare. note: the corresponding channel must also be setup for output compare (iosx = 1) for data to be transferred from the output compare 7 data register to the timer port. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 698 freescale semiconductor 19.3.2.4 output compare 7 data register (oc7d) read or write: anytime all bits reset to zero. module base + 0x0003 76543210 r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w reset 0 0 0 00000 figure 19-6. output compare 7 data register (oc7d) table 19-5. oc7d field descriptions field description 7:0 oc7d[7:0] output compare 7 data bits ?a channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 699 19.3.2.5 timer count register (tcnt) read: anytime write: has no meaning or effect all bits reset to zero. module base + 0x0004 15 14 13 12 11 10 9 8 r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w reset 0 0 0 00000 figure 19-7. timer count register high (tcnt) module base + 0x0005 76543210 r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w reset 0 0 0 00000 figure 19-8. timer count register low (tcnt) table 19-6. tcnt field descriptions field description 15:0 tcnt[15:0] timer counter bits the 16-bit main timer is an up counter. a read to this register will return the current value of the counter. access to the counter register will take place in one clock cycle. note: a separate read/write for high byte and low byte in test mode will give a different result than accessing them as a word. the period of the ?st count after a write to the tcnt registers may be a different size because the write is not synchronized with the prescaler clock. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 700 freescale semiconductor 19.3.2.6 timer system control register 1 (tscr1) read or write: anytime except prnt bit is write once all bits reset to zero. module base + 0x0006 76543210 r ten tswai tsfrz tffca prnt 000 w reset 0 0 0 00000 = unimplemented or reserved figure 19-9. timer system control register 1 (tscr1) table 19-7. tscr1 field descriptions field description 7 ten timer enable 0 disables the main timer, including the counter. can be used for reducing power consumption. 1 allows the timer to function normally. note: if for any reason the timer is not active, there is no 64 clock for the pulse accumulator since the 64 is generated by the timer prescaler. 6 tswai timer module stops while in wait 0 allows the timer module to continue running during wait. 1 disables the timer counter, pulse accumulators and modulus down counter when the mcu is in wait mode. timer interrupts cannot be used to get the mcu out of wait. 5 tsfrz timer and modulus counter stop while in freeze mode 0 allows the timer and modulus counter to continue running while in freeze mode. 1 disables the timer and modulus counter whenever the mcu is in freeze mode. this is useful for emulation. the pulse accumulators do not stop in freeze mode. 4 tffca timer fast flag clear all 0 allows the timer ?g clearing to function normally. 1 a read from an input capture or a write to the output compare channel registers causes the corresponding channel ?g, cxf, to be cleared in the tflg1 register. any access to the tcnt register clears the tof ?g in the tflg2 register. any access to the pacn3 and pacn2 registers clears the paovf and paif ?gs in the paflg register. any access to the pacn1 and pacn0 registers clears the pbovf ?g in the pbflg register. any access to the mccnt register clears the mczf ?g in the mcflg register. this has the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental ?g clearing due to unintended accesses. note: the ?gs cannot be cleared via the normal ?g clearing mechanism (writing a one to the ?g) when tffca = 1. 3 prnt precision timer 0 enables legacy timer. only bits dly0 and dly1 of the dlyct register are used for the delay selection of the delay counter. pr0, pr1, and pr2 bits of the tscr2 register are used for timer counter prescaler selection. mcpr0 and mcpr1 bits of the mcctl register are used for modulus down counter prescaler selection. 1 enables precision timer. all bits in the dlyct register are used for the delay selection, all bits of the ptpsr register are used for precision timer prescaler selection, and all bits of ptmcpsr register are used for the prescaler precision timer modulus counter prescaler selection. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 701 19.3.2.7 timer toggle on over?w register 1 (ttov) read or write: anytime all bits reset to zero. module base + 0x0007 76543210 r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w reset 0 0 0 00000 figure 19-10. timer toggle on over?w register 1 (ttov) table 19-8. ttov field descriptions field description 7:0 tov[7:0] toggle on over?w bits tov97:0] toggles output compare pin on timer counter over?w. this feature only takes effect when in output compare mode. when set, it takes precedence over forced output compare but not channel 7 override events. 0 toggle output compare pin on over?w feature disabled. 1 toggle output compare pin on over?w feature enabled. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 702 freescale semiconductor 19.3.2.8 timer control register 1/timer control register 2 (tctl1/tctl2) read or write: anytime all bits reset to zero. note to enable output action by omx and olx bits on timer port, the corresponding bit in oc7m should be cleared. module base + 0x0008 76543210 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w reset 0 0 0 00000 figure 19-11. timer control register 1 (tctl1) module base + 0x0009 76543210 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w reset 0 0 0 00000 figure 19-12. timer control register 2 (tctl2) table 19-9. tctl1/tctl2 field descriptions field description om[7:0] 7, 5, 3, 1 omx ?output mode olx ?output level these eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or olx is one, the pin associated with ocx becomes an output tied to ocx. see table 19-10 . ol[7:0] 6, 4, 2, 0 table 19-10. compare result output action omx olx action 0 0 no output compare action on the timer output signal 0 1 toggle ocx output line 1 0 clear ocx output line to zero 1 1 set ocx output line to one 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 703 19.3.2.9 timer control register 3/timer control register 4 (tctl3/tctl4) read or write: anytime all bits reset to zero. module base + 0x000a 76543210 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w reset 0 0 0 00000 figure 19-13. timer control register 3 (tctl3) module base + 0x000b 76543210 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w reset 0 0 0 00000 figure 19-14. timer control register 4 (tctl4) table 19-11. tctl3/tctl4 field descriptions field description edg[7:0]b 7, 5, 3, 1 input capture edge control ?these eight pairs of control bits con?ure the input capture edge detector circuits for each input capture channel. the four pairs of control bits in tctl4 also con?ure the input capture edge control for the four 8-bit pulse accumulators pac0?ac3.edg0b and edg0a in tctl4 also determine the active edge for the 16-bit pulse accumulator pacb. see table 19-12 . edg[7:0]a 6, 4, 2, 0 table 19-12. edge detector circuit con?uration edgxb edgxa con?uration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 704 freescale semiconductor 19.3.2.10 timer interrupt enable register (tie) read or write: anytime all bits reset to zero. the bits c7i?0i correspond bit-for-bit with the ?gs in the tflg1 status register. module base + 0x000c 76543210 r c7i c6i c5i c4i c3i c2i c1i c0i w reset 0 0 0 00000 figure 19-15. timer interrupt enable register (tie) table 19-13. tie field descriptions field description 7:0 c[7:0]i input capture/output compare ??interrupt enable 0 the corresponding ?g is disabled from causing a hardware interrupt. 1 the corresponding ?g is enabled to cause an interrupt. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 705 19.3.2.11 timer system control register 2 (tscr2) read or write: anytime all bits reset to zero. module base + 0x000d 76543210 r toi 000 tcre pr2 pr1 pr0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-16. timer system control register 2 (tscr2) table 19-14. tscr2 field descriptions field description 7 toi timer over?w interrupt enable 0 timer over?w interrupt disabled. 1 hardware interrupt requested when tof ?g set. 3 tcre timer counter reset enable this bit allows the timer counter to be reset by a successful channel 7 output compare. this mode of operation is similar to an up-counting modulus counter. 0 counter reset disabled and counter free runs. 1 counter reset by a successful output compare on channel 7. note: if register tc7 = 0x0000 and tcre = 1, then the tcnt register will stay at 0x0000 continuously. if register tc7 = 0xffff and tcre = 1, the tof ?g will never be set when tcnt is reset from 0xffff to 0x0000. 2:0 pr[2:0] timer prescaler select these three bits specify the division rate of the main timer prescaler when the prnt bit of register tscr1 is set to 0. the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. see table 19-15 . table 19-15. prescaler selection pr2 pr1 pr0 prescale factor 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 706 freescale semiconductor 19.3.2.12 main timer interrupt flag 1 (tflg1) read: anytime write used in the ?g clearing mechanism. writing a one to the ?g clears the ?g. writing a zero will not affect the current status of the bit. note when tffca = 1, the ?gs cannot be cleared via the normal ?g clearing mechanism (writing a one to the ?g). reference section 19.3.2.6, ?imer system control register 1 (tscr1) . all bits reset to zero. tflg1 indicates when interrupt conditions have occurred. the ?gs can be cleared via the normal ?g clearing mechanism (writing a one to the ?g) or via the fast ?g clearing mechanism (reference tffca bit in section 19.3.2.6, ?imer system control register 1 (tscr1) ). use of the tfmod bit in the icsys register in conjunction with the use of the icovw register allows a timer interrupt to be generated after capturing two values in the capture and holding registers, instead of generating an interrupt for every capture. module base + 0x000e 76543210 r c7f c6f c5f c4f c3f c2f c1f c0f w reset 0 0 0 00000 figure 19-17. main timer interrupt flag 1 (tflg1) table 19-16. tflg1 field descriptions field description 7:0 c[7:0]f input capture/output compare channel ? flag a cxf ?g is set when a corresponding input capture or output compare is detected. c0f can also be set by 16-bit pulse accumulator b (pacb). c3f?0f can also be set by 8-bit pulse accumulators pac3?ac0. if the delay counter is enabled, the cxf ?g will not be set until after the delay. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 707 19.3.2.13 main timer interrupt flag 2 (tflg2) read: anytime write used in the ?g clearing mechanism. writing a one to the ?g clears the ?g. writing a zero will not affect the current status of the bit. note when tffca = 1, the ?g cannot be cleared via the normal ?g clearing mechanism (writing a one to the ?g). reference section 19.3.2.6, ?imer system control register 1 (tscr1) . all bits reset to zero. tflg2 indicates when interrupt conditions have occurred. the ?g can be cleared via the normal ?g clearing mechanism (writing a one to the ?g) or via the fast ?g clearing mechanism (reference tffca bit in section 19.3.2.6, ?imer system control register 1 (tscr1) ). module base + 0x000f 76543210 r tof 0000000 w reset 0 0 0 00000 = unimplemented or reserved figure 19-18. main timer interrupt flag 2 (tflg2) table 19-17. tflg2 field descriptions field description 7 tof timer over?w flag ?set when 16-bit free-running timer over?ws from 0xffff to 0x0000. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 708 freescale semiconductor 19.3.2.14 timer input capture/output compare registers 0? module base + 0x0010 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-19. timer input capture/output compare register 0 high (tc0) module base + 0x0011 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-20. timer input capture/output compare register 0 low (tc0) module base + 0x0012 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-21. timer input capture/output compare register 1 high (tc1) module base + 0x0013 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-22. timer input capture/output compare register 1 low (tc1) module base + 0x0014 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-23. timer input capture/output compare register 2 high (tc2) module base + 0x0015 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-24. timer input capture/output compare register 2 low (tc2) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 709 module base + 0x0016 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-25. timer input capture/output compare register 3 high (tc3) module base + 0x0017 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-26. timer input capture/output compare register 3 low (tc3) module base + 0x0018 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-27. timer input capture/output compare register 4 high (tc4) module base + 0x0019 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-28. timer input capture/output compare register 4 low (tc4) module base + 0x001a 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-29. timer input capture/output compare register 5 high (tc5) module base + 0x001b 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-30. timer input capture/output compare register 5 low (tc5) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 710 freescale semiconductor read: anytime write anytime for output compare function. writes to these registers have no meaning or effect during input capture. all bits reset to zero. depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a de?ed transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. module base + 0x001c 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-31. timer input capture/output compare register 6 high (tc6) module base + 0x001d 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-32. timer input capture/output compare register 6 low (tc6) module base + 0x001e 15 14 13 12 11 10 9 8 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 19-33. timer input capture/output compare register 7 high (tc7) module base + 0x001f 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 19-34. timer input capture/output compare register 7 low (tc7) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 711 19.3.2.15 16-bit pulse accumulator a control register (pactl) read: anytime write: anytime all bits reset to zero. module base + 0x0020 76543210 r0 paen pamod pedge clk1 clk0 paovi pai w reset 0 0 0 00000 = unimplemented or reserved figure 19-35. 16-bit pulse accumulator control register (pactl) table 19-18. pactl field descriptions field description 6 paen pulse accumulator a system enable ?paen is independent from ten. with timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit pulse accumulator a system disabled. 8-bit pac3 and pac2 can be enabled when their related enable bits in icpar are set. pulse accumulator input edge flag (paif) function is disabled. 1 16-bit pulse accumulator a system enabled. the two 8-bit pulse accumulators pac3 and pac2 are cascaded to form the paca 16-bit pulse accumulator. when paca in enabled, the pacn3 and pacn2 registers contents are respectively the high and low byte of the paca. pa3en and pa2en control bits in icpar have no effect. pulse accumulator input edge flag (paif) function is enabled. the paca shares the input pin with ic7. 5 pamod pulse accumulator mode ?this bit is active only when the pulse accumulator a is enabled (paen = 1). 0 event counter mode 1 gated time accumulation mode 4 pedge pulse accumulator edge control ?this bit is active only when the pulse accumulator a is enabled (paen = 1). refer to table 19-19 . for pamod bit = 0 (event counter mode). 0 falling edges on pt7 pin cause the count to be incremented 1 rising edges on pt7 pin cause the count to be incremented for pamod bit = 1 (gated time accumulation mode). 0 pt7 input pin high enables bus clock divided by 64 to pulse accumulator and the trailing falling edge on pt7 sets the paif ?g. 1 pt7 input pin low enables bus clock divided by 64 to pulse accumulator and the trailing rising edge on pt7 sets the paif ?g. if the timer is not active (ten = 0 in tscr1), there is no divide-by-64 since the 64 clock is generated by the timer prescaler. 3:2 clk[1:0] clock select bits ?for the description of paclk please refer to figure 19-71 . if the pulse accumulator is disabled (paen = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. the change from one selected clock to the other happens immediately after these bits are written. refer to table 19-20 . 2 paov i pulse accumulator a over?w interrupt enable 0 interrupt inhibited 1 interrupt requested if paovf is set 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 712 freescale semiconductor . 19.3.2.16 pulse accumulator a flag register (paflg) read: anytime write used in the ?g clearing mechanism. writing a one to the ?g clears the ?g. writing a zero will not affect the current status of the bit. note when tffca = 1, the ?gs cannot be cleared via the normal ?g clearing mechanism (writing a one to the ?g). reference section 19.3.2.6, ?imer system control register 1 (tscr1) . all bits reset to zero. 0 pa i pulse accumulator input interrupt enable 0 interrupt inhibited 1 interrupt requested if paif is set table 19-19. pin action pamod pedge pin action 0 0 falling edge 0 1 rising edge 1 0 divide by 64 clock enabled with pin high level 1 1 divide by 64 clock enabled with pin low level table 19-20. clock selection clk1 clk0 clock source 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65536 as timer counter clock frequency module base + 0x0021 76543210 r000000 paovf paif w reset 0 0 0 00000 = unimplemented or reserved figure 19-36. pulse accumulator a flag register (paflg) table 19-18. pactl field descriptions (continued) field description 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 713 paflg indicates when interrupt conditions have occurred. the ?gs can be cleared via the normal ?g clearing mechanism (writing a one to the ?g) or via the fast ?g clearing mechanism (reference tffca bit in section 19.3.2.6, ?imer system control register 1 (tscr1) ). 19.3.2.17 pulse accumulators count registers (pacn3 and pacn2) read: anytime write: anytime all bits reset to zero. the two 8-bit pulse accumulators pac3 and pac2 are cascaded to form the paca 16-bit pulse accumulator. when paca in enabled (paen = 1 in pactl), the pacn3 and pacn2 registers contents are respectively the high and low byte of the paca. when pacn3 over?ws from 0x00ff to 0x0000, the interrupt ?g paovf in paflg is set. full count register access will take place in one clock cycle. note a separate read/write for high byte and low byte will give a different result than accessing them as a word. table 19-21. paflg field descriptions field description 1 paov f pulse accumulator a over?w flag ?set when the 16-bit pulse accumulator a over?ws from 0xffff to 0x0000, or when 8-bit pulse accumulator 3 (pac3) over?ws from 0x00ff to 0x0000. when pacmx = 1, paovf bit can also be set if 8-bit pulse accumulator 3 (pac3) reaches 0x00ff followed by an active edge on pt3. 0 paif pulse accumulator input edge flag set when the selected edge is detected at the pt7 input pin. in event mode the event edge triggers paif and in gated time accumulation mode the trailing edge of the gate signal at the pt7 input pin triggers paif. module base + 0x0022 76543210 r pacnt7(15) pacnt6(14) pacnt5(13) pacnt4(12) pacnt3(11) pacnt2(10) pacnt1(9) pacnt0(8) w reset 0 0 0 00000 figure 19-37. pulse accumulators count register 3 (pacn3) module base + 0x0023 76543210 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w reset 0 0 0 00000 figure 19-38. pulse accumulators count register 2 (pacn2) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 714 freescale semiconductor when clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. 19.3.2.18 pulse accumulators count registers (pacn1 and pacn0) read: anytime write: anytime all bits reset to zero. the two 8-bit pulse accumulators pac1 and pac0 are cascaded to form the pacb 16-bit pulse accumulator. when pacb in enabled, (pben = 1 in pbctl) the pacn1 and pacn0 registers contents are respectively the high and low byte of the pacb. when pacn1 over?ws from 0x00ff to 0x0000, the interrupt ?g pbovf in pbflg is set. full count register access will take place in one clock cycle. note a separate read/write for high byte and low byte will give a different result than accessing them as a word. when clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. module base + 0x0024 76543210 r pacnt7(15) pacnt6(14) pacnt5(13) pacnt4(12) pacnt3(11) pacnt2(10) pacnt1(9) pacnt0(8) w reset 0 0 0 00000 figure 19-39. pulse accumulators count register 1 (pacn1) module base + 0x0025 76543210 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w reset 0 0 0 00000 figure 19-40. pulse accumulators count register 0 (pacn0) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 715 19.3.2.19 16-bit modulus down-counter control register (mcctl) read: anytime write: anytime all bits reset to zero. module base + 0x0026 76543210 r mczi modmc rdmcl 00 mcen mcpr1 mcpr0 w iclat flmc reset 0 0 0 00000 figure 19-41. 16-bit modulus down-counter control register (mcctl) table 19-22. mcctl field descriptions field description 7 mczi modulus counter under?w interrupt enable 0 modulus counter interrupt is disabled. 1 modulus counter interrupt is enabled. 6 modmc modulus mode enable 0 the modulus counter counts down from the value written to it and will stop at 0x0000. 1 modulus mode is enabled. when the modulus counter reaches 0x0000, the counter is loaded with the latest value written to the modulus count register. note: for proper operation, the mcen bit should be cleared before modifying the modmc bit in order to reset the modulus counter to 0xffff. 5 rdmcl read modulus down-counter load 0 reads of the modulus count register (mccnt) will return the present value of the count register. 1 reads of the modulus count register (mccnt) will return the contents of the load register. 4 iclat input capture force latch action ?when input capture latch mode is enabled (latq and bufen bit in icsys are set), a write one to this bit immediately forces the contents of the input capture registers tc0 to tc3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. the pulse accumulators will be automatically cleared when the latch action occurs. writing zero to this bit has no effect. read of this bit will always return zero. 3 flmc force load register into the modulus counter count register ?this bit is active only when the modulus down-counter is enabled (mcen = 1). a write one into this bit loads the load register into the modulus counter count register (mccnt). this also resets the modulus counter prescaler. write zero to this bit has no effect. read of this bit will return always zero. 2 mcen modulus down-counter enable 0 modulus counter disabled. the modulus counter (mccnt) is preset to 0xffff. this will prevent an early interrupt ?g when the modulus down-counter is enabled. 1 modulus counter is enabled. 1:0 mcpr[1:0] modulus counter prescaler select these two bits specify the division rate of the modulus counter prescaler when prnt of tscr1 is set to 0. the newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 716 freescale semiconductor 19.3.2.20 16-bit modulus down-counter flag register (mcflg) read: anytime write only used in the ?g clearing mechanism for bit 7. writing a one to bit 7 clears the ?g. writing a zero will not affect the current status of the bit. note when tffca = 1, the ?g cannot be cleared via the normal ?g clearing mechanism (writing a one to the ?g). reference section 19.3.2.6, ?imer system control register 1 (tscr1) . all bits reset to zero. table 19-23. modulus counter prescaler select mcpr1 mcpr0 prescaler division 00 1 01 4 10 8 11 16 module base + 0x0027 76543210 r mczf 0 0 0 polf3 polf2 polf1 polf0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-42. 16-bit modulus down-counter flag register (mcflg) table 19-24. mcflg field descriptions field description 7 mczf modulus counter under?w flag ?the ?g is set when the modulus down-counter reaches 0x0000. the ?g indicates when interrupt conditions have occurred. the ?g can be cleared via the normal ?g clearing mechanism (writing a one to the ?g) or via the fast ?g clearing mechanism (reference tffca bit in section 19.3.2.6, ?imer system control register 1 (tscr1) ). 3:0 polf[3:0] first input capture polarity status ?these are read only bits. writes to these bits have no effect. each status bit gives the polarity of the ?st edge which has caused an input capture to occur after capture latch has been read. each polfx corresponds to a timer portx input. 0 the ?st input capture has been caused by a falling edge. 1 the ?st input capture has been caused by a rising edge. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 717 19.3.2.21 icpar ?input control pulse accumulators register (icpar) read: anytime write: anytime. all bits reset to zero. the 8-bit pulse accumulators pac3 and pac2 can be enabled only if paen in pactl is cleared. if paen is set, pa3en and pa2en have no effect. the 8-bit pulse accumulators pac1 and pac0 can be enabled only if pben in pbctl is cleared. if pben is set, pa1en and pa0en have no effect. module base + 0x0028 76543210 r0000 pa3en pa2en pa1en pa0en w reset 0 0 0 00000 = unimplemented or reserved figure 19-43. input control pulse accumulators register (icpar) table 19-25. icpar field descriptions field description 3:0 pa[3:0]en 8-bit pulse accumulator ??enable 0 8-bit pulse accumulator is disabled. 1 8-bit pulse accumulator is enabled. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 718 freescale semiconductor 19.3.2.22 delay counter control register (dlyct) read: anytime write: anytime all bits reset to zero. module base + 0x0029 76543210 r dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 w reset 0 0 0 00000 figure 19-44. delay counter control register (dlyct) table 19-26. dlyct field descriptions field description 7:0 dly[7:0] delay counter select ?when the prnt bit of tscr1 register is set to 0, only bits dly0, dly1 are used to calculate the delay. table 19-27 shows the delay settings in this case. when the prnt bit of tscr1 register is set to 1, all bits are used to set a more precise delay. table 19-28 shows the delay settings in this case. after detection of a valid edge on an input capture pin, the delay counter counts the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level of input signal, after the preset delay, is the opposite of the level before the transition.this will avoid reaction to narrow input pulses. delay between two active edges of the input signal period should be longer than the selected counter delay. note: it is recommended to not write to this register while the timer is enabled, that is when ten is set in register tscr1. table 19-27. delay counter select when prnt = 0 dly1 dly0 delay 0 0 disabled 0 1 256 bus clock cycles 1 0 512 bus clock cycles 1 1 1024 bus clock cycles table 19-28. delay counter select examples when prnt = 1 dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 delay 00000000 disabled (bypassed) 00000001 8 bus clock cycles 0000001012 bus clock cycles 0000001116 bus clock cycles 0000010020 bus clock cycles 0000010124 bus clock cycles 0000011028 bus clock cycles 0000011132 bus clock cycles 0000111164 bus clock cycles 00011111 128 bus clock cycles 00111111 256 bus clock cycles 01111111 512 bus clock cycles 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 719 19.3.2.23 input control overwrite register (icovw) read: anytime write: anytime all bits reset to zero. 11111111 1024 bus clock cycles module base + 0x002a 76543210 r novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 w reset 0 0 0 00000 figure 19-45. input control overwrite register (icovw) table 19-29. icovw field descriptions field description 7:0 novw[7:0] no input capture overwrite 0 the contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 the related capture register or holding register cannot be written by an event unless they are empty (see section 19.4.1.1, ?c channels ). this will prevent the captured value being overwritten until it is read or latched in the holding register. table 19-28. delay counter select examples when prnt = 1 dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 delay 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 720 freescale semiconductor 19.3.2.24 input control system control register (icsys) read: anytime write: once in normal modes all bits reset to zero. module base + 0x002b 76543210 r sh37 sh26 sh15 sh04 tfmod pacmx bufen latq w reset 0 0 0 00000 figure 19-46. input control system register (icsys) table 19-30. icsys field descriptions field description 7:4 shxy share input action of input capture channels x and y 0 normal operation 1 the channel input ? causes the same action on the channel ?? the port pin ? and the corresponding edge detector is used to be active on the channel ?? 3 tfmod timer flag setting mode use of the tfmod bit in conjunction with the use of the icovw register allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. by setting tfmod in queue mode, when novwx bit is set and the corresponding capture and holding registers are emptied, an input capture event will ?st update the related input capture register with the main timer contents. at the next event, the tcx data is transferred to the tcxh register, the tcx is updated and the cxf interrupt ?g is set. in all other input capture cases the interrupt ?g is set by a valid external event on ptx. 0 the timer ?gs c3f?0f in tflg1 are set when a valid input capture transition on the corresponding port pin occurs. 1 if in queue mode (bufen = 1 and latq = 0), the timer ?gs c3f?0f in tflg1 are set only when a latch on the corresponding holding register occurs. if the queue mode is not engaged, the timer ?gs c3f?0f are set the same way as for tfmod = 0. 2 pacmx 8-bit pulse accumulators maximum count 0 normal operation. when the 8-bit pulse accumulator has reached the value 0x00ff, with the next active edge, it will be incremented to 0x0000. 1 when the 8-bit pulse accumulator has reached the value 0x00ff, it will not be incremented further. the value 0x00ff indicates a count of 255 or more. 1 buffen ic buffer enable 0 input capture and pulse accumulator holding registers are disabled. 1 input capture and pulse accumulator holding registers are enabled. the latching mode is de?ed by latq control bit. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 721 19.3.2.25 output compare pin disconnect register (ocpd) read: anytime write: anytime all bits reset to zero. 0 latq input control latch or queue mode enable the bufen control bit should be set in order to enable the ic and pulse accumulators holding registers. otherwise latq latching modes are disabled. write one into iclat bit in mcctl, when latq and bufen are set will produce latching of input capture and pulse accumulators registers into their holding registers. 0 queue mode of input capture is enabled. the main timer value is memorized in the ic register by a valid input pin transition. with a new occurrence of a capture, the value of the ic register will be transferred to its holding register and the ic register memorizes the new timer value. 1 latch mode is enabled. latching function occurs when modulus down-counter reaches zero or a zero is written into the count register mccnt (see section 19.4.1.1.2, ?uffered ic channels ). with a latching event the contents of ic registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse accumulators are cleared. module base + 0x002c 76543210 r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w reset 0 0 0 00000 figure 19-47. output compare pin disconnect register (ocpd) table 19-31. ocpd field descriptions field description 7:0 ocpd[7:0] output compare pin disconnect bits 0 enables the timer channel io port. output compare actions will occur on the channel pin. these bits do not affect the input capture or pulse accumulator functions. 1 disables the timer channel io port. output compare actions will not affect on the channel pin; the output compare flag will still be set on an output compare event. table 19-30. icsys field descriptions (continued) field description 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 722 freescale semiconductor 19.3.2.26 precision timer prescaler select register (ptpsr) read: anytime write: anytime all bits reset to zero. module base + 0x002e 76543210 r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w reset 0 0 0 00000 figure 19-48. precision timer prescaler select register (ptpsr) table 19-32. ptpsr field descriptions field description 7:0 ptps[7:0] precision timer prescaler select bits these eight bits specify the division rate of the main timer prescaler. these are effective only when the prnt bit of tscr1 is set to 1. table 19-33 shows some selection examples in this case. the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. table 19-33. precision timer prescaler selection examples when prnt = 1 ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 prescale factor 00000000 1 00000001 2 00000010 3 00000011 4 00000100 5 00000101 6 00000110 7 00000111 8 00001111 16 00011111 32 00111111 64 01111111 128 11111111 256 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 723 19.3.2.27 precision timer modulus counter prescaler select register (ptmcpsr) read: anytime write: anytime all bits reset to zero. module base + 0x002f 76543210 r ptmps7 ptmps6 ptmps5 ptmps4 ptmps3 ptmps2 ptmps1 ptmps0 w reset 0 0 0 00000 figure 19-49. precision timer modulus counter prescaler select register (ptmcpsr) table 19-34. ptmcpsr field descriptions field description 7:0 ptmps[7:0] precision timer modulus counter prescaler select bits ?these eight bits specify the division rate of the modulus counter prescaler. these are effective only when the prnt bit of tscr1 is set to 1. table 19-35 shows some possible division rates. the newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. table 19-35. precision timer modulus counter prescaler select examples when prnt = 1 ptmps7 ptmps6 ptmps5 ptmps4 ptmps3 ptmps2 ptmps1 ptmps0 prescaler division rate 000000001 000000012 000000103 000000114 000001005 000001016 000001107 000001118 0000111116 0001111132 0011111164 01111111128 11111111256 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 724 freescale semiconductor 19.3.2.28 16-bit pulse accumulator b control register (pbctl) read: anytime write: anytime all bits reset to zero. module base + 0x0030 76543210 r0 pben 0000 pbovi 0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-50. 16-bit pulse accumulator b control register (pbctl) table 19-36. pbctl field descriptions field description 6 pben pulse accumulator b system enable ?pben is independent from ten. with timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 8-bit pac1 and pac0 can be enabled when their related enable bits in icpar are set. 1 pulse accumulator b system enabled. the two 8-bit pulse accumulators pac1 and pac0 are cascaded to form the pacb 16-bit pulse accumulator b. when pacb is enabled, the pacn1 and pacn0 registers contents are respectively the high and low byte of the pacb. pa1en and pa0en control bits in icpar have no effect. the pacb shares the input pin with ic0. 1 pbovi pulse accumulator b over?w interrupt enable 0 interrupt inhibited 1 interrupt requested if pbovf is set 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 725 19.3.2.29 pulse accumulator b flag register (pbflg) read: anytime write used in the ?g clearing mechanism. writing a one to the ?g clears the ?g. writing a zero will not affect the current status of the bit. note when tffca = 1, the ?g cannot be cleared via the normal ?g clearing mechanism (writing a one to the ?g). reference section 19.3.2.6, ?imer system control register 1 (tscr1) . all bits reset to zero. pbflg indicates when interrupt conditions have occurred. the ?g can be cleared via the normal ?g clearing mechanism (writing a one to the ?g) or via the fast ?g clearing mechanism (reference tffca bit in section 19.3.2.6, ?imer system control register 1 (tscr1) ). module base + 0x0031 76543210 r000000 pbovf 0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-51. pulse accumulator b flag register (pbflg) table 19-37. pbflg field descriptions field description 1 pbovf pulse accumulator b over?w flag ?this bit is set when the 16-bit pulse accumulator b over?ws from 0xffff to 0x0000, or when 8-bit pulse accumulator 1 (pac1) over?ws from 0x00ff to 0x0000. when pacmx = 1, pbovf bit can also be set if 8-bit pulse accumulator 1 (pac1) reaches 0x00ff and an active edge follows on pt1. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 726 freescale semiconductor 19.3.2.30 8-bit pulse accumulators holding registers (pa3h?a0h) read: anytime. write: has no effect. all bits reset to zero. these registers are used to latch the value of the corresponding pulse accumulator when the related bits in register icpar are enabled (see section 19.4.1.3, ?ulse accumulators ). module base + 0x0032 76543210 r pa3h7 pa3h6 pa3h5 pa3h4 pa3h3 pa3h2 pa3h1 pa3h0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-52. 8-bit pulse accumulators holding register 3 (pa3h) module base + 0x0033 76543210 r pa2h7 pa2h6 pa2h5 pa2h4 pa2h3 pa2h2 pa2h1 pa2h0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-53. 8-bit pulse accumulators holding register 2 (pa2h) module base + 0x0034 76543210 r pa1h7 pa1h6 pa1h5 pa1h4 pa1h3 pa1h2 pa1h1 pa1h0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-54. 8-bit pulse accumulators holding register 1 (pa1h) module base + 0x0035 76543210 r pa0h7 pa0h6 pa0h5 pa0h4 pa0h3 pa0h2 pa0h1 pa0h0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-55. 8-bit pulse accumulators holding register 0 (pa0h) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 727 19.3.2.31 modulus down-counter count register (mccnt) read: anytime write: anytime. all bits reset to one. a full access for the counter register will take place in one clock cycle. note a separate read/write for high byte and low byte will give different results than accessing them as a word. if the rdmcl bit in mcctl register is cleared, reads of the mccnt register will return the present value of the count register. if the rdmcl bit is set, reads of the mccnt will return the contents of the load register. if a 0x0000 is written into mccnt when latq and bufen in icsys register are set, the input capture and pulse accumulator registers will be latched. with a 0x0000 write to the mccnt, the modulus counter will stay at zero and does not set the mczf ?g in mcflg register. if the modulus down counter is enabled (mcen = 1) and modulus mode is enabled (modmc = 1), a write to mccnt will update the load register with the value written to it. the count register will not be updated with the new value until the next counter under?w. if modulus mode is not enabled (modmc = 0), a write to mccnt will clear the modulus prescaler and will immediately update the counter register with the value written to it and down-counts to 0x0000 and stops. the flmc bit in mcctl can be used to immediately update the count register with the new value if an immediate load is desired. module base + 0x0036 15 14 13 12 11 10 9 8 r mccnt15 mccnt14 mccnt13 mccnt12 mccnt11 mccnt10 mccnt9 mccnt8 w reset 1 1 1 11111 figure 19-56. modulus down-counter count register high (mccnt) module base + 0x0037 76543210 r mccnt7 mccnt6 mccnt5 mccnt4 mccnt3 mccnt2 mccnt1 mccnt9 w reset 1 1 1 11111 figure 19-57. modulus down-counter count register low (mccnt) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 728 freescale semiconductor 19.3.2.32 timer input capture holding registers 0? (tcxh) module base + 0x0038 15 14 13 12 11 10 9 8 r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w reset 0 0 0 00000 = unimplemented or reserved figure 19-58. timer input capture holding register 0 high (tc0h) module base + 0x0039 76543210 r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-59. timer input capture holding register 0 low (tc0h) module base + 0x003a 15 14 13 12 11 10 9 8 r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w reset 0 0 0 00000 = unimplemented or reserved figure 19-60. timer input capture holding register 1 high (tc1h) module base + 0x003b 76543210 r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-61. timer input capture holding register 1 low (tc1h) module base + 0x003c 15 14 13 12 11 10 9 8 r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w reset 0 0 0 00000 = unimplemented or reserved figure 19-62. timer input capture holding register 2 high (tc2h) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 729 read: anytime write: has no effect. all bits reset to zero. these registers are used to latch the value of the input capture registers tc0?c3. the corresponding iosx bits in tios should be cleared (see section 19.4.1.1, ?c channels ). 19.4 functional description this section provides a complete functional description of the ect block, detailing the operation of the design from the end user perspective in a number of subsections. module base + 0x003d 76543210 r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-63. timer input capture holding register 2 low (tc2h) module base + 0x003e 15 14 13 12 11 10 9 8 r tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 w reset 0 0 0 00000 = unimplemented or reserved figure 19-64. timer input capture holding register 3 high (tc3h) module base + 0x003f 76543210 r tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 w reset 0 0 0 00000 = unimplemented or reserved figure 19-65. timer input capture holding register 3 low (tc3h) 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 730 freescale semiconductor figure 19-66. detailed timer block diagram in latch mode when prnt = 0 16 bit main timer p1 comparator tc0h hold reg. p0 p3 p2 p4 p5 p6 p7 edg0 edg1 edg2 edg3 mux modulus prescaler bus clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 4, 8, 16 16-bit free-running latch under?w main timer timer prescaler tc0 capture/compare reg. comparator tc1 capture/compare reg. comparator tc2 capture/compare reg. comparator tc3 capture/compare reg. comparator tc4 capture/compare reg. comparator tc5 capture/compare reg. comparator tc6 capture/compare reg. comparator tc7 capture/compare reg. pin logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic delay tc1h hold reg. tc2h hold reg. tc3h hold reg. mux mux mux pa0h hold reg. pac 0 0 reset pa1h hold reg. pac 1 0 reset pa2h hold reg. pac 2 0 reset pa3h hold reg. pac 3 write 0x0000 to modulus counter iclat, latq, bufen (force latch) latq (mdc latch enable) down counter sh04 sh15 sh26 sh37 bus clock 1, 2, ..., 128 counter delay counter delay counter delay counter 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 731 figure 19-67. detailed timer block diagram in latch mode when prnt = 1 16 bit main timer p1 comparator tc0h hold reg. p0 p3 p2 p4 p5 p6 p7 edg0 edg1 edg2 edg3 mux modulus prescaler bus clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2,3, ..., 256 16-bit free-running latch under?w main timer timer prescaler tc0 capture/compare reg. comparator tc1 capture/compare reg. comparator tc2 capture/compare reg. comparator tc3 capture/compare reg. comparator tc4 capture/compare reg. comparator tc5 capture/compare reg. comparator tc6 capture/compare reg. comparator tc7 capture/compare reg. pin logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic delay tc1h hold reg. tc2h hold reg. tc3h hold reg. mux mux mux pa0h hold reg. pac 0 0 reset pa1h hold reg. pac 1 0 reset pa2h hold reg. pac 2 0 reset pa3h hold reg. pac 3 write 0x0000 to modulus counter iclat, latq, bufen (force latch) latq (mdc latch enable) down counter sh04 sh15 sh26 sh37 bus clock 1, 2,3, ..., 256 counter delay counter delay counter delay counter 8, 12, 16, ..., 1024 8, 12, 16, ..., 1024 8, 12, 16, ..., 1024 8, 12, 16, ..., 1024 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 732 freescale semiconductor figure 19-68. detailed timer block diagram in queue mode when prnt = 0 16 bit main timer p1 tc0h hold reg. p0 p3 p2 p4 p5 p6 p7 edg0 edg1 edg2 edg3 mux bus clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2, ..., 128 1, 4, 8, 16 latch0 pin logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic bus clock tc1h hold reg. tc2h hold reg. tc3h hold reg. mux mux mux pa0h hold reg. pac 0 0 reset pa1h hold reg. pac 1 0 reset pa2h hold reg. pac 2 0 reset pa3h hold reg. pac 3 latch1 latch3 latch2 latq, bufen (queue mode) read tc3h hold reg. read tc2h hold reg. read tc1h hold reg. read tc0h hold reg. down counter sh04 sh15 sh26 sh37 timer prescaler 16-bit free-running main timer delay counter delay counter delay counter delay counter modulus prescaler comparator tc0 capture/compare reg. comparator tc1 capture/compare reg. comparator tc2 capture/compare reg. comparator tc3 capture/compare reg. comparator tc4 capture/compare reg. comparator tc5 capture/compare reg. comparator tc6 capture/compare reg. comparator tc7 capture/compare reg. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 733 figure 19-69. detailed timer block diagram in queue mode when prnt = 1 16 bit main timer p1 tc0h hold reg. p0 p3 p2 p4 p5 p6 p7 edg0 edg1 edg2 edg3 mux bus clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2, 3, ... 256 1, 2, 3, ... 256 latch0 pin logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic bus clock tc1h hold reg. tc2h hold reg. tc3h hold reg. mux mux mux pa0h hold reg. pac 0 0 reset pa1h hold reg. pac 1 0 reset pa2h hold reg. pac 2 0 reset pa3h hold reg. pac 3 latch1 latch3 latch2 latq, bufen (queue mode) read tc3h hold reg. read tc2h hold reg. read tc1h hold reg. read tc0h hold reg. down counter sh04 sh15 sh26 sh37 timer prescaler 16-bit free-running main timer delay counter delay counter delay counter delay counter modulus prescaler comparator tc0 capture/compare reg. comparator tc1 capture/compare reg. comparator tc2 capture/compare reg. comparator tc3 capture/compare reg. comparator tc4 capture/compare reg. comparator tc5 capture/compare reg. comparator tc6 capture/compare reg. comparator tc7 capture/compare reg. 8, 12, 16, ... 1024 8, 12, 16, ... 1024 8, 12, 16, ... 1024 8, 12, 16, ... 1024 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 734 freescale semiconductor figure 19-70. 8-bit pulse accumulators block diagram p0 load holding register and reset pulse accumulator 0 0 edg3 edg2 edg1 edg0 edge detector delay counter interrupt interrupt p1 edge detector delay counter p2 edge detector delay counter p3 edge detector delay counter pa0h holding 0 8-bit pac1 (pacn1) 0 8-bit pac2 (pacn2) pa2h holding 0 8-bit pac3 (pacn3) pa3h holding 8-bit pac0 (pacn0) 8, 12,16, ..., 1024 8, 12,16, ..., 1024 8, 12,16, ..., 1024 8, 12,16, ..., 1024 register pa1h holding register register register 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 735 figure 19-71. 16-bit pulse accumulators block diagram figure 19-72. block diagram for port 7 with output compare/pulse accumulator a edge detector p7 p0 bus clock divide by 64 clock select clk0 clk1 4:1 mux timclk (timer clock) paclk paclk / 256 paclk / 65536 prescaled clock (pclk) interrupt mux (pamod) edge detector pac a delay counter interrupt pac b 8-bit pac3 (pacn3) 8-bit pac2 (pacn2) 8-bit pac1 (pacn1) 8-bit pac0 (pacn0) px edge delay 16-bit main timer tcx input tcxh i.c. bufen ? la tq ? tfmod set cxf detector counter capture register holding register interrupt 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 736 freescale semiconductor 19.4.1 enhanced capture timer modes of operation the enhanced capture timer has 8 input capture, output compare (ic/oc) channels, same as on the hc12 standard timer (timer channels tc0 to tc7). when channels are selected as input capture by selecting the iosx bit in tios register, they are called input capture (ic) channels. four ic channels (channels 7?) are the same as on the standard timer with one capture register each that memorizes the timer value captured by an action on the associated input pin. four other ic channels (channels 3?), in addition to the capture register, also have one buffer each called a holding register. this allows two different timer values to be saved without generating any interrupts. four 8-bit pulse accumulators are associated with the four buffered ic channels (channels 3?). each pulse accumulator has a holding register to memorize their value by an action on its external input. each pair of pulse accumulators can be used as a 16-bit pulse accumulator. the 16-bit modulus down-counter can control the transfer of the ic registers and the pulse accumulators contents to the respective holding registers for a given period, every time the count reaches zero. the modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability. 19.4.1.1 ic channels the ic channels are composed of four standard ic registers and four buffered ic channels. an ic register is empty when it has been read or latched into the holding register. a holding register is empty when it has been read. 19.4.1.1.1 non-buffered ic channels the main timer value is memorized in the ic register by a valid input pin transition. if the corresponding novwx bit of the icovw register is cleared, with a new occurrence of a capture, the contents of ic register are overwritten by the new value. if the corresponding novwx bit of the icovw register is set, the capture register cannot be written unless it is empty. this will prevent the captured value from being overwritten until it is read. 19.4.1.1.2 buffered ic channels there are two modes of operations for the buffered ic channels: 1. ic latch mode (latq = 1) the main timer value is memorized in the ic register by a valid input pin transition (see figure 19-66 and figure 19-67 ). the value of the buffered ic register is latched to its holding register by the modulus counter for a given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write to iclat in the mcctl register. if the corresponding novwx bit of the icovw register is cleared, with a new occurrence of a capture, the contents of ic register are overwritten by the new value. in case of latching, the contents of its holding register are overwritten. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 737 if the corresponding novwx bit of the icovw register is set, the capture register or its holding register cannot be written by an event unless they are empty (see section 19.4.1.1, ?c channels ). this will prevent the captured value from being overwritten until it is read or latched in the holding register. 2. ic queue mode (latq = 0) the main timer value is memorized in the ic register by a valid input pin transition (see figure 19-68 and figure 19-69 ). if the corresponding novwx bit of the icovw register is cleared, with a new occurrence of a capture, the value of the ic register will be transferred to its holding register and the ic register memorizes the new timer value. if the corresponding novwx bit of the icovw register is set, the capture register or its holding register cannot be written by an event unless they are empty (see section 19.4.1.1, ?c channels ). in queue mode, reads of the holding register will latch the corresponding pulse accumulator value to its holding register. 19.4.1.1.3 delayed ic channels there are four delay counters in this module associated with ic channels 0?. the use of this feature is explained in the diagram and notes below. figure 19-73. channel input validity with delay counter feature in figure 19-73 a delay counter value of 256 bus cycles is considered. 1. input pulses with a duration of (dly_cnt ?1) cycles or shorter are rejected. 2. input pulses with a duration between (dly_cnt ?1) and dly_cnt cycles may be rejected or accepted, depending on their relative alignment with the sample points. 3. input pulses with a duration between (dly_cnt ?1) and dly_cnt cycles may be rejected or accepted, depending on their relative alignment with the sample points. 4. input pulses with a duration of dly_cnt or longer are accepted. 1 2 3 253 254 255 256 bus clock dly_cnt input on ch0? rejected accepted input on ch0? input on ch0? accepted input on ch0? rejected 0 255 cycles 255.5 cycles 255.5 cycles 256 cycles 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 738 freescale semiconductor 19.4.1.2 oc channel initialization an internal compare channel whose output drives ocx may be programmed before the timer drives the output compare state (ocx). the required output of the compare logic can be disconnected from the pin, leaving it driven by the gp io port, by setting the appropriate ocpdx bit before enabling the output compare channel (by default the opcd bits are cleared which would enable the output compare logic to drive the pin as soon as the time output compare channel is enabled). the desired initial state can then be con?ured in the internal output compare logic by forcing a compare action with the logic disconnected from the io (by writing a one to cforcx bit with tiosx, ocpdx and ten bits set to one). clearing the output compare disconnect bit (ocpdx) will then allow the internal compare logic to drive the programmed state to ocx. this allows a glitch free switch over of the port from general purpose i/o to timer output. 19.4.1.3 pulse accumulators there are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four ic buffered channels 3?. a pulse accumulator counts the number of active edges at the input of its channel. the minimum pulse width for the pai input is greater than two bus clocks.the maximum input frequency on the pulse accumulator channel is one half the bus frequency or eclk. the user can prevent the 8-bit pulse accumulators from counting further than 0x00ff by utilizing the pacmx control bit in the icsys register. in this case, a value of 0x00ff means that 255 counts or more have occurred. each pair of pulse accumulators can be used as a 16-bit pulse accumulator (see figure 19-71 ). to operate the 16-bit pulse accumulators a and b (paca and pacb) independently of input capture or output compare 7 and 0 respectively, the user must set the corresponding bits: iosx = 1, omx = 0, and olx = 0. oc7m7 or oc7m0 in the oc7m register must also be cleared. there are two modes of operation for the pulse accumulators: pulse accumulator latch mode the value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control bit iclat is written. at the same time the pulse accumulator is cleared. pulse accumulator queue mode when queue mode is enabled, reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its holding register. at the same time the pulse accumulator is cleared. 19.4.1.4 modulus down-counter the modulus down-counter can be used as a time base to generate a periodic interrupt. it can also be used to latch the values of the ic registers and the pulse accumulators to their holding registers. the action of latching can be programmed to be periodic or only once. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 739 19.4.1.5 precision timer by enabling the prnt bit of the tscr1 register, the performance of the timer can be enhanced. in this case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter and enhance delay counter settings compared to the settings in the present ect timer. 19.4.1.6 flag clearing mechanisms the ?gs in the ect can be cleared one of two ways: 1. normal ?g clearing mechanism (tffca = 0) any of the ect ?gs can be cleared by writing a one to the ?g. 2. fast ?g clearing mechanism (tffca = 1) with the timer fast ?g clear all (tffca) enabled, the ect ?gs can only be cleared by accessing the various registers associated with the ect modes of operation as described below. the ?gs cannot be cleared via the normal ?g clearing mechanism . this fast ?g clearing mechanism has the advantage of eliminating the software overhead required by a separate clear sequence. extra care must be taken to avoid accidental ?g clearing due to unintended accesses. input capture a read from an input capture channel register causes the corresponding channel ?g, cxf, to be cleared in the tflg1 register. output compare a write to the output compare channel register causes the corresponding channel flag, cxf, to be cleared in the tflg1 register. timer counter any access to the tcnt register clears the tof flag in the tflg2 register. pulse accumulator a any access to the pacn3 and pacn2 registers clears the paovf and paif flags in the paflg register. pulse accumulator b any access to the pacn1 and pacn0 registers clears the pbovf flag in the pbflg register. modulus down counter any access to the mccnt register clears the mczf flag in the mcflg register. 19.4.2 reset the reset state of each individual bit is listed within the register description section ( section 19.3, ?emory map and register de?ition ) which details the registers and their bit-?lds. 4 .com u datasheet
chapter 19 enhanced capture timer (ect16b8cv3) MC9S12XHZ512 data sheet, rev. 1.02 740 freescale semiconductor 19.4.3 interrupts this section describes interrupts originated by the ect block. the mcu must service the interrupt requests. table 19-38 lists the interrupts generated by the ect to communicate with the mcu. table 19-38. ect interrupts the ect only originates interrupt requests. the following is a description of how the module makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt number are chip dependent. 19.4.3.1 channel [7:0] interrupt this active high output will be asserted by the module to request a timer channel 7? interrupt to be serviced by the system controller. 19.4.3.2 modulus counter interrupt this active high output will be asserted by the module to request a modulus counter under?w interrupt to be serviced by the system controller. 19.4.3.3 pulse accumulator b over?w interrupt this active high output will be asserted by the module to request a timer pulse accumulator b over?w interrupt to be serviced by the system controller. 19.4.3.4 pulse accumulator a input interrupt this active high output will be asserted by the module to request a timer pulse accumulator a input interrupt to be serviced by the system controller. 19.4.3.5 pulse accumulator a over?w interrupt this active high output will be asserted by the module to request a timer pulse accumulator a over?w interrupt to be serviced by the system controller. 19.4.3.6 timer over?w interrupt this active high output will be asserted by the module to request a timer over?w interrupt to be serviced by the system controller. interrupt source description timer channel 7? active high timer channel interrupts 7? modulus counter under?w active high modulus counter interrupt pulse accumulator b over?w active high pulse accumulator b interrupt pulse accumulator a input active high pulse accumulator a input interrupt pulse accumulator a over?w pulse accumulator over?w interrupt timer over?w timer 0ver?w interrupt 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 741 chapter 20 voltage regulator (vreg3v3v5) 20.1 introduction module vreg_3v3 is a dual output voltage regulator that provides two separate 2.5v (typical) supplies differing in the amount of current that can be sourced. the regulator input voltage range is from 3.3v up to 5v (typical). 20.1.1 features module vreg_3v3 includes these distinctive features: two parallel, linear voltage regulators bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) low-voltage reset (lvr) autonomous periodical interrupt (api) 20.1.2 modes of operation there are three modes vreg_3v3 can operate in: 1. full performance mode (fpm) (mcu is not in stop mode) the regulator is active, providing the nominal supply voltage of 2.5 v with full current sourcing capability at both outputs. features lvd (low-voltage detect), lvr (low-voltage reset), and por (power-on reset) are available. the api is available. 2. reduced power mode (rpm) (mcu is in stop mode) the purpose is to reduce power consumption of the device. the output voltage may degrade to a lower value than in full performance mode, additionally the current sourcing capability is substantially reduced. only the por is available in this mode, lvd and lvr are disabled. the api is available. 3. shutdown mode controlled by vregen (see device level speci?ation for connectivity of vregen). this mode is characterized by minimum power consumption. the regulator outputs are in a high-impedance state, only the por feature is available, lvd and lvr are disabled. the api internal rc oscillator clock is not available. this mode must be used to disable the chip internal regulator vreg_3v3, i.e., to bypass the vreg_3v3 to use external supplies. 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 742 freescale semiconductor 20.1.3 block diagram figure 20-1 shows the function principle of vreg_3v3 by means of a block diagram. the regulator core reg consists of two parallel subblocks, reg1 and reg2, providing two independent output voltages. figure 20-1. vreg_3v3 block diagram lv r lv d por v ddr v dd lv i por lv r ctrl v ss v ddpll v sspll v regen reg reg2 reg1 pin v dda v ssa reg: regulator core ctrl: regulator control lvd: low-voltage detect lvr: low-voltage reset por: power-on reset api api api: auto. periodical interrupt vbg api rate select bus clock 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 743 20.2 external signal description due to the nature of vreg_3v3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. table 20-1 shows all signals of vreg_3v3 associated with pins. note check device level speci?ation for connectivity of the signals. 20.2.1 vddr ?regulator power input pins signal v ddr is the power input of vreg_3v3. all currents sourced into the regulator loads ?w through this pin. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between v ddr and v ssr (if v ssr is not available v ss ) can smooth ripple on v ddr . for entering shutdown mode, pin v ddr should also be tied to ground on devices without vregen pin. 20.2.2 vdda, vssa ?regulator reference supply pins signals v dda /v ssa, which are supposed to be relatively quiet, are used to supply the analog parts of the regulator. internal precision reference circuits are supplied from these signals. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between v dda and v ssa can further improve the quality of this supply. 20.2.3 vdd, vss ?regulator output1 (core logic) pins signals v dd /v ss are the primary outputs of vreg_3v3 that provide the power supply for the core logic. these signals are connected to device pins to allow external decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode an external supply driving v dd /v ss can replace the voltage regulator. table 20-1. signal properties name function reset state pull up v ddr power input (positive supply) v dda quiet input (positive supply) v ssa quiet input (ground) v dd primary output (positive supply) v ss primary output (ground) v ddpll secondary output (positive supply) v sspll secondary output (ground) v regen (optional) optional regulator enable 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 744 freescale semiconductor 20.2.4 vddpll, vsspll ?regulator output2 (pll) pins signals v ddpll /v sspll are the secondary outputs of vreg_3v3 that provide the power supply for the pll and oscillator. these signals are connected to device pins to allow external decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode, an external supply driving v ddpll /v sspll can replace the voltage regulator. 20.2.5 v regen optional regulator enable pin this optional signal is used to shutdown vreg_3v3. in that case, v dd /v ss and v ddpll /v sspll must be provided externally. shutdown mode is entered with vregen being low. if vregen is high, the vreg_3v3 is either in full performance mode or in reduced power mode. for the connectivity of vregen, see device speci?ation. note switching from fpm or rpm to shutdown of vreg_3v3 and vice versa is not supported while mcu is powered. 20.3 memory map and register de?ition this section provides a detailed description of all registers accessible in vreg_3v3. if enabled in the system, the vreg_3v3 will abort all read and write accesses to reserved registers within its memory slice. 20.3.1 module memory map table 20-2 provides an overview of all used registers. table 20-2. memory map address offset use access 0x0000 ht control register (vreghtcl) 0x0001 control register (vregctrl) r/w 0x0002 autonomous periodical interrupt control register (vregapicl) r/w 0x0003 autonomous periodical interrupt trimming register (vregapitr) r/w 0x0004 autonomous periodical interrupt period high (vregapirh) r/w 0x0005 autonomous periodical interrupt period low (vregapirl) r/w 0x0006 reserved 06 0x0007 reserved 07 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 745 20.3.2 register descriptions this section describes all the vreg_3v3 registers and their individual bits. 20.3.2.1 ht control register (vreghtcl) the vreghtcl is reserved for test purposes. this register should not be written. 20.3.2.2 control register (vregctrl) the vregctrl register allows the con?uration of the vreg_3v3 low-voltage detect features. 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 20-2. ht control register (vreghtcl) 76543210 r00000lvds lvie lvif w reset 0 0 0 00000 = unimplemented or reserved figure 20-3. control register (vregctrl) table 20-3. vregctrl field descriptions field description 2 lvds low-voltage detect status bit ?this read-only status bit re?cts the input voltage. writes have no effect. 0 input voltage v dda is above level v lvid or rpm or shutdown mode. 1 input voltage v dda is below level v lvia and fpm. 1 lvie low-voltage interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever lvif is set. 0 lvif low-voltage interrupt flag lvif is set to 1 when lvds status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (lvie = 1), lvif causes an interrupt request. 0 no change in lvds bit. 1 lvds bit has changed. note: on entering the reduced power mode the lvif is not cleared by the vreg_3v3. 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 746 freescale semiconductor 20.3.2.3 autonomous periodical interrupt control register (vregapicl) the vregapicl register allows the con?uration of the vreg_3v3 autonomous periodical interrupt features. 76543210 r apiclk 0000 apife apie apif w reset 0 0 0 00000 = unimplemented or reserved figure 20-4. autonomous periodical interrupt control register (vregapicl) table 20-4. vregapicl field descriptions field description 7 apiclk autonomous periodical interrupt clock select bit ?selects the clock source for the api. writable only if apife = 0; apiclk cannot be changed if apife is set by the same write operation. 0 autonomous periodical interrupt clock used as source. 1 bus clock used as source. 2 apife autonomous periodical interrupt feature enable bit ?enables the api feature and starts the api timer when set. 0 autonomous periodical interrupt is disabled. 1 autonomous periodical interrupt is enabled and timer starts running. 1 apie autonomous periodical interrupt enable bit 0 api interrupt request is disabled. 1 api interrupt will be requested whenever apif is set. 0 apif autonomous periodical interrupt flag ?apif is set to 1 when the in the api con?ured time has elapsed. this ?g can only be cleared by writing a 1 to it. clearing of the ?g has precedence over setting. writing a 0 has no effect. if enabled (apie = 1), apif causes an interrupt request. 0 api timeout has not yet occurred. 1 api timeout has occurred. 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 747 20.3.2.4 autonomous periodical interrupt trimming register (vregapitr) the vregapitr register allows to trim the api timeout period. 76543210 r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w reset 0 1 0 1 0 1 0 1 0 1 0 1 00 1. reset value is either 0 or preset by factory. see device user guide for details. = unimplemented or reserved figure 20-5. autonomous periodical interrupt trimming register (vregapitr) table 20-5. vregapitr field descriptions field description 7? apitr[5:0] autonomous periodical interrupt period trimming bits ?see table 20-6 for trimming effects. table 20-6. trimming effect of apit bit trimming effect apitr[5] increases period apitr[4] decreases period less than apitr[5] increased it apitr[3] decreases period less than apitr[4] apitr[2] decreases period less than apitr[3] apitr[1] decreases period less than apitr[2] apitr[0] decreases period less than apitr[1] 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 748 freescale semiconductor 20.3.2.5 autonomous periodical interrupt rate high and low register (vregapirh / vregapirl) the vregapirh and vregapirl register allows the con?uration of the vreg_3v3 autonomous periodical interrupt rate. 76543210 r0000 apir11 apir10 apir9 apir8 w reset 0 0 0 00000 = unimplemented or reserved figure 20-6. autonomous periodical interrupt rate high register (vregapirh) 76543210 r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w reset 0 0 0 00000 figure 20-7. autonomous periodical interrupt rate low register (vregapirl) table 20-7. vregapirh / vregapirl field descriptions field description 11-0 apir[11:0] autonomous periodical interrupt rate bits these bits de?e the timeout period of the api. see table 20-8 for details of the effect of the autonomous periodical interrupt rate bits. writable only if apife = 0 of vregapicl register. 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 749 you can calculate the selected period depending of apiclk as: period = 2*(apir[11:0] + 1) * 0.1 ms or period = 2*(apir[11:0] + 1) * bus clock period table 20-8. selectable autonomous periodical interrupt periods apiclk apir[11:0] selected period 0 000 0.2 ms 1 1 when trimmed within speci?d accuracy. see electrical speci?ations for details. 0 001 0.4 ms 1 0 002 0.6 ms 1 0 003 0.8 ms 1 0 004 1.0 ms 1 0 005 1.2 ms 1 0 ..... ..... 0 ffd 818.8 ms 1 0 ffe 819 ms 1 0 fff 819.2 ms 1 1 000 2 * bus clock period 1 001 4 * bus clock period 1 002 6 * bus clock period 1 003 8 * bus clock period 1 004 10 * bus clock period 1 005 12 * bus clock period 1 ..... ..... 1 ffd 8188 * bus clock period 1 ffe 8190 * bus clock period 1 fff 8192 * bus clock period 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 750 freescale semiconductor 20.3.2.6 reserved 06 the reserved 06 is reserved for test purposes. 20.3.2.7 reserved 07 the reserved 07 is reserved for test purposes. 20.4 functional description 20.4.1 general module vreg_3v3 is a voltage regulator, as depicted in figure 20-1 . the regulator functional elements are the regulator core (reg), a low-voltage detect module (lvd), a control block (ctrl), a power-on reset module (por), and a low-voltage reset module (lvr). 20.4.2 regulator core (reg) respectively its regulator core has two parallel, independent regulation loops (reg1 and reg2) that differ only in the amount of current that can be delivered. the regulator is a linear regulator with a bandgap reference when operated in full performance mode. it acts as a voltage clamp in reduced power mode. all load currents ?w from input v ddr to v ss or v sspll . the reference circuits are supplied by v dda and v ssa . 20.4.2.1 full performance mode in full performance mode, the output voltage is compared with a reference voltage by an operational ampli?r. the ampli?d input voltage difference drives the gate of an output transistor. 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 20-8. reserved 06 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 20-9. reserved 07 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 751 20.4.2.2 reduced power mode in reduced power mode, the gate of the output transistor is connected directly to a reference voltage to reduce power consumption. 20.4.3 low-voltage detect (lvd) subblock lvd is responsible for generating the low-voltage interrupt (lvi). lvd monitors the input voltage (v dda ? ssa ) and continuously updates the status ?g lvds. interrupt ?g lvif is set whenever status ?g lvds changes its value. the lvd is available in fpm and is inactive in reduced power mode or shutdown mode. 20.4.4 power-on reset (por) this functional block monitors v dd . if v dd is below v pord , por is asserted; if v dd exceeds v pord , the por is deasserted. por asserted forces the mcu into reset. por deasserted will trigger the power-on sequence. 20.4.5 low-voltage reset (lvr) block lvr monitors the primary output voltage v dd . if it drops below the assertion level (v lvra ) signal, lvr asserts; if v dd rises above the deassertion level (v lvrd ) signal, lvr deasserts. the lvr function is available only in full performance mode. 20.4.6 regulator control (ctrl) this part contains the register block of vreg_3v3 and further digital functionality needed to control the operating modes. ctrl also represents the interface to the digital core logic. 20.4.7 autonomous periodical interrupt (api) subblock api can generate periodical interrupts independent of the clock source of the mcu. to enable the timer, the bit apife needs to be set. the api timer is either clocked by a trimmable internal rc oscillator or the bus clock. timer operation will freeze when mcu clock source is selected and bus clock is turned off. see crg speci?ation for details. the clock source can be selected with bit apiclk. apiclk can only be written when apife is not set. the apir[11:0] bits determine the interrupt period. apir[11:0] can only be written when apife is cleared. as soon as apife is set, the timer starts running for the period selected by apir[11:0] bits. when the con?ured time has elapsed, the ?g apif is set. an interrupt, indicated by ?g apif = 1, is triggered if interrupt enable bit apie = 1. the timer is started automatically again after it has set apif. the procedure to change apiclk or apir[11:0] is ?st to clear apife, then write to apiclk or apir[11:0], and afterwards set apife. 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 752 freescale semiconductor the api trimming bits apitr[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. see table 20-6 for the trimming effect of apitr. note the ?st period after enabling the counter by apife might be reduced. the api internal rc oscillator clock is not available if vreg_3v3 is in shutdown mode. 20.4.8 resets this section describes how vreg_3v3 controls the reset of the mcu.the reset values of registers and signals are provided in section 20.3, ?emory map and register de?ition . possible reset sources are listed in table 20-9 . 20.4.9 description of reset operation 20.4.9.1 power-on reset (por) during chip power-up the digital core may not work if its supply voltage v dd is below the por deassertion level (v pord ). therefore, signal por, which forces the other blocks of the device into reset, is kept high until v dd exceeds v pord . the mcu will run the start-up sequence after por deassertion. the power-on reset is active in all operation modes of vreg_3v3. 20.4.9.2 low-voltage reset (lvr) for details on low-voltage reset, see section 20.4.5, ?ow-voltage reset (lvr) . 20.4.10 interrupts this section describes all interrupts originated by vreg_3v3. the interrupt vectors requested by vreg_3v3 are listed in table 20-10 . vector addresses and interrupt priorities are de?ed at mcu level. table 20-9. reset sources reset source local enable power-on reset always active low-voltage reset available only in full performance mode table 20-10. interrupt vectors interrupt source local enable low-voltage interrupt (lvi) lvie = 1; available only in full performance mode 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 753 20.4.10.1 low-voltage interrupt (lvi) in fpm, vreg_3v3 monitors the input voltage v dda . whenever v dda drops below level v lvia, the status bit lvds is set to 1. on the other hand, lvds is reset to 0 when v dda rises above level v lvid .an interrupt, indicated by ?g lvif = 1, is triggered by any change of the status bit lvds if interrupt enable bit lvie = 1. note on entering the reduced power mode, the lvif is not cleared by the vreg_3v3. 20.4.10.2 autonomous periodical interrupt (api) as soon as the con?ured timeout period of the api has elapsed, the apif bit is set. an interrupt, indicated by ?g apif = 1, is triggered if interrupt enable bit apie = 1. autonomous periodical interrupt (api) apie = 1 table 20-10. interrupt vectors interrupt source local enable 4 .com u datasheet
chapter 20 voltage regulator (vreg3v3v5) MC9S12XHZ512 data sheet, rev. 1.02 754 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 755 chapter 21 background debug module (s12xbdmv2) 21.1 introduction this section describes the functionality of the background debug module (bdm) sub-block of the hcs12x core platform. the background debug module (bdm) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal cpu intervention. all interfacing with the bdm is done via the bkgd pin. the bdm has enhanced capability for maintaining synchronization between the target and host while allowing more ?xibility in clock rates. this includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. the system is backwards compatible to the bdm of the s12 family with the following exceptions: taggo command no longer supported by bdm external instruction tagging feature now part of dbg module bdm register map and register content extended/modi?d global page access functionality enabled but not active out of reset in emulation modes clksw bit set out of reset in emulation mode. family id readable from ?mware rom at global address 0x7fff0f (value for hcs12x devices is 0xc1) 21.1.1 features the bdm includes these distinctive features: single-wire communication with host development system enhanced capability for allowing more ?xibility in clock rates sync command to determine communication rate go_until command hardware handshake protocol to increase the performance of the serial communication active out of reset in special single chip mode nine hardware commands using free cycles, if available, for minimal cpu intervention hardware commands not requiring active bdm 14 ?mware commands execute from the standard bdm ?mware lookup table 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 756 freescale semiconductor software control of bdm operation during wait mode software selectable clocks global page access functionality enabled but not active out of reset in emulation modes clksw bit set out of reset in emulation mode. when secured, hardware commands are allowed to access the register space in special single chip mode, if the flash and eeprom erase tests fail. family id readable from ?mware rom at global address 0x7fff0f (value for hcs12x devices is 0xc1) bdm hardware commands are operational until system stop mode is entered (all bus masters are in stop mode) 21.1.2 modes of operation bdm is available in all operating modes but must be enabled before ?mware commands are executed. some systems may have a control bit that allows suspending thefunction during background debug mode. 21.1.2.1 regular run modes all of these operations refer to the part in run mode and not being secured. the bdm does not provide controls to conserve power during run mode. normal modes general operation of the bdm is available and operates the same in all normal modes. special single chip mode in special single chip mode, background operation is enabled and active out of reset. this allows programming a system with blank memory. emulation modes in emulation mode, background operation is enabled but not active out of reset. this allows debugging and programming a system in this mode more easily. 21.1.2.2 secure mode operation if the device is in secure mode, the operation of the bdm is reduced to a small subset of its regular run mode operation. secure operation prevents access to flash or eeprom other than allowing erasure. for more information please see section 21.4.1, ?ecurity . 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 757 21.1.2.3 low-power modes the bdm can be used until all bus masters (e.g., cpu or xgate) are in stop mode. when cpu is in a low power mode (wait or stop mode) all bdm ?mware commands as well as the hardware background command can not be used respectively are ignored. in this case the cpu can not enter bdm active mode, and only hardware read and write commands are available. also the cpu can not enter a low power mode during bdm active mode. if all bus masters are in stop mode, the bdm clocks are stopped as well. when bdm clocks are disabled and one of the bus masters exits from stop mode the bdm clocks will restart and bdm will have a soft reset (clearing the instruction register, any command in progress and disable the ack function). the bdm is now ready to receive a new command. 21.1.3 block diagram a block diagram of the bdm is shown in figure 21-1 . figure 21-1. bdm block diagram enbdm clksw bdmact trace sdv 16-bit shift register bkgd host system serial interface data control unsec register block register bdmsts instruction code and execution standard bdm firmware lookup table secured bdm firmware lookup table bus interface and control logic address data control clocks 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 758 freescale semiconductor 21.2 external signal description a single-wire interface pin called the background debug interface (bkgd) pin is used to communicate with the bdm system. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the background debug mode. 21.3 memory map and register de?ition 21.3.1 module memory map table 21-1 shows the bdm memory map when bdm is active. table 21-1. bdm memory map global address module size (bytes) 0x7fff00?x7fff0b bdm registers 12 0x7fff0c?x7fff0e bdm ?mware rom 3 0x7fff0f family id (part of bdm ?mware rom) 1 0x7fff10?x7fffff bdm ?mware rom 240 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 759 21.3.2 register descriptions a summary of the registers associated with the bdm is shown in figure 21-2 . registers are accessed by host-driven communications to the bdm hardware using read_bd and write_bd commands. global address register name bit 7 6 5 4 3 2 1 bit 0 0x7fff00 reserved r x x x x x x 0 0 w 0x7fff01 bdmsts r enbdm bdmact 0 sdv trace clksw unsec 0 w 0x7fff02 reserved r x x x x x x x x w 0x7fff03 reserved r x x x x x x x x w 0x7fff04 reserved r x x x x x x x x w 0x7fff05 reserved r x x x x x x x x w 0x7fff06 bdmccrl r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w 0x7fff07 bdmccrh r 0 0 0 0 0 ccr10 ccr9 ccr8 w 0x7fff08 bdmgpr r bgae bgp6 bgp5 bgp4 bgp3 bgp2 bgp1 bgp0 w 0x7fff09 reserved r 0 0 0 0 0 0 0 0 w 0x7fff0a reserved r 0 0 0 0 0 0 0 0 w 0x7fff0b reserved r 0 0 0 0 0 0 0 0 w = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero figure 21-2. bdm register summary 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 760 freescale semiconductor 21.3.2.1 bdm status register (bdmsts) figure 21-3. bdm status register ( bdmsts) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured, but subject to the following: enbdm should only be set via a bdm hardware command if the bdm ?mware commands are needed. (this does not apply in special single chip and emulation modes). bdmact can only be set by bdm hardware upon entry into bdm. it can only be cleared by the standard bdm ?mware lookup table upon exit from bdm active mode. clksw can only be written via bdm hardware write_bd commands. all other bits, while writable via bdm hardware or standard bdm ?mware write commands, should only be altered by the bdm hardware or standard ?mware lookup table as part of bdm command execution. register global address 0x7fff01 7 6 54 3 2 1 0 r enbdm bdmact 0sdv trace clksw unsec 0 w reset special single-chip mode 0 1 1 enbdm is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased (flash and eeprom). this is because the enbdm bit is set by the standard ?mware before a bdm command can be fully transmitted and executed. 1 00 0 0 0 3 3 unsec is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). 0 emulation modes 1 0 00 0 1 2 2 clksw is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when secured. 0 0 all other modes 0 0 00 0 0 0 0 = unimplemented, reserved = implemented (do not alter) 0 = always read zero table 21-2. bdmsts field descriptions field description 7 enbdm enable bdm ?this bit controls whether the bdm is enabled or disabled. when enabled, bdm can be made active to allow ?mware commands to be executed. when disabled, bdm cannot be made active but bdm hardware commands are still allowed. 0 bdm disabled 1 bdm enabled note: enbdm is set by the ?mware out of reset in special single chip mode and by hardware in emulation modes. in special single chip mode with the device secured, this bit will not be set by the ?mware until after the eeprom and flash erase verify tests are complete. in emulation modes with the device secured, the bdm operations are blocked. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 761 6 bdmact bdm active status ?this bit becomes set upon entering bdm. the standard bdm ?mware lookup table is then enabled and put into the memory map. bdmact is cleared by a carefully timed store instruction in the standard bdm ?mware as part of the exit sequence to return to user code and remove the bdm memory from the map. 0 bdm not active 1 bdm active 4 sdv shift data valid this bit is set and cleared by the bdm hardware. it is set after data has been transmitted as part of a ?mware or hardware read command or after data has been received as part of a ?mware or hardware write command. it is cleared when the next bdm command has been received or bdm is exited. sdv is used by the standard bdm ?mware to control program ?w execution. 0 data phase of command not complete 1 data phase of command is complete 3 trace trace1 bdm firmware command is being executed ?this bit gets set when a bdm trace1 ?mware command is ?st recognized. it will stay set until bdm ?mware is exited by one of the following bdm commands: go or go_until. 0 trace1 command is not being executed 1 trace1 command is being executed 2 clksw clock switch the clksw bit controls which clock the bdm operates with. it is only writable from a hardware bdm command. a minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send. the delay should be obtained no matter which bit is modi?d to effectively change the clock source (either pllsel bit or clksw bit). this guarantees that the start of the next bdm command uses the new clock for timing subsequent bdm communications. table 21-3 shows the resulting bdm clock source based on the clksw and the pllsel (pll select in the crg module, the bit is part of the clksel register) bits. note: the bdm alternate clock source can only be selected when clksw = 0 and pllsel = 1. the bdm serial interface is now fully synchronized to the alternate clock source, when enabled. this eliminates frequency restriction on the alternate clock which was required on previous versions. refer to the device speci?ation to determine which clock connects to the alternate clock source input. note: if the acknowledge function is turned on, changing the clksw bit will cause the ack to be at the new rate for the write command which changes it. note: in emulation mode, the clksw bit will be set out of reset. 1 unsec unsecure ?if the device is secured this bit is only writable in special single chip mode from the bdm secure ?mware. it is in a zero state as secure mode is entered so that the secure bdm ?mware lookup table is enabled and put into the memory map overlapping the standard bdm ?mware lookup table. the secure bdm ?mware lookup table veri?s that the on-chip eeprom and flash eeprom are erased. this being the case, the unsec bit is set and the bdm program jumps to the start of the standard bdm ?mware lookup table and the secure bdm ?mware lookup table is turned off. if the erase test fails, the unsec bit will not be asserted. 0 system is in a secured mode. 1 system is in a unsecured mode. note: when unsec is set, security is off and the user can change the state of the secure bits in the on-chip flash eeprom. note that if the user does not change the state of the bits to ?nsecured?mode, the system will be secured again when it is next taken out of reset.after reset this bit has no meaning or effect when the security byte in the flash eeprom is con?ured for unsecure mode. table 21-2. bdmsts field descriptions (continued) field description 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 762 freescale semiconductor 21.3.2.2 bdm ccr low holding register (bdmccrl) figure 21-4. bdm ccr low holding register (bdmccrl) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured note when bdm is made active, the cpu stores the content of its ccr l register in the bdmccrl register. however, out of special single-chip reset, the bdmccrl is set to 0xd8 and not 0xd0 which is the reset value of the ccr l register in this cpu mode. out of reset in all other modes the bdmccrl register is read zero. when entering background debug mode, the bdm ccr low holding register is used to save the low byte of the condition code register of the users program. it is also used for temporary storage in the standard bdm ?mware mode. the bdm ccr low holding register can be written to modify the ccr value. table 21-3. bdm clock sources pllsel clksw bdmclk 0 0 bus clock dependent on oscillator 0 1 bus clock dependent on oscillator 1 0 alternate clock (refer to the device speci?ation to determine the alternate clock source) 1 1 bus clock dependent on the pll register global address 0x7fff06 7 6 5 4 3 2 1 0 r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w reset special single-chip mode 1 1 0 0 1 0 0 0 all other modes 0 0 0 0 0 0 0 0 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 763 21.3.2.3 bdm ccr high holding register (bdmccrh) figure 21-5. bdm ccr high holding register (bdmccrh) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured when entering background debug mode, the bdm ccr high holding register is used to save the high byte of the condition code register of the users program. the bdm ccr high holding register can be written to modify the ccr value. 21.3.2.4 bdm global page index register (bdmgpr) figure 21-6. bdm global page register (bdmgpr) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured 21.3.3 family id assignment the family id is a 8-bit value located in the ?mware rom (at global address: 0x7fff0f). the read-only value is a unique family id which is 0xc1 for s12x devices. register global address 0x7fff07 7 6 5 4 3 2 1 0 r 0 0 0 0 0 ccr10 ccr9 ccr8 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved register global address 0x7fff08 7 6 5 4 3 2 1 0 r bgae bgp6 bgp5 bgp4 bgp3 bgp2 bgp1 bgp0 w reset 0 0 0 0 0 0 0 0 table 21-4. bdmgpr field descriptions field description 7 bgae bdm global page access enable bit bgae enables global page access for bdm hardware and ?mware read/write instructions the bdm hardware commands used to access the bdm registers (read_bd_ and write_bd_) can not be used for global accesses even if the bgae bit is set. 0 bdm global access disabled 1 bdm global access enabled 6? bgp[6:0] bdm global page index bits 6? ?these bits de?e the extended address bits from 22 to 16. for more detailed information regarding the global page window scheme, please refer to the s12x_mmc block guide. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 764 freescale semiconductor 21.4 functional description the bdm receives and executes commands from a host via a single wire serial interface. there are two types of bdm commands: hardware and ?mware commands. hardware commands are used to read and write target system memory locations and to enter active background debug mode, see section 21.4.3, ?dm hardware commands . target system memory includes all memory that is accessible by the cpu. firmware commands are used to read and write cpu resources and to exit from active background debug mode, see section 21.4.4, ?tandard bdm firmware commands . the cpu resources referred to are the accumulator (d), x index register (x), y index register (y), stack pointer (sp), and program counter (pc). hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see section 21.4.3, ?dm hardware commands ) and in secure mode (see section 21.4.1, ?ecurity ). firmware commands can only be executed when the system is not secure and is in active background debug mode (bdm). 21.4.1 security if the user resets into special single chip mode with the system secured, a secured mode bdm ?mware lookup table is brought into the map overlapping a portion of the standard bdm ?mware lookup table. the secure bdm ?mware veri?s that the on-chip eeprom and flash eeprom are erased. this being the case, the unsec and enbdm bit will get set. the bdm program jumps to the start of the standard bdm ?mware and the secured mode bdm ?mware is turned off and all bdm commands are allowed. if the eeprom or flash do not verify as erased, the bdm ?mware sets the enbdm bit, without asserting unsec, and the ?mware enters a loop. this causes the bdm hardware commands to become enabled, but does not enable the ?mware commands. this allows the bdm hardware to be used to erase the eeprom and flash. bdm operation is not possible in any other mode than special single chip mode when the device is secured. the device can only be unsecured via bdm serial interface in special single chip mode. for more information regarding security, please see the s12x_9sec block guide. 21.4.2 enabling and activating bdm the system must be in active bdm to execute standard bdm ?mware commands. bdm can be activated only after being enabled. bdm is enabled by setting the enbdm bit in the bdm status (bdmsts) register. the enbdm bit is set by writing to the bdm status (bdmsts) register, via the single-wire interface, using a hardware command such as write_bd_byte. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 765 after being enabled, bdm is activated by one of the following 1 : hardware background command cpu bgnd instruction external instruction tagging mechanism 2 breakpoint force or tag mechanism 2 when bdm is activated, the cpu ?ishes executing the current instruction and then begins executing the ?mware in the standard bdm ?mware lookup table. when bdm is activated by a breakpoint, the type of breakpoint used determines if bdm becomes active before or after execution of the next instruction. note if an attempt is made to activate bdm before being enabled, the cpu resumes normal instruction execution after a brief delay. if bdm is not enabled, any hardware background commands issued are ignored by the bdm and the cpu is not delayed. in active bdm, the bdm registers and standard bdm ?mware lookup table are mapped to addresses 0x7fff00 to 0x7fffff. bdm registers are mapped to addresses 0x7fff00 to 0x7fff0b. the bdm uses these registers which are readable anytime by the bdm. however, these registers are not readable by user programs. 21.4.3 bdm hardware commands hardware commands are used to read and write target system memory locations and to enter active background debug mode. target system memory includes all memory that is accessible by the cpu such as on-chip ram, eeprom, flash eeprom, i/o and control registers, and all external memory. hardware commands are executed with minimal or no cpu intervention and do not require the system to be in active bdm for execution, although, they can still be executed in this mode. when executing a hardware command, the bdm sub-block waits for a free bus cycle so that the background access does not disturb the running application program. if a free cycle is not found within 128 clock cycles, the cpu is momentarily frozen so that the bdm can steal a cycle. when the bdm ?ds a free cycle, the operation does not intrude on normal cpu operation provided that it can be completed in a single cycle. however, if an operation requires multiple cycles the cpu is frozen until the operation is complete, even though the bdm found a free cycle. the bdm hardware commands are listed in table 21-5 . the read_bd and write_bd commands allow access to the bdm register locations. these locations are not normally in the system memory map but share addresses with the application in memory. to distinguish between physical memory locations that share the same address, bdm memory resources are enabled just for the read_bd and write_bd access cycle. this allows the bdm to access bdm locations unobtrusively, even if the addresses con?ct with the application memory map. 1. bdm is enabled and active immediately out of special single-chip reset. 2. this method is provided by the s12x_dbg module. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 766 freescale semiconductor 21.4.4 standard bdm firmware commands firmware commands are used to access and manipulate cpu resources. the system must be in active bdm to execute standard bdm ?mware commands, see section 21.4.2, ?nabling and activating bdm . normal instruction execution is suspended while the cpu executes the ?mware located in the standard bdm ?mware lookup table. the hardware command background is the usual way to activate bdm. as the system enters active bdm, the standard bdm ?mware lookup table and bdm registers become visible in the on-chip memory map at 0x7fff00?x7fffff, and the cpu begins executing the standard bdm ?mware. the standard bdm ?mware watches for serial commands and executes them as they are received. the ?mware commands are shown in table 21-6 . table 21-5. hardware commands command opcode (hex) data description background 90 none enter background mode if ?mware is enabled. if enabled, an ack will be issued when the part enters active background mode. ack_enable d5 none enable handshake. issues an ack pulse after the command is executed. ack_disable d6 none disable handshake. this command does not issue an ack pulse. read_bd_byte e4 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table in map. odd address data on low byte; even address data on high byte. read_bd_word ec 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table in map. must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table out of map. odd address data on low byte; even address data on high byte. read_word e8 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table out of map. must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table in map. odd address data on low byte; even address data on high byte. write_bd_word cc 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table in map. must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table out of map. odd address data on low byte; even address data on high byte. write_word c8 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table out of map. must be aligned access. note: if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 767 table 21-6. firmware commands command 1 1 if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. opcode (hex) data description read_next 2 2 when the ?mware command read_next or write_next is used to access the bdm address space the bdm resources are accessed rather than user code. writing bdm ?mware is not possible. 62 16-bit data out increment x index register by 2 (x = x + 2), then read word x points to. read_pc 63 16-bit data out read program counter. read_d 64 16-bit data out read d accumulator. read_x 65 16-bit data out read x index register. read_y 66 16-bit data out read y index register. read_sp 67 16-bit data out read stack pointer. write_next

42 16-bit data in increment x index register by 2 (x = x + 2), then write word to location pointed to by x. write_pc 43 16-bit data in write program counter. write_d 44 16-bit data in write d accumulator. write_x 45 16-bit data in write x index register. write_y 46 16-bit data in write y index register. write_sp 47 16-bit data in write stack pointer. go 08 none go to user program. if enabled, ack will occur when leaving active background mode. go_until 3 3 system stop disables the ack function and ignored commands will not have an ack-pulse (e.g., cpu in stop or wait mode). the go_until command will not get an acknowledge if cpu executes the wait or stop instruction before the ?ntil condition (bdm active again) is reached (see section 21.4.7, ?erial interface hardware handshake protocol last note). 0c none go to user program. if enabled, ack will occur upon returning to active background mode. trace1 10 none execute one user instruction then return to active bdm. if enabled, ack will occur upon returning to active background mode. taggo -> go 18 none (previous enable tagging and go to user program.) this command will be deprecated and should not be used anymore. opcode will be executed as a go command. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 768 freescale semiconductor 21.4.5 bdm command structure hardware and ?mware bdm commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. all the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. if reading an even address, the valid data will appear in the msb. if reading an odd address, the valid data will appear in the lsb. 16-bit misaligned reads and writes are generally not allowed. if attempted by bdm hardware command, the bdm will ignore the least signi?ant bit of the address and will assume an even address from the remaining bits. the following cycle count information is only valid when the external wait function is not used (see wait bit of ebi sub-block). during an external wait the bdm can not steal a cycle. hence be careful with the external wait function if the bdm serial interface is much faster than the bus, because of the bdm soft-reset after time-out (see section 21.4.11, ?erial communication time out ). for hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. this is to be certain that valid data is available in the bdm shift register, ready to be shifted out. for hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the bdm waits for a free cycle before stealing a cycle. for ?mware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. this includes the potential of extra cycles when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the pru (port replacement unit) in emulation mode. the 48 cycle wait allows enough time for the requested data to be made available in the bdm shift register, ready to be shifted out. note this timing has increased from previous bdm modules due to the new capability in which the bdm serial interface can potentially run faster than the bus. on previous bdm modules this extra time could be hidden within the serial time. for ?mware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 769 the external host should wait at least for 76 bus clock cycles after a trace1 or go command before starting any new serial command. this is to allow the cpu to exit gracefully from the standard bdm ?mware lookup table and resume execution of the user code. disturbing the bdm shift register prematurely may adversely affect the exit from the standard bdm ?mware lookup table. note if the bus rate of the target processor is unknown or could be changing or the external wait function is used, it is recommended that the ack (acknowledge function) is used to indicate when an operation is complete. when using ack, the delay times are automated. figure 21-7 represents the bdm command structure. the command blocks illustrate a series of eight bit times starting with a falling edge. the bar across the top of the blocks indicates that the bkgd line idles in the high state. the time for an 8-bit command is 8 16 target clock cycles. 1 figure 21-7. bdm command structure 1. target clock cycles are cycles measured using the target mcus serial clock rate. see section 21.4.6, ?dm serial interface and section 21.3.2.1, ?dm status register (bdmsts) for information on how serial clock rate is selected. hardware hardware firmware firmware go, 48-bc bc = bus clock cycles command address 150-bc delay next delay 8 bits at ~ 16 tc/bit 16 bits at ~ 16 tc/bit 16 bits at ~ 16 tc/bit command address data next data read write read write trace command next command data 76-bc delay next command 150-bc delay 36-bc delay command command command command data next command tc = target clock cycles 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 770 freescale semiconductor 21.4.6 bdm serial interface the bdm communicates with external devices serially via the bkgd pin. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the bdm. the bdm serial interface is timed using the clock selected by the clksw bit in the status register see section 21.3.2.1, ?dm status register (bdmsts) . this clock will be referred to as the target clock in the following explanation. the bdm serial interface uses a clocking scheme in which the external host generates a falling edge on the bkgd pin to indicate the start of each bit time. this falling edge is sent for every bit whether data is transmitted or received. data is transferred most signi?ant bit (msb) ?st at 16 target clock cycles per bit. the interface times out if 512 clock cycles occur between falling edges from the host. the bkgd pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. it is assumed that there is an external pull-up and that drivers connected to bkgd do not typically drive the high level. since r-c rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive bkgd to a logic 1. the source of this speedup pulse is the host for transmit cases and the target for receive cases. the timing for host-to-target is shown in figure 21-8 and that of target-to-host in figure 21-9 and figure 21-10 . all four cases begin when the host drives the bkgd pin low to generate a falling edge. since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. the target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove bkgd low to start the bit up to one target clock cycle earlier. synchronization between the host and target is established in this manner at the start of every bit time. figure 21-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the bkgd pin of a target system. the host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. ten target clock cycles later, the target senses the bit level on the bkgd pin. internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 771 figure 21-8. bdm host-to-target serial bit timing the receive cases are more complicated. figure 21-9 shows the host receiving a logic 1 from the target system. since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target. the host holds the bkgd pin low long enough for the target to recognize it (at least two target clock cycles). the host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. the host should sample the bit level about 10 target clock cycles after it started the bit time. figure 21-9. bdm target-to-host serial bit timing (logic 1) target senses bit 10 cycles synchronization uncertainty bdm clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time earliest start of next bit high-impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin bdm clock (target mcu) host drive to bkgd pin target system speedup pulse high-impedance high-impedance 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 772 freescale semiconductor figure 21-10 shows the host receiving a logic 0 from the target. since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target. the host initiates the bit time but the target ?ishes it. since the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 target clock cycles then brie? drives it high to speed up the rising edge. the host samples the bit level about 10 target clock cycles after starting the bit time. figure 21-10. bdm target-to-host serial bit timing (logic 0) 21.4.7 serial interface hardware handshake protocol bdm commands that require cpu execution are ultimately treated at the mcu bus rate. since the bdm clock source can be asynchronously related to the bus frequency, when clksw = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the cpu. the alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. this sub-section will describe the hardware handshake protocol. the hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. this protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the bkgd pin. this pulse is generated by the target mcu when a command, issued by the host, has been successfully executed (see figure 21-11 ). this pulse is referred to as the ack pulse. after the ack pulse has ?ished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (background, go, go_until or trace1). the ack pulse is not issued earlier than 32 serial clock cycles after the bdm command was issued. the end of the bdm command is assumed to be the 16th tick of the last bit. this minimum delay assures enough time for the host to perceive the ack pulse. note also that, there is no upper limit for the delay between the command and the related ack pulse, since the command execution depends upon the cpu bus frequency, which in some cases could be very slow earliest start of next bit bdm clock (target mcu) host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target system drive and speedup pulse speedup pulse high-impedance 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 773 compared to the serial communication rate. this protocol allows a great ?xibility for the pod designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. figure 21-11. target acknowledge pulse (ack) note if the ack pulse was issued by the target, the host assumes the previous command was executed. if the cpu enters wait or stop prior to executing a hardware command, the ack pulse will not be issued meaning that the bdm command was not executed. after entering wait or stop mode, the bdm command is no longer pending. figure 21-12 shows the ack handshake protocol in a command level timing diagram. the read_byte instruction is used as an example. first, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. the target bdm decodes the instruction. a bus cycle is grabbed (free or stolen) by the bdm and it executes the read_byte operation. having retrieved the data, the bdm issues an ack pulse to the host controller, indicating that the addressed byte is ready to be retrieved. after detecting the ack pulse, the host initiates the byte retrieval process. note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even. figure 21-12. handshake protocol at command level 16 cycles bdm clock (target mcu) target transmits ack pulse high-impedance bkgd pin minimum delay from the bdm command 32 cycles earliest start of next bit speedup pulse 16th tick of the last command bit high-impedance read_byte bdm issues the bkgd pin byte address bdm executes the read_byte command host target host target bdm decodes the command ack pulse (out of scale) host target (2) bytes are retrieved new bdm command 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 774 freescale semiconductor differently from the normal bit transfer (where the host initiates the transmission), the serial interface ack handshake pulse is initiated by the target mcu by issuing a negative edge in the bkgd pin. the hardware handshake protocol in figure 21-11 speci?s the timing when the bkgd pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical con?ct in the bkgd pin. note the only place the bkgd pin can have an electrical con?ct is when one side is driving low and the other side is issuing a speedup pulse (high). other ?ighs are pulled rather than driven. however, at low rates the time of the speedup pulse can become lengthy and so the potential con?ct time becomes longer as well. the ack handshake protocol does not support nested ack pulses. if a bdm command is not acknowledge by an ack pulse, the host needs to abort the pending command ?st in order to be able to issue a new bdm command. when the cpu enters wait or stop while the host issues a hardware command (e.g., write_byte), the target discards the incoming command due to the wait or stop being detected. therefore, the command is not acknowledged by the target, which means that the ack pulse will not be issued in this case. after a certain time the host (not aware of stop or wait) should decide to abort any possible pending ack pulse in order to be sure a new command can be issued. therefore, the protocol provides a mechanism in which a command, and its corresponding ack, can be aborted. note the ack pulse does not provide a time out. this means for the go_until command that it can not be distinguished if a stop or wait has been executed (command discarded and ack not issued) or if the ?ntil?condition (bdm active) is just not reached yet. hence in any case where the ack pulse of a command is not issued the possible pending command should be aborted before issuing a new command. see the handshake abort procedure described in section 21.4.8, ?ardware handshake abort procedure . 21.4.8 hardware handshake abort procedure the abort procedure is based on the sync command. in order to abort a command, which had not issued the corresponding ack pulse, the host controller should generate a low pulse in the bkgd pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. by detecting this long low pulse in the bkgd pin, the target executes the sync protocol, see section 21.4.9, ?ync request timed reference pulse , and assumes that the pending command and therefore the related ack pulse, are being aborted. therefore, after the sync protocol has been completed the host is free to issue new bdm commands. for firmware read or write commands it can not be guaranteed that the pending command is aborted when issuing a sync before the corresponding ack pulse. there is a short latency time from the time the read or write access begins until it is ?ished and the corresponding ack pulse is issued. the latency time depends on the ?mware read or write command that is issued and if the serial interface is running on a different clock rate than the bus. when the sync command starts during this latency time the read or write command will not be aborted, but the corresponding ack pulse will be aborted. a pending go, trace1 or 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 775 go_until command can not be aborted. only the corresponding ack pulse can be aborted by the sync command. although it is not recommended, the host could abort a pending bdm command by issuing a low pulse in the bkgd pin shorter than 128 serial clock cycles, which will not be interpreted as the sync command. the ack is actually aborted when a negative edge is perceived by the target in the bkgd pin. the short abort pulse should have at least 4 clock cycles keeping the bkgd pin low, in order to allow the negative edge to be detected by the target. in this case, the target will not execute the sync protocol but the pending command will be aborted along with the ack pulse. the potential problem with this abort procedure is when there is a con?ct between the ack pulse and the short abort pulse. in this case, the target may not perceive the abort pulse. the worst case is when the pending command is a read command (i.e., read_byte). if the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. in this case, host and target will run out of synchronism. however, if the command to be aborted is not a read command the short abort pulse could be used. after a command is aborted the target assumes the next negative edge, after the abort pulse, is the ?st bit of a new bdm command. note the details about the short abort pulse are being provided only as a reference for the reader to better understand the bdm internal behavior. it is not recommended that this procedure be used in a real application. since the host knows the target serial clock frequency, the sync command (used to abort a command) does not need to consider the lower possible target frequency. in this case, the host could issue a sync very close to the 128 serial clock cycles length. providing a small overhead on the pulse length in order to assure the sync pulse will not be misinterpreted by the target. see section 21.4.9, ?ync ?request timed reference pulse . figure 21-13 shows a sync command being issued after a read_byte, which aborts the read_byte command. note that, after the command is aborted a new command could be issued by the host computer. figure 21-13. ack abort procedure at the command level note figure 21-13 does not represent the signals in a true timing scale read_byte read_status bkgd pin memory address new bdm command new bdm command host target host target host target sync response from the target (out of scale) bdm decode and starts to execute the read_byte command read_byte cmd is aborted by the sync request (out of scale) 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 776 freescale semiconductor figure 21-14 shows a con?ct between the ack pulse and the sync request pulse. this con?ct could occur if a pod device is connected to the target bkgd pin and the target is already in debug active mode. consider that the target cpu is executing a pending bdm command at the exact moment the pod is being connected to the bkgd pin. in this case, an ack pulse is issued along with the sync command. in this case, there is an electrical con?ct between the ack speedup pulse and the sync pulse. since this is not a probable situation, the protocol does not prevent this con?ct from happening. figure 21-14. ack pulse and sync request con?ct note this information is being provided so that the mcu integrator will be aware that such a con?ct could eventually occur. the hardware handshake protocol is enabled by the ack_enable and disabled by the ack_disable bdm commands. this provides backwards compatibility with the existing pod devices which are not able to execute the hardware handshake protocol. it also allows for new pod devices, that support the hardware handshake protocol, to freely communicate with the target device. if desired, without the need for waiting for the ack pulse. the commands are described as follows: ack_enable enables the hardware handshake protocol. the target will issue the ack pulse when a cpu command is executed by the cpu. the ack_enable command itself also has the ack pulse as a response. ack_disable disables the ack pulse protocol. in this case, the host needs to use the worst case delay time at the appropriate places in the protocol. the default state of the bdm after reset is hardware handshake protocol disabled. all the read commands will ack (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the bkgd serial pin. all the write commands will ack (if enabled) after the data has been received by the bdm through the bkgd serial pin and when the data bus cycle is complete. see section 21.4.3, ?dm hardware commands and section 21.4.4, ?tandard bdm firmware commands for more information on the bdm commands. bdm clock (target mcu) target mcu drives to bkgd pin bkgd pin 16 cycles speedup pulse high-impedance host drives sync to bkgd pin ack pulse host sync request pulse at least 128 cycles electrical con?ct host and target drive to bkgd pin 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 777 the ack_enable sends an ack pulse when the command has been completed. this feature could be used by the host to evaluate if the target supports the hardware handshake protocol. if an ack pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. if the target does not support the hardware handshake protocol the ack pulse is not issued. in this case, the ack_enable command is ignored by the target since it is not recognized as a valid command. the background command will issue an ack pulse when the cpu changes from normal to background mode. the ack pulse related to this command could be aborted using the sync command. the go command will issue an ack pulse when the cpu exits from background mode. the ack pulse related to this command could be aborted using the sync command. the go_until command is equivalent to a go command with exception that the ack pulse, in this case, is issued when the cpu enters into background mode. this command is an alternative to the go command and should be used when the host wants to trace if a breakpoint match occurs and causes the cpu to enter active background mode. note that the ack is issued whenever the cpu enters bdm, which could be caused by a breakpoint match or by a bgnd instruction being executed. the ack pulse related to this command could be aborted using the sync command. the trace1 command has the related ack pulse issued when the cpu enters background active mode after one instruction of the application program is executed. the ack pulse related to this command could be aborted using the sync command. 21.4.9 sync ?request timed reference pulse the sync command is unlike other bdm commands because the host does not necessarily know the correct communication speed to use for bdm communications until after it has analyzed the response to the sync command. to issue a sync command, the host should perform the following steps: 1. drive the bkgd pin low for at least 128 cycles at the lowest possible bdm serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by clksw.) 2. drive bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. remove all drive to the bkgd pin so it reverts to high impedance. 4. listen to the bkgd pin for the sync response pulse. upon detecting the sync request from the host, the target performs the following steps: 1. discards any incomplete command received or bit retrieved. 2. waits for bkgd to return to a logic one. 3. delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. drives bkgd low for 128 cycles at the current bdm serial communication frequency. 5. drives a one-cycle high speedup pulse to force a fast rise time on bkgd. 6. removes all drive to the bkgd pin so it reverts to high impedance. the host measures the low time of this 128 cycle sync response pulse and determines the correct speed for subsequent bdm communications. typically, the host can determine the correct communication speed 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 778 freescale semiconductor within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. as soon as the sync request is detected by the target, any partially received command or bit retrieved is discarded. this is referred to as a soft-reset, equivalent to a time-out in the serial communication. after the sync response, the target will consider the next negative edge (issued by the host) as the start of a new bdm command or the start of new sync request. another use of the sync command pulse is to abort a pending ack pulse. the behavior is exactly the same as in a regular sync command. note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. in this case, the command may not have been understood by the target and so an ack response pulse will not be issued. 21.4.10 instruction tracing when a trace1 command is issued to the bdm in active bdm, the cpu exits the standard bdm ?mware and executes a single instruction in the user code. once this has occurred, the cpu is forced to return to the standard bdm ?mware and the bdm is active and ready to receive a new command. if the trace1 command is issued again, the next user instruction will be executed. this facilitates stepping or tracing through the user code one instruction at a time. if an interrupt is pending when a trace1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. once back in standard bdm ?mware execution, the program counter points to the ?st instruction in the interrupt service routine. be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. hence possible timing relations between cpu code execution and occurrence of events of other peripherals no longer exist. do not trace the cpu instruction bgnd used for soft breakpoints. tracing the bgnd instruction will result in a return address pointing to bdm ?mware address space. when tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: the cpu enters stop or wait mode and the trace1 command can not be ?ished before leaving the low power mode. this is the case because bdm active mode can not be entered after cpu executed the stop instruction. however all bdm hardware commands except the background command are operational after tracing a stop or wait instruction and still being in stop or wait mode. if system stop mode is entered (all bus masters are in stop mode) no bdm command is operational. as soon as stop or wait mode is exited the cpu enters bdm active mode and the saved pc value points to the entry of the corresponding interrupt service routine. in case the handshake feature is enabled the corresponding ack pulse of the trace1 command will be discarded when tracing a stop or wait instruction. hence there is no ack pulse when bdm active mode is entered as part of the trace1 command after cpu exited from stop or wait mode. all valid commands sent during cpu being in stop or wait mode or after cpu exited from stop or wait mode will have an ack pulse. the handshake feature becomes disabled only when system 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 779 stop mode has been reached. hence after a system stop mode the handshake feature must be enabled again by sending the ack_enable command. 21.4.11 serial communication time out the host initiates a host-to-target serial transmission by generating a falling edge on the bkgd pin. if bkgd is kept low for more than 128 target clock cycles, the target understands that a sync command was issued. in this case, the target will keep waiting for a rising edge on bkgd in order to answer the sync request pulse. if the rising edge is not detected, the target will keep waiting forever without any time-out limit. consider now the case where the host returns bkgd to logic one before 128 cycles. this is interpreted as a valid bit transmission, and not as a sync request. the target will keep waiting for another falling edge marking the start of a new bit. if, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the mcu. this is referred to as a soft-reset. if a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. the data is not available for retrieval after the time-out has occurred. this is the expected behavior if the handshake protocol is not enabled. however, consider the behavior where the bdm is running in a frequency much greater than the cpu frequency. in this case, the command could time out before the data is ready to be retrieved. in order to allow the data to be retrieved even with a large clock frequency mismatch (between bdm and cpu) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. however, once the handshake pulse (ack pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ack pulse had been issued. after that period, the read command is discarded and the data is no longer available for retrieval. any negative edge in the bkgd pin after the time-out period is considered to be a new command or a sync request. note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. this means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. the next negative edge in the bkgd pin, after a soft-reset has occurred, is considered by the target as the start of a new bdm command, or the start of a sync request pulse. 4 .com u datasheet
chapter 21 background debug module (s12xbdmv2) MC9S12XHZ512 data sheet, rev. 1.02 780 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 781 chapter 22 s12x debug (s12xdbgv3) module 22.1 introduction the s12xdbg module provides an on-chip trace buffer with ?xible triggering capability to allow non-intrusive debug of application software. the s12xdbg module is optimized for the hcs12x 16-bit architecture and allows debugging of both s12xcpu and xgate module operations. typically the s12xdbg module is used in conjunction with the s12xbdm module, whereby the user con?ures the s12xdbg module for a debugging session over the bdm interface. once con?ured the s12xdbg module is armed and the device leaves bdm mode returning control to the user program, which is then monitored by the s12xdbg module. alternatively the s12xdbg module can be con?ured over a serial interface using swi routines. 22.1.1 glossary of terms cof: change of flow. change in the program ?w due to a conditional branch, indexed jump or interrupt. bdm : background debug mode dug: device user guide, describing the features of the device into which the dbg is integrated. word: 16 bit data entity data line : 64 bit data entity xgate : s12x family programmable direct memory access module cpu : s12x_cpu module tag : tags can be attached to xgate or cpu opcodes as they enter the instruction pipe. if the tagged opcode reaches the execution stage a tag hit occurs. 22.1.2 overview the comparators monitor the bus activity of the s12xcpu and xgate modules. when a match occurs the control logic can trigger the state sequencer to a new state. on a transition to the final state, bus tracing is triggered and/or a breakpoint can be generated. independent of comparator matches a transition to final state with associated tracing and breakpoint can be triggered by the external t a ghi and t a glo signals, by an xgate module s/w breakpoint request or an immediate trigger, instigated by writing to the trig control bit. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 782 freescale semiconductor the trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. tracing is disabled when the mcu system is secured. 22.1.3 features four comparators (a, b, c, and d) comparators a and c compare the full address bus and full 16-bit data bus comparators a and c feature a data bus mask register comparators b and d compare the full address bus only each comparator can be con?ured to monitor either s12xcpu or xgate buses each comparator features selection of read or write access cycles comparators b and d allow selection of byte or word access cycles comparisons can be used as triggers for the state sequencer three comparator modes simple address/data comparator match mode inside address range mode, addmin address addmax outside address range match mode, address < addmin or address > addmax two types of triggers tagged ?this triggers just before a speci? instruction begins execution force ?this triggers on the ?st instruction boundary after a match occurs. three types of breakpoints s12xcpu breakpoint entering bdm on breakpoint (bdm) s12xcpu breakpoint executing swi on breakpoint (swi) xgate breakpoint three trigger modes independent of comparators external instruction tagging (associated with s12xcpu instructions only) xgate s/w breakpoint request trig immediate software trigger four trace modes normal: change of ?w (cof) pc information is stored (see section 22.4.5.2.1 ) for change of ?w de?ition. loop1: same as normal but inhibits consecutive duplicate source address entries detail: address and data for all cycles except free cycles and opcode fetches are stored pure pc: all program counter addresses are stored. 4-stage state sequencer for trace buffer control tracing session trigger linked to final state of state sequencer begin, end, and mid alignment of tracing to trigger 22.1.4 modes of operation the s12xdbg module can be used in all mcu functional modes. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 783 during bdm hardware accesses and whilst the bdm module is active, s12xcpu monitoring is disabled. thus breakpoints, comparators, and bus tracing mapped to the s12xcpu are disabled but xgate bus monitoring accessing the s12xdbg registers, including comparator registers, is still possible. while in active bdm or during hardware bdm accesses, xgate activity can still be compared, traced and can be used to generate a breakpoint to the xgate module. when the s12xcpu enters active bdm mode through a background command, with the s12xdbg module armed, the s12xdbg remains armed. the s12xdbg module tracing is disabled if the mcu is secure. however, breakpoints can still be generated if the mcu is secure. 22.1.5 block diagram figure 22-1. debug module block diagram 22.2 external signal description the s12xdbg sub-module features two external tag input signals. see device user guide (dug) for the mapping of these signals to device pins. these tag pins may be used for the external tagging in emulation modes only. table 22-1. mode dependent restriction summary bdm enable bdm active mcu secure comparator matches enabled breakpoints possible tagging possible tracing possible x x 1 yes yes yes no 0 0 0 yes only swi yes yes 0 1 0 active bdm not possible when not enabled 1 0 0 yes yes yes yes 1 1 0 xgate only xgate only xgate only xgate only s12xcpu bus trace buffer bus interface trigger external taghi / taglo match0 state xgate bus comparator b comparator c comparator d comparator a state sequencer match1 match2 match3 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control xgate s/w breakpoint request trigger tag & trigger control logic tag s taghits state s12xcpu & xgate 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 784 freescale semiconductor 22.3 memory map and registers 22.3.1 module memory map a summary of the registers associated with the s12xdbg sub-block is shown in table 22-2 . detailed descriptions of the registers and bits are given in the subsections that follow. table 22-2. external system pins associated with s12xdbg pin name pin functions description t a ghi (see dug) taghi when instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. t a glo (see dug) taglo when instruction tagging is on, tags the low half of the instruction word being read into the instruction queue. t a glo (see dug) unconditional tagging enable in emulation modes, a low assertion on this pin in the 7th or 8th cycle after the end of reset enables the unconditional tagging function. address name bit 7 6 54321 bit 0 0x0020 dbgc1 r arm 0 xgsbpe bdm dbgbrk comrv w trig 0x0021 dbgsr r tbf extf 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r tsource trange trcmod talign w 0x0023 dbgc2 r0 0 0 0 cdcm abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r 0 cnt w 0x0027 dbgscrx r0 0 0 0 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 mc3 mc2 mc1 mc0 w 0x0028 1 dbgxctl (compa/c) r0 ndb tag brk rw rwe src compe w 0x0028 2 dbgxctl (compb/d) r sze sz tag brk rw rwe src compe w 0x0029 dbgxah r0 bit 22 21 20 19 18 17 bit 16 w figure 22-2. quick reference to s12xdbg registers 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 785 22.3.2 register descriptions this section consists of the s12xdbg control and trace buffer register descriptions in address order. each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002f in the s12xdbg module register address map. when arm is set in dbgc1, the only bits in the s12xdbg module registers that can be written are arm, trig, and comrv[1:0] 22.3.2.1 debug control register 1 (dbgc1) read: anytime write: bits 7, 1, 0 anytime bit 6 can be written anytime but always reads back as 0. bits 5:2 anytime s12xdbg is not armed. note when disarming the s12xdbg by clearing arm with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, arm = 1 preventing these bits from being written. these bits must be cleared using a second write if required. 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 54321 bit 0 w 0x002c dbgxdh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgxdl r bit 7 6 54321 bit 0 w 0x002e dbgxdhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgxdlm r bit 7 6 54321 bit 0 w 1 this represents the contents if the comparator a or c control register is blended into this address. 2 this represents the contents if the comparator b or d control register is blended into this address address: 0x0020 76543210 r arm 0 xgsbpe bdm dbgbrk comrv w trig reset 0 0 0 00000 figure 22-3. debug control register (dbgc1) address name bit 7 6 54321 bit 0 figure 22-2. quick reference to s12xdbg registers 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 786 freescale semiconductor table 22-3. dbgc1 field descriptions field description 7 arm arm bit ?the arm bit controls whether the s12xdbg module is armed. this bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. on setting this bit the state sequencer enters state1. 0 debugger disarmed 1 debugger armed 6 trig immediate trigger request bit ?this bit when written to 1 requests an immediate trigger independent of comparator or external tag signal status. when tracing is complete a forced breakpoint may be generated depending upon dbgbrk and bdm bit settings. this bit always reads back a 0. writing a 0 to this bit has no effect. if both tsource bits are clear no tracing is carried out. if tracing has already commenced using begin- or mid trigger alignment, it continues until the end of the tracing session as de?ed by the talign bit settings, thus trig has no affect. in secure mode tracing is disabled and writing to this bit has no effect. 0 do not trigger until the state sequencer enters the final state. 1 enter final state immediately and issue forced breakpoint request when tracing is completed. 5 xgsbpe xgate s/w breakpoint enable ?the xgsbpe bit controls whether an xgate s/w breakpoint request is passed to the s12xcpu. the xgate s/w breakpoint request is handled by the s12xdbg module, which can request an s12xcpu breakpoint depending on the state of this bit. 0 xgate s/w breakpoint request is disabled 1 xgate s/w breakpoint request is enabled 4 bdm background debug mode enable ?this bit determines if an s12x breakpoint causes the system to enter background debug mode (bdm) or initiate a software interrupt (swi). if this bit is set but the bdm is not enabled by the enbdm bit in the bdm module, then breakpoints default to swi. 0 breakpoint to software interrupt if bdm inactive. otherwise no breakpoint. 1 breakpoint to bdm, if bdm enabled. otherwise breakpoint to swi 3? dbgbrk s12xdbg breakpoint enable bits the dbgbrk bits control whether the debugger will request a breakpoint to either s12xcpu or xgate or both upon reaching the state sequencer final state. if tracing is enabled, the breakpoint is generated on completion of the tracing session. if tracing is not enabled, the breakpoint is generated immediately. please refer to section 22.4.7 for further details. xgate software breakpoints are independent of the dbgbrk bits. xgate software breakpoints force a breakpoint to the s12xcpu independent of the dbgbrk bit ?ld con?uration. see table 22-4 . 1? comrv comparator register visibility bits these bits determine which bank of comparator register is visible in the 8-byte window of the s12xdbg module address map, located between 0x0028 to 0x002f. furthermore these bits determine which register is visible at the address 0x0027. see table 22-5 . table 22-4. dbgbrk encoding dbgbrk resource halted by breakpoint 00 no breakpoint generated 01 xgate breakpoint generated 10 s12xcpu breakpoint generated 11 breakpoints generated for s12xcpu and xgate table 22-5. comrv encoding comrv visible comparator visible register at 0x0027 00 comparator a dbgscr1 01 comparator b dbgscr2 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 787 10 comparator c dbgscr3 11 comparator d dbgmfr table 22-5. comrv encoding comrv visible comparator visible register at 0x0027 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 788 freescale semiconductor 22.3.2.2 debug status register (dbgsr) read: anytime write: never address: 0x0021 76543210 r tbf extf 0 0 0 ssf2 ssf1 ssf0 w reset por 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 22-4. debug status register (dbgsr) table 22-6. dbgsr field descriptions field description 7 tbf trace buffer full the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of dbgcnt bits cnt[6:0]. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit 6 extf external tag hit flag ?the extf bit indicates if a tag hit condition from an external t a ghi/ t a glo tag was met since arming. this bit is cleared when arm in dbgc1 is written to a one. 0 external tag hit has not occurred 1 external tag hit has occurred 2? ssf[2:0] state sequencer flag bits the ssf bits indicate in which state the state sequencer is currently in. during a debug session on each transition to a new state these bits are updated. if the debug session is ended by software clearing the arm bit, then these bits retain their value to re?ct the last state of the state sequencer before disarming. if a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. on arming the module the state sequencer enters state1 and these bits are forced to ssf[2:0] = 001. see table 22-7 . table 22-7. ssf[2:0] ?state sequence flag bit encoding ssf[2:0] current state 000 state0 (disarmed) 001 state1 010 state2 011 state3 100 final state 101,110,111 reserved 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 789 22.3.2.3 debug trace control register (dbgtcr) read: anytime write: bits 7:6 only when s12xdbg is neither secure nor armed. bits 5:0 anytime the module is disarmed. address: 0x0022 76543210 r tsource trange trcmod talign w reset 0 0 0 00000 figure 22-5. debug trace control register (dbgtcr) table 22-8. dbgtcr field descriptions field description 7? tsource trace source control bits ?the tsource bits select the data source for the tracing session. if the mcu system is secured, these bits cannot be set and tracing is inhibited. see table 22-9 . 5? trange trace range bits the trange bits allow ?tering of trace information from a selected address range when tracing from the s12xcpu in detail mode. the xgate tracing range cannot be narrowed using these bits. to use a comparator for range ?tering, the corresponding compe and src bits must remain cleared. if the compe bit is not clear then the comparator will also be used to generate state sequence triggers. if the corresponding src bit is set the comparator is mapped to the xgate buses, the trange bits have no effect on the valid address range, memory accesses within the whole memory map are traced. see table 22-10 . 3? trcmod trace mode bits see section 22.4.5.2 for detailed trace mode descriptions. in normal mode, change of ?w information is stored. in loop1 mode, change of ?w information is stored but redundant entries into trace memory are inhibited. in detail mode, address and data for all memory and register accesses is stored. see table 22-11 . 1? talign trigger align bits ?these bits control whether the trigger is aligned to the beginning, end or the middle of a tracing session. see table 22-12 . table 22-9. tsource ?trace source bit encoding tsource tracing source 00 no tracing requested 01 s12xcpu 10 1 1 no range limitations are allowed. thus tracing operates as if trange = 00. xgate 11 1,2 2 no detail mode tracing supported. if trcmod = 10, no information is stored. both s12xcpu and xgate 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 790 freescale semiconductor table 22-10. trange trace range encoding trange tracing range 00 trace from all addresses (no ?ter) 01 trace only in address range from $00000 to comparator d 10 trace only in address range from comparator c to $7fffff 11 trace only in range from comparator c to comparator d table 22-11. trcmod trace mode bit encoding trcmod description 00 normal 01 loop1 10 detail 11 pure pc table 22-12. talign trace alignment encoding talign description 00 trigger at end of stored data 01 trigger before storing data 10 trace buffer entries before and after trigger 11 reserved 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 791 22.3.2.4 debug control register2 (dbgc2) read: anytime write: anytime the module is disarmed. this register con?ures the comparators for range matching. address: 0x0023 76543210 r0000 cdcm abcm w reset 0 0 0 00000 = unimplemented or reserved figure 22-6. debug control register2 (dbgc2) table 22-13. dbgc2 field descriptions field description 3? cdcm[1:0] c and d comparator match control ?these bits determine the c and d comparator match mapping as described in table 22-14 . 1? abcm[1:0] a and b comparator match control ?these bits determine the a and b comparator match mapping as described in table 22-15 . table 22-14. cdcm encoding cdcm description 00 match2 mapped to comparator c match....... match3 mapped to comparator d match. 01 match2 mapped to comparator c/d inside range....... match3 disabled. 10 match2 mapped to comparator c/d outside range....... match3 disabled. 11 reserved 1 1 currently defaults to match2 mapped to comparator c : match3 mapped to comparator d table 22-15. abcm encoding abcm description 00 match0 mapped to comparator a match....... match1 mapped to comparator b match. 01 match 0 mapped to comparator a/b inside range....... match1 disabled. 10 match 0 mapped to comparator a/b outside range....... match1 disabled. 11 reserved 1 1 currently defaults to match0 mapped to comparator a : match1 mapped to comparator b 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 792 freescale semiconductor 22.3.2.5 debug trace buffer register (dbgtbh:dbgtbl) read: anytime when unlocked and not secured and not armed. write: aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. address: 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w porxxxxxxxxxxxxxxxx other resets figure 22-7. debug trace buffer register (dbgtb) table 22-16. dbgtb field descriptions field description 15? bit[15:0] trace buffer data bits the trace buffer register is a window through which the 64-bit wide data lines of the trace buffer may be read 16 bits at a time. each valid read of dbgtb increments an internal trace buffer pointer which points to the next address to be read. when the arm bit is written to 1 the trace buffer is locked to prevent reading. the trace buffer can only be unlocked for reading by writing to dbgtb with an aligned word write when the module is disarmed. the dbgtb register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. the same is true for word reads while the debugger is armed. the por state is unde?ed other resets do not affect the trace buffer contents. . 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 793 22.3.2.6 debug count register (dbgcnt) read: anytime write: never address: 0x0026 76543210 r 0 cnt w reset por 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 22-8. debug count register (dbgcnt) table 22-17. dbgcnt field descriptions field description 6? cnt[6:0] count value the cnt bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer. table 22-18 shows the correlation between the cnt bits and the number of valid data lines in the trace buffer. when the cnt rolls over to zero, the tbf bit in dbgsr is set and incrementing of cnt will continue in end-trigger or mid-trigger mode. the dbgcnt register is cleared when arm in dbgc1 is written to a one. the dbgcnt register is cleared by power-on-reset initialization but is not cleared by other system resets. thus should a reset occur during a debug session, the dbgcnt register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. the dbgcnt register is not decremented when reading from the trace buffer. table 22-18. cnt decoding table tbf (dbgsr) cnt[6:0] description 0 0000000 no data valid 0 0000001 32 bits of one line valid 1 1 this applies to normal/loop1 modes when tracing from either s12xcpu or xgate only. 0 0000010 0000100 0000110 .. 1111100 1 line valid 2 lines valid 3 lines valid .. 62 lines valid 0 1111110 63 lines valid 1 0000000 64 lines valid; if using begin trigger alignment, arm bit will be cleared and the tracing session ends. 1 0000010 .. .. 1111110 64 lines valid, oldest data has been overwritten by most recent data 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 794 freescale semiconductor 22.3.2.7 debug state control registers there is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and de?es the next state for the state sequencer following a match. the three debug state control registers are located at the same address in the register address map (0x0027). each register can be accessed using the comrv bits in dbgc1 to blend in the required register. the comrv = 11 value blends in the match ?g register (dbgmfr). table 22-19. state control register access encoding comrv visible state control register 00 dbgscr1 01 dbgscr2 10 dbgscr3 11 dbgmfr 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 795 22.3.2.7.1 debug state control register 1 (dbgscr1) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 00. the state control register 1 selects the targeted next state whilst in state1. the matches refer to the match channels of the comparator match control logic as depicted in figure 22-1 and described in section 22.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. the trigger priorities described in table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches. address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 0 0 0 00000 = unimplemented or reserved figure 22-9. debug state control register 1 (dbgscr1) table 22-20. dbgscr1 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state1, based upon the match event. table 22-21. state1 sequencer next state selection sc[3:0] description 0000 any match triggers to state2 0001 any match triggers to state3 0010 any match triggers to final state 0011 match2 triggers to state2....... other matches have no effect 0100 match2 triggers to state3....... other matches have no effect 0101 match2 triggers to final state....... other matches have no effect 0110 match0 triggers to state2....... match1 triggers to state3....... other matches have no effect 0111 match1 triggers to state3....... match0 triggers final state....... other matches have no effect 1000 match0 triggers to state2....... match2 triggers to state3....... other matches have no effect 1001 match2 triggers to state3....... match0 triggers final state....... other matches have no effect 1010 match1 triggers to state2....... match3 triggers to state3....... other matches have no effect 1011 match3 triggers to state3....... match1 triggers to final state....... other matches have no effect 1100 match3 has no effect....... all other matches (m0,m1,m2) trigger to state2 1101 reserved 1110 reserved 1111 reserved 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 796 freescale semiconductor 22.3.2.7.2 debug state control register 2 (dbgscr2) read: if comrv[1:0] = 01 write: if comrv[1:0] = 01 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 01. the state control register 2 selects the targeted next state whilst in state2. the matches refer to the match channels of the comparator match control logic as depicted in figure 22-1 and described in section 22.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. the trigger priorities described in table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches. address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 0 0 0 00000 = unimplemented or reserved figure 22-10. debug state control register 2 (dbgscr2) table 22-22. dbgscr2 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state2, based upon the match event. table 22-23. state2 ?equencer next state selection sc[3:0] description 0000 any match triggers to state1 0001 any match triggers to state3 0010 any match triggers to final state 0011 match3 triggers to state1....... other matches have no effect 0100 match3 triggers to state3....... other matches have no effect 0101 match3 triggers to final state....... other matches have no effect 0110 match0 triggers to state1....... match1 triggers to state3....... other matches have no effect 0111 match1 triggers to state3....... match0 triggers final state....... other matches have no effect 1000 match0 triggers to state1....... match2 triggers to state3....... other matches have no effect 1001 match2 triggers to state3....... match0 triggers final state....... other matches have no effect 1010 match1 triggers to state1....... match3 triggers to state3....... other matches have no effect 1011 match3 triggers to state3....... match1 triggers final state....... other matches have no effect 1100 match2 triggers to state1..... match3 trigger to final state 1101 match2 has no affect, all other matches (m0,m1,m3) trigger to final state 1110 reserved 1111 reserved 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 797 22.3.2.7.3 debug state control register 3 (dbgscr3) read: if comrv[1:0] = 10 write: if comrv[1:0] = 10 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 10. the state control register three selects the targeted next state whilst in state3. the matches refer to the match channels of the comparator match control logic as depicted in figure 22-1 and described in section 22.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. the trigger priorities described in table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to final state has priority over all other matches. address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 0 0 0 00000 = unimplemented or reserved figure 22-11. debug state control register 3 (dbgscr3) table 22-24. dbgscr3 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state3, based upon the match event. table 22-25. state3 ?sequencer next state selection sc[3:0] description 0000 any match triggers to state1 0001 any match triggers to state2 0010 any match triggers to final state 0011 match0 triggers to state1....... other matches have no effect 0100 match0 triggers to state2....... other matches have no effect 0101 match0 triggers to final state.......match1 triggers to state1 0110 match1 triggers to state1....... other matches have no effect 0111 match1 triggers to state2....... other matches have no effect 1000 match1 triggers to final state....... other matches have no effect 1001 match2 triggers to state2....... match0 triggers to final state....... other matches have no effect 1010 match1 triggers to state1....... match3 triggers to state2....... other matches have no effect 1011 match3 triggers to state2....... match1 triggers to final state....... other matches have no effect 1100 match2 triggers to final state....... other matches have no effect 1101 match3 triggers to final state....... other matches have no effect 1110 reserved 1111 reserved 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 798 freescale semiconductor 22.3.2.7.4 debug match flag register (dbgmfr) read: if comrv[1:0] = 11 write: never dbgmfr is visible at 0x0027 only with comrv[1:0] = 11. it features four ?g bits each mapped directly to a channel. should a match occur on the channel during the debug session, then the corresponding ?g is set and remains set until the next time the module is armed by writing to the arm bit. thus the contents are retained after a debug session for evaluation purposes. these ?gs cannot be cleared by software, they are cleared only when arming the module. a set ?g does not inhibit the setting of other ?gs. once a ?g is set, further triggers on the same channel have no affect. 22.3.2.8 comparator register descriptions each comparator has a bank of registers that are visible through an 8-byte window in the s12xdbg module register address map. comparators a and c consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). comparators b and d consist of four register bytes (three address bus compare registers and a control register). each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the comrv bits in the dbgc1 register. if the comparators b or d are accessed through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with data bus and data bus masking read as zero and cannot be written. furthermore the control registers for comparators b and d differ from those of comparators a and c. address: 0x0027 76543210 r 0 0 0 0 mc3 mc2 mc1 mc0 w reset 0 0 0 00000 = unimplemented or reserved figure 22-12. debug match flag register (dbgmfr) table 22-26. comparator register layout 0x0028 control read/write comparators a,b,c,d 0x0029 address high read/write comparators a,b,c,d 0x002a address medium read/write comparators a,b,c,d 0x002b address low read/write comparators a,b,c,d 0x002c data high comparator read/write comparator a and c only 0x002d data low comparator read/write comparator a and c only 0x002e data high mask read/write comparator a and c only 0x002f data low mask read/write comparator a and c only 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 799 22.3.2.8.1 debug comparator control register (dbgxctl) the contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the dbg module register address map. read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. the dbgc1_comrv bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002f as shown in section table 22-27. table 22-27. comparator address register visibility address: 0x0028 76543210 r0 ndb tag brk rw rwe src compe w reset 0 0 0 00000 = unimplemented or reserved figure 22-13. debug comparator control register (comparators a and c) address: 0x0028 76543210 r sze sz tag brk rw rwe src compe w reset 0 0 0 00000 figure 22-14. debug comparator control register (comparators b and d) comrv visible comparator 00 dbgactl, dbgaah ,dbgaam, dbgaal, dbgadh, dbgadl, dbgadhm, dbgadlm 01 dbgbctl, dbgbah, dbgbam, dbgbal 10 dbgcctl, dbgcah, dbgcam, dbgcal, dbgcdh, dbgcdl, dbgcdhm, dbgcdlm 11 dbdactl, dbgdah, dbgdam, dbgdal table 22-28. dbgxctl field descriptions field description 7 sze (comparators b nd d) size comparator enable bit ?the sze bit controls whether access size comparison is enabled for the associated comparator. this bit is ignored if the tag bit in the same register is set. 0 word/byte access size is not used in comparison 1 word/byte access size is used in comparison 6 ndb (comparators a and c not data bus the ndb bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. furthermore data bus bits can be individually masked using the comparator data mask registers. this bit is only available for comparators a and c. this bit is ignored if the tag bit in the same register is set. this bit position has an sz functionality for comparators b and d. 0 match on data bus equivalence to comparator register contents 1 match on data bus difference to comparator register contents 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 800 freescale semiconductor table 22-29 shows the effect for rwe and rw on the comparison conditions. these bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. thus these bits are ignored if tagged triggering is selected. 6 sz (comparators b and d) size comparator value bit ?the sz bit selects either word or byte access size in comparison for the associated comparator. this bit is ignored if the sze bit is cleared or if the tag bit in the same register is set. this bit position has ndb functionality for comparators a and c 0 word access size will be compared 1 byte access size will be compared 5 tag tag select ?this bit controls whether the comparator match will cause a trigger or tag the opcode at the matched address. tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 trigger immediately on match 1 on match, tag the opcode. if the opcode is about to be executed a trigger is generated 4 brk break ?this bit controls whether a channel match terminates a debug session immediately, independent of state sequencer state. to generate an immediate breakpoint the module breakpoints must be enabled using the dbgc1 bits dbgbrk[1:0]. 0 the debug session termination is dependent upon the state sequencer and trigger conditions. 1 a match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 rw read/write comparator value bit the rw bit controls whether read or write is used in compare for the associated comparator. the rw bit is not used if rwe = 0. 0 write cycle will be matched 1 read cycle will be matched 2 rwe read/write enable bit ?the rwe bit controls whether read or write comparison is enabled for the associated comparator. this bit is not useful for tagged operations. 0 read/write is not used in comparison 1 read/write is used in comparison 1 src determines mapping of comparator to s12xcpu or xgate 0 the comparator is mapped to s12xcpu buses 1 the comparator is mapped to xgate address and data buses 0 compe determines if comparator is enabled 0 the comparator is not enabled 1 the comparator is enabled for state sequence triggers or tag generation table 22-29. read or write comparison logic table rwe bit rw bit rw signal comment 0 x 0 rw not used in comparison 0 x 1 rw not used in comparison 1 0 0 write data bus 1 0 1 no match 1 1 0 no match 1 1 1 read data bus table 22-28. dbgxctl field descriptions (continued) field description 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 801 22.3.2.8.2 debug comparator address high register (dbgxah) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. 22.3.2.8.3 debug comparator address mid register (dbgxam) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. address: 0x0029 76543210 r0 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 w reset 0 0 0 00000 = unimplemented or reserved figure 22-15. debug comparator address high register (dbgxah) table 22-30. dbgxah field descriptions field description 6? bit[22:16] comparator address high compare bits the comparator address high compare bits control whether the selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. this register byte is ignored for xgate compares. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one address: 0x002a 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 22-16. debug comparator address mid register (dbgxam) table 22-31. dbgxam field descriptions field description 7? bit[15:8] comparator address mid compare bits ?the comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 802 freescale semiconductor 22.3.2.8.4 debug comparator address low register (dbgxal) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. 22.3.2.8.5 debug comparator data high register (dbgxdh) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. address: 0x002b 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 22-17. debug comparator address low register (dbgxal) table 22-32. dbgxal field descriptions field description 7? bits[7:0] comparator address low compare bits ?the comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one address: 0x002c 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 22-18. debug comparator data high register (dbgxdh) table 22-33. dbgxah field descriptions field description 7? bits[15:8] comparator data high compare bits the comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparators a and c. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 803 22.3.2.8.6 debug comparator data low register (dbgxdl) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. 22.3.2.8.7 debug comparator data high mask register (dbgxdhm) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. address: 0x002d 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 22-19. debug comparator data low register (dbgxdl) table 22-34. dbgxdl field descriptions field description 7? bits[7:0] comparator data low compare bits the comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparators a and c. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one address: 0x002e 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 0 0 0 00000 figure 22-20. debug comparator data high mask register (dbgxdhm) table 22-35. dbgxdhm field descriptions field description 7? bits[15:8] comparator data high mask bits ?the comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. this register is available only for comparators a and c. 0 do not compare corresponding data bit 1 compare corresponding data bit 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 804 freescale semiconductor 22.3.2.8.8 debug comparator data low mask register (dbgxdlm) read: anytime. see table 22-27 for visible register encoding. write: if dbg not armed. see table 22-27 for visible register encoding. 22.4 functional description this section provides a complete functional description of the s12xdbg module. if the part is in secure mode, the s12xdbg module can generate breakpoints but tracing is not possible. 22.4.1 s12xdbg operation arming the s12xdbg module by setting arm in dbgc1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the s12xcpu or the xgate module. the dbg module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. the comparators monitor the bus activity of the s12xcpu and xgate modules. comparators can be con?ured to monitor address and databus. comparators can also be con?ured to mask out individual data bus bits during a compare and to use r/w and word/byte access quali?ation in the comparison. when a match with a comparator register value occurs the associated control logic can trigger the state sequencer to another state (see figure 22-23 ). either forced or tagged triggers are possible. using a forced trigger, the trigger is generated immediately on a comparator match. using a tagged trigger, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue is a trigger generated. in the case of a transition to final state, bus tracing is triggered and/or a breakpoint can be generated. tracing of both s12xcpu and/or xgate bus activity is possible. independent of the state sequencer, a breakpoint can be triggered by the external t a ghi / t a glo signals, by an xgate s/w breakpoint request or by writing to the trig bit in the dbgc1 control register. address: 0x002f 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 0 0 0 00000 figure 22-21. debug comparator data low mask register (dbgxdlm) table 22-36. dbgxdlm field descriptions field description 7? bits[7:0] comparator data low mask bits ?the comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. this register is available only for comparators a and c. 0 do not compare corresponding data bit 1 compare corresponding data bit 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 805 the trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. figure 22-22. s12xdbg overview 22.4.2 comparator modes the s12xdbg contains four comparators, a, b, c, and d. each comparator can be con?ured to monitor either s12xcpu or xgate buses using the src bit in the corresponding comparator control register. each comparator compares the selected address bus with the address stored in dbgxah, dbgxam, and dbgxal. furthermore, comparators a and c also compare the data buses to the data stored in dbgxdh, dbgxdl and allow masking of individual data bus bits. all comparators are disabled in bdm and during bdm accesses. the comparator match control logic (see figure 22-22 ) con?ures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the speci?d range generates a match condition. the comparator con?uration is controlled by the control register contents and the range control by the dbgc2 contents. on a match a trigger can initiate a transition to another state sequencer state (see section 22.4.3 ). the comparator control register also allows the type of access to be included in the comparison through the use of the rwe, rw, sze, and sz bits. the rwe bit controls whether read or write comparison is enabled for the associated comparator and the rw bit selects either a read or write access for a valid match. similarly the sze and sz bits allows the size of access (word or byte) to be considered in the compare. only comparators b and d feature sze and sz. the tag bit in each comparator control register is used to determine the triggering condition. by setting tag, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs s12xcpu bus trace buffer bus interface trigger external taghi / taglo match0 state xgate bus comparator b comparator c comparator d comparator a state sequencer match1 match2 match3 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control xgate s/w breakpoint request trigger tag & trigger control logic tag s taghits state s12xcpu & xgate 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 806 freescale semiconductor before the tagged instruction executes (tagged-type trigger). whilst tagging the rw, rwe, sze, and sz bits are ignored and the comparator register must be loaded with the exact opcode address. if the tag bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. if the selected address is an opcode address, the match is generated when the opcode is fetched from the memory. this precedes the instruction execution by an inde?ite number of cycles due to instruction pipe lining. for a comparator match of an opcode at an odd address when tag = 0, the corresponding even address must be contained in the comparator register. thus for an opcode at odd address (n), the comparator register must contain address (n?). once a successful comparator match has occurred, the condition that caused the original match is not veri?d again on subsequent matches. thus if a particular data value is veri?d at a given address, this address may not still contain that data value when a subsequent match occurs. comparators c and d can also be used to select an address range to trace from. this is determined by the trange bits in the dbgtcr register. the trange encoding is shown in table 22-10 . if the trange bits select a range de?ition using comparator d, then comparator d is con?ured for trace range de?ition and cannot be used for address bus comparisons. similarly if the trange bits select a range de?ition using comparator c, then comparator c is con?ured for trace range de?ition and cannot be used for address bus comparisons. match[0, 1, 2, 3] map directly to comparators[a, b, c, d] respectively, except in range modes (see section 22.3.2.4 ). comparator priority rules are described in the trigger priority section ( section 22.4.3.6? . 22.4.2.1 exact address comparator match (comparators a and c) with range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. further quali?ation of the type of access (r/w, word/byte) is possible. comparators a and c do not feature sze or sz control bits, thus the access size is not compared. the exact address is compared, thus with the comparator address register loaded with address (n) a misaligned word access of address (n?) also accesses (n) but does not cause a match. table 22-38 lists access considerations without data bus compare. table 22-37 lists access considerations with data bus comparison. to compare byte accesses dbgxdh must be loaded with the data byte. the low byte must be masked out using the dbgxdlm mask register. on word accesses the data byte of the lower address is mapped to dbgxdh. table 22-37. comparator a and c data bus considerations access address dbgxdh dbgxdl dbgxdhm dbgxdlm example valid match word addr[n] data[n] data[n+1] $ff $ff movw #$word addr[n] byte addr[n] data[n] x $ff $00 movb #$byte addr[n] word addr[n] data[n] x $ff $00 movw #$word addr[n] word addr[n] x data[n+1] $00 $ff movw #$word addr[n] 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 807 comparators a and c feature an ndb control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents. 22.4.2.2 exact address comparator match (comparators b and d) comparators b and d feature sz and sze control bits. if sze is clear, then the comparator address match quali?ation functions the same as for comparators a and c. if the sze bit is set the access size (word or byte) is compared with the sz bit value such that only the speci?d type of access causes a match. thus if con?ured for a byte access of a particular address, a word access covering the same address does not lead to match. 22.4.2.3 range comparisons when using the ab comparator pair for a range comparison, the data bus can also be used for quali?ation by using the comparator a data and data mask registers. furthermore the dbgactl rw and rwe bits can be used to qualify the range comparison on either a read or a write access. the corresponding dbgbctl bits are ignored. similarly when using the cd comparator pair for a range comparison, the data bus can also be used for quali?ation by using the comparator c data and data mask registers. furthermore the dbgcctl rw and rwe bits can be used to qualify the range comparison on either a read or a write access if tagging is not selected. the corresponding dbgdctl bits are ignored. the sze and sz control bits are ignored in range mode. the comparator a and c tag bits are used to tag range comparisons for the ab and cd ranges respectively. the comparator b and d tag bits are ignored in range modes. in order for a range comparison using comparators a and b, both compea and compeb must be set; to disable range comparisons both must be cleared. similarly for a range cd comparison, both compec and comped must be set. if a range mode is selected srca and srcc select the source (s12x or xgate), srcb and srcd are ignored. the comparator a and c brk bits are used for the ab and cd ranges respectively, the comparator b and d brk bits are ignored in range mode. when con?ured for range comparisons and tagging, the ranges are accurate only to word boundaries. table 22-38. comparator access size considerations comparator address sze sz8 condition for valid match comparators a and c addr[n] word and byte accesses of addr[n] 1 movb #$byte addr[n] movw #$word addr[n] 1 a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contain the exact address used in the code. comparators b and d addr[n] 0 x word and byte accesses of addr[n] 1 movb #$byte addr[n] movw #$word addr[n] comparators b and d addr[n] 1 0 word accesses of addr[n] 1 movw #$word addr[n] comparators b and d addr[n] 1 1 byte accesses of addr[n] movb #$byte addr[n] 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 808 freescale semiconductor 22.4.2.3.1 inside range (compac_addr address compbd_addr) in the inside range comparator mode, either comparator pair a and b or comparator pair c and d can be con?ured for range comparisons. this con?uration depends upon the control register (dbgc2). the match condition requires that a valid match for both comparators happens on the same bus cycle. a match condition on only one comparator is not valid. an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 22.4.2.3.2 outside range (address < compac_addr or address > compbd_addr) in the outside range comparator mode, either comparator pair a and b or comparator pair c and d can be con?ured for range comparisons. a single match condition on either of the comparators is recognized as valid. an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. in forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. this can be avoided by setting the upper range limit to $7fffff or lower range limit to $000000 respectively. when comparing the xgate address bus in outside range mode, the initial vector fetch as determined by the vector contained in the xgate xgvbr register should be taken into consideration. the xgvbr register and hence vector address can be modi?d. 22.4.3 trigger modes trigger modes are used as quali?rs for a state sequencer change of state. the control logic determines the trigger mode and provides a trigger to the state sequencer. the individual trigger modes are described in the following sections. 22.4.3.1 forced trigger on comparator match if a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state sequencer state whereby the corresponding ?gs in dbgsr are set. the state control register for the current state determines the next state for each trigger. forced triggers are generated as soon as the matching address appears on the address bus, which in the case of opcode fetches occurs several cycles before the opcode execution. for this reason a forced trigger of an opcode address precedes a tagged trigger at the same address by several cycles. 22.4.3.2 trigger on comparator related taghit if either a s12xcpu or xgate taghit occurs a transition to another state sequencer state is initiated and the corresponding dbgsr ?gs are set. for a comparator related taghit to occur, the s12xdbg must ?st generate tags based on comparator matches. when the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the s12xcpu/xgate. the state control register for the current state determines the next state for each trigger. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 809 22.4.3.3 external tagging trigger in external tagging trigger mode, the t a glo and t a ghi pins (mapped to device pins) are used to tag an instruction. this function can be used as another breakpoint source. when the tagged opcode reaches the execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session and generating a breakpoint, if breakpoints are enabled. external tagging is only possible in device emulation modes. 22.4.3.4 trigger on xgate s/w breakpoint request the xgate s/w breakpoint request issues a forced breakpoint request to the s12xcpu immediately independent of s12xdbg settings and triggers the state sequencer into the disarmed state. active tracing sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored. xgate generated breakpoints are independent of the dbgbrk bits. the xgsbpe bit in dbgc1 determines if the xgate s/w breakpoint function is enabled. the bdm bit in dbgc1 determines if the xgate requested breakpoint causes the system to enter bdm mode or initiate a software interrupt (swi). 22.4.3.5 immediate trigger independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or breakpoint by writing to the trig bit in dbgc1. this triggers the state sequencer into the final state and issues a forced breakpoint request to both s12xcpu and xgate. 22.4.3.6 trigger priorities in case of simultaneous triggers, the priority is resolved according to table 22-39 . the lower priority trigger is suppressed. it is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. the trigger priorities described in table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches independent of current state sequencer state. when con?ured for range modes a simultaneous match of comparators a and c generates an active match0 whilst match2 is suppressed. table 22-39. trigger priorities priority source action highest xgate immediate forced breakpoint......(tracing terminated immediately). trig enter final state external taghi/taglo enter state0 match0 (force or tag hit) trigger to next state as de?ed by state control registers match1 (force or tag hit) trigger to next state as de?ed by state control registers match2 (force or tag hit) trigger to next state as de?ed by state control registers lowest match3 (force or tag hit) trigger to next state as de?ed by state control registers 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 810 freescale semiconductor 22.4.4 state sequence control figure 22-23. state sequencer diagram the state sequencer allows a de?ed sequence of events to provide a trigger point for tracing of data in the trace buffer. once the s12xdbg module has been armed by setting the arm bit in the dbgc1 register, then state1 of the state sequencer is entered. further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. from final state the only permitted transition is back to the disarmed state0. transition between any of the states 1 to 3 is not restricted. each transition updates the ssf[2:0] ?gs in dbgsr accordingly to indicate the current state. alternatively writing to the trig bit in dbgsc1, the final state is entered and tracing starts immediately if the tsource bits are con?ured for tracing. a tag hit through t a ghi/ t a glo brings the state sequencer immediately into state0, causes a breakpoint, if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits talign[1:0]. independent of the state sequencer, each comparator channel can be individually con?ured to generate an immediate breakpoint when a match occurs through the use of the brk bits in the dbgxctl registers. thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. if a debug session is ended by a trigger on a channel with brk = 1, the state sequencer transitions through final state for a clock cycle to state0. this is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. an xgate s/w breakpoint request, if enabled causes a transition to the state0 and generates a breakpoint request to the s12xcpu immediately. 22.4.4.1 final state on entering final state a trigger may be issued to the trace buffer according to the trace position control as de?ed by the talign ?ld (see section 22.3.2.3 ). if the tsource bits in the trace control register dbgtcr are cleared then the trace buffer is disabled and the transition to final state can only generate a breakpoint request. in this case or upon completion of a tracing session when tracing is enabled, the arm state1 final state state3 arm = 1 session complete (disarm) state2 state 0 (disarmed) arm = 0 arm = 0 arm = 0 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 811 bit in the dbgc1 register is cleared, returning the module to the disarmed state0. if tracing is enabled a breakpoint request can occur at the end of the tracing session. if neither tracing nor breakpoints are enabled then when the ?al state is reached it returns automatically to state0 and the debug module is disarmed. 22.4.5 trace buffer operation the trace buffer is a 64 lines deep by 64-bits wide ram array. the s12xdbg module stores trace information in the ram array in a circular buffer format. the s12xcpu accesses the ram array through a register window (dbgtbh:dbgtbl) using 16-bit wide word accesses. after each complete 64-bit trace buffer line is read via the s12xcpu, an internal pointer into the ram is incremented so that the next read will receive fresh information. data is stored in the format shown in table 22-40 . after each store the counter register bits dbgcnt[6:0] are incremented. tracing of s12xcpu activity is disabled when the bdm is active but tracing of xgate activity is still possible. reading the trace buffer whilst the dbg is armed returns invalid data and the trace buffer pointer is not incremented. 22.4.5.1 trace trigger alignment using the talign bits (see section 22.3.2.3 ) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. if end or mid tracing is selected, tracing begins when the arm bit in dbgc1 is set and state1 is entered. the transition to final state if end is selected signals the end of the tracing session. the transition to final state if mid is selected signals that another 32 lines will be traced before ending the tracing session. tracing with begin-trigger starts at the opcode of the trigger. 22.4.5.1.1 storing with begin-trigger storing with begin-trigger, data is not stored in the trace buffer until the final state is entered. once the trigger condition is met the s12xdbg module will remain armed until 64 lines are stored in the trace buffer. if the trigger is at the address of the change-of-?w instruction the change of ?w associated with the trigger will be stored in the trace buffer. using begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 22.4.5.1.2 storing with mid-trigger storing with mid-trigger, data is stored in the trace buffer as soon as the s12xdbg module is armed. when the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the s12xdbg module is disarmed and no more data is stored. if the trigger is at the address of a change of ?w instruction the trigger event is not stored in the trace buffer. using mid-trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 812 freescale semiconductor 22.4.5.1.3 storing with end-trigger storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the s12xdbg module will become disarmed and no more data will be stored. if the trigger is at the address of a change of ?w instruction the trigger event will not be stored in the trace buffer. 22.4.5.2 trace modes the s12xdbg module can operate in four trace modes. the mode is selected using the trcmod bits in the dbgtcr register. in each mode tracing of xgate or s12xcpu information is possible. the source for the trace is selected using the tsource bits in the dbgtcr register. the modes are described in the following subsections. the trace buffer organization is shown in table 22-40 . 22.4.5.2.1 normal mode in normal mode, change of ?w (cof) program counter (pc) addresses will be stored. cof addresses are de?ed as follows for the s12xcpu: source address of taken conditional branches (long, short, bit-conditional, and loop primitives) destination address of indexed jmp, jsr, and call instruction. destination address of rti, rts, and rtc instructions vector address of interrupts, except for swi and bdm vectors lbra, bra, bsr, bgnd as well as non-indexed jmp, jsr, and call instructions are not classi?d as change of ?w and are not stored in the trace buffer. cof addresses are de?ed as follows for the xgate: source address of taken conditional branches destination address of indexed jal instructions. first xgate code address in a thread change-of-?w addresses stored include the full 23-bit address bus in the case of s12xcpu, the 16-bit address bus for the xgate module and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. 22.4.5.2.2 loop1 mode loop1 mode, similarly to normal mode also stores only cof address information to the trace buffer, it however allows the ?tering out of redundant information. the intent of loop1 mode is to prevent the trace buffer from being ?led entirely with duplicate information from a looping construct such as delays using the dbne instruction or polling loops using brset/brclr instructions. immediately after address information is placed in the trace buffer, the s12xdbg module writes this value into a background register. this prevents consecutive duplicate address entries in the trace buffer resulting from repeated branches. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 813 loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. it does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the users code that the s12xdbg module is designed to help ?d. note in certain very tight loops, the source address will have already been fetched again before the background comparator is updated. this results in the source address being stored twice before further duplicate entries are suppressed. this condition occurs with branch-on-bit instructions when the branch is fetched by the ?st p-cycle of the branch or with loop-construct instructions in which the branch is fetched with the ?st or second p cycle. see examples below: loop inx ; 1-byte instruction fetched by 1st p-cycle of brclr brclr cmptmp,#$0c, loop ; the brclr instruction also will be fetched by 1st ; p-cycle of brclr loop2 brn * ; 2-byte instruction fetched by 1st p-cycle of dbne nop ; 1-byte instruction fetched by 2nd p-cycle of dbne dbne a,loop2 ; this instruction also fetched by 2nd p-cycle of dbne 22.4.5.2.3 detail mode in detail mode, address and data for all memory and register accesses is stored in the trace buffer. in the case of xgate tracing this means that initialization of the r1 register during a vector fetch is not traced. this mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. this mode also features information byte storage to the trace buffer, for each address byte storage. the information byte indicates the size of access (word or byte), the type of access (read or write). when tracing s12xcpu activity in detail mode, all cycles are traced except those when the s12xcpu is either in a free or opcode fetch cycle. in this mode the xgate program counter is also traced to provide a snapshot of the xgate activity. cxinf information byte bits indicate the type of xgate activity occurring at the time of the trace buffer entry. when tracing s12xcpu activity alone in detail mode, the address range can be limited to a range speci?d by the trange bits in dbgtcr. this function uses comparators c and d to de?e an address range inside which s12xcpu activity should be traced (see table 22-40 ). thus the traced s12xcpu activity can be restricted to register range accesses. when tracing xgate activity in detail mode, all load and store cycles are traced. additionally the s12xcpu program counter is stored at the time of the xgate trace buffer entry to provide a snapshot of s12xcpu activity. 22.4.5.2.4 pure pc mode in pure pc mode, tracing from the cpu the pc addresses of all executed opcodes are stored. in pure pc mode, tracing from the xgate the pc addresses of all executed opcodes are stored. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 814 freescale semiconductor 22.4.5.3 trace buffer organization the buffer can be used to trace either from s12xcpu, from xgate or from both sources. an x pre? denotes information from the xgate module, a c pre? denotes information from the s12xcpu. adrh, adrm, adrl denote address high, middle and low byte respectively. inf bytes contain control information (r/w, s/d etc.). the numerical suf? indicates which tracing step. the information format for loop1 mode is the same as that of normal mode. whilst tracing from xgate or s12xcpu only, in normal or loop1 modes each array line contains data from entries made at two separate times, thus in this case the dbgcnt[0] is incremented after each separate entry. in all other modes dbgcnt[0] remains cleared whilst the other dbgcnt bits are incremented on each trace buffer entry. xgate and s12xcpu cofs occur independently of each other and the pro?e of cofs for the two sources is totally different. when both sources are being traced in normal or loop1 mode, for each cof from one source, there may be many cofs from the other source, depending on user code. cof events could occur far from each other in the time domain, on consecutive cycles or simultaneously. when a cof occurs in either source (s12x or xgate) a trace buffer entry is made and the corresponding cdv or xdv bit is set. the current pc of the other source is simultaneously stored to the trace buffer even if no cof has occurred, in which case cdv/xdv remains cleared indicating the address is not associated with a cof, but is simply a snapshot of the pc contents at the time of the cof from the other source. single byte data accesses in detail mode are always stored to the low byte of the trace buffer (cdatal or xdatal) and the high byte is cleared. when tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2 table 22-40. trace buffer organization mode 8-byte wide word buffer 76543210 xgate detail cxinf1 cadrh1 cadrm1 cadrl1 xdatah1 xdatal1 xadrm1 xadrl1 cxinf2 cadrh2 cadrm2 cadrl2 xdatah2 xdatal2 xadrm2 xadrl2 s12xcpu detail cxinf1 cadrh1 cadrm1 cadrl1 cdatah1 cdatal1 xadrm1 xadrl1 cxinf2 cadrh2 cadrm2 cadrl2 cdatah2 cdatal2 xadrm2 xadrl2 both other modes xinf0 xpcm0 xpcl0 cinf0 cpch0 cpcm0 cpcl0 xinf1 xpcm1 xpcl1 cinf1 cpch1 cpcm1 cpcl1 xgate other modes xinf1 xpcm1 xpcl1 xinf0 xpcm0 xpcl0 xinf3 xpcm3 xpcl3 xinf2 xpcm2 xpcl2 s12xcpu other modes cinf1 cpch1 cpcm1 cpcl1 cinf0 cpch0 cpcm0 cpcl0 cinf3 cpch3 cpcm3 cpcl3 cinf2 cpch2 cpcm2 cpcl2 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 815 22.4.5.3.1 information byte organization the format of the control information byte for both s12xcpu and xgate modules is dependent upon the active trace mode and tracing source as described below. in normal, loop1, or pure pc modes tracing of xgate activity, xinf is used to store control information. in normal, loop1, or pure pc modes tracing of s12xcpu activity, cinf is used to store control information. in detail mode, cxinf contains the control information xgate information byte x12x_cpu information byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xsd xsot xcot xdv 0 0 0 0 figure 22-24. xgate information byte xinf table 22-41. xinf field descriptions field description 7 xsd source destination indicator this bit indicates if the corresponding stored address is a source or destination address. this is only used in normal and loop1 mode tracing. 0 source address 1 destination address or start of thread or continuation of thread 6 xsot source of thread indicator ?this bit indicates that the corresponding stored address is a start of thread address. this is only used in normal and loop1 mode tracing. note. this bit only has effect on devices where the xgate module supports multiple interrupt levels . 0 stored address not from a start of thread 1 stored address from a start of thread 5 xcot continuation of thread indicator ?this bit indicates that the corresponding stored address is the ?st address following a return from a higher priority thread. this is only used in normal and loop1 mode tracing. note. this bit only has effect on devices where the xgate module supports multiple interrupt levels. 0 stored address not from a continuation of thread 1 stored address from a continuation of thread 4 xdv data invalid indicator ?this bit indicates if the trace buffer entry is invalid. it is only used when tracing from both sources in normal, loop1 and pure pc modes, to indicate that the xgate trace buffer entry is valid. 0 trace buffer entry is invalid 1 trace buffer entry is valid bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csd cva 0 cdv 0 0 0 0 figure 22-25. s12xcpu information byte cinf 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 816 freescale semiconductor cxinf information byte this describes the format of the information byte used only when tracing from s12xcpu or xgate in detail mode. when tracing from the s12xcpu in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. the xgate entry stored on the same line is a snapshot of the xgate program counter. in this case the csz and crw bits indicate the type of access being made by the s12xcpu, whilst the xack and xocf bits indicate if the simultaneous xgate cycle is a free cycle (no bus acknowledge) or opcode fetch cycle. similarly when tracing from the xgate in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. the s12xcpu entry stored on the same line is a snapshot of the s12xcpu program counter. in this case the xsz and xrw bits indicate the type of access being made by the xgate, whilst the cfree and cocf bits indicate if the simultaneous s12xcpu cycle is a free cycle or opcode fetch cycle. table 22-42. cinf field descriptions field description 7 csd source destination indicator this bit indicates if the corresponding stored address is a source or destination address. this is only used in normal and loop1 mode tracing. 0 source address 1 destination address 6 cva vector indicator this bit indicates if the corresponding stored address is a vector address.. this is only used in normal and loop1 mode tracing. 0 indexed jump destination address 1 vector destination address 4 cdv data invalid indicator ?this bit indicates if the trace buffer entry is invalid. it is only used when tracing from both sources in normal, loop1 and pure pc modes, to indicate that the s12xcpu trace buffer entry is valid. 0 trace buffer entry is invalid 1 trace buffer entry is valid bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfree csz crw cocf xack xsz xrw xocf figure 22-26. information byte cxinf table 22-43. cxinf field descriptions field description 7 cfree s12xcpu free cycle indicato r this bit indicates if the stored s12xcpu address corresponds to a free cycle. this bit only contains valid information when tracing the xgate accesses in detail mode. 0 stored information corresponds to free cycle 1 stored information does not correspond to free cycle 6 csz access type indicator this bit indicates if the access was a byte or word size access.this bit only contains valid information when tracing s12xcpu activity in detail mode. 0 word access 1 byte access 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 817 22.4.5.4 reading data from trace buffer the data stored in the trace buffer can be read using either the background debug module (bdm) module or the s12xcpu provided the s12xdbg module is not armed, is con?ured for tracing (at least one tsource bit is set) and the system not secured. when the arm bit is written to 1 the trace buffer is locked to prevent reading. the trace buffer can only be unlocked for reading by an aligned word write to dbgtb when the module is disarmed. the trace buffer can only be read through the dbgtb register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. the trace buffer data is read out ?st-in ?st-out. by reading cnt in dbgcnt the number of valid 64-bit lines can be determined. dbgcnt will not decrement as data is read. whilst reading an internal pointer is used to determine the next line to be read. after a tracing session, the pointer points to the oldest data entry, thus if no over?w has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. the pointer is initialized by each aligned write to dbgtbh to point to the oldest data again. this enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. the least signi?ant word of each 64-bit wide array line is read out ?st. this corresponds to the bytes 1 and 0 of table 22-40 . the bytes containing invalid information (shaded in table 22-40 ) are also read out. 5 crw read write indicator ?this bit indicates if the corresponding stored address corresponds to a read or write access. this bit only contains valid information when tracing s12xcpu activity in detail mode. 0 write access 1 read access 4 cocf s12xcpu opcode fetch indicator ?this bit indicates if the stored address corresponds to an opcode fetch cycle. this bit only contains valid information when tracing the xgate accesses in detail mode. 0 stored information does not correspond to opcode fetch cycle 1 stored information corresponds to opcode fetch cycle 3 xack xgate access indicator this bit indicates if the stored xgate address corresponds to a free cycle. this bit only contains valid information when tracing the s12xcpu accesses in detail mode. 0 stored information corresponds to free cycle 1 stored information does not correspond to free cycle 2 xsz access type indicator this bit indicates if the access was a byte or word size access. this bit only contains valid information when tracing xgate activity in detail mode. 0 word access 1 byte access 1 xrw read write indicator ?this bit indicates if the corresponding stored address corresponds to a read or write access. this bit only contains valid information when tracing xgate activity in detail mode. 0 write access 1 read access 0 xocf xgate opcode fetch indicator ?this bit indicates if the stored address corresponds to an opcode fetch cycle.this bit only contains valid information when tracing the s12xcpu accesses in detail mode. 0 stored information does not correspond to opcode fetch cycle 1 stored information corresponds to opcode fetch cycle table 22-43. cxinf field descriptions (continued) field description 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 818 freescale semiconductor reading the trace buffer while the s12xdbg module is armed will return invalid data and no shifting of the ram pointer will occur. 22.4.5.5 trace buffer reset state the trace buffer contents are not initialized by a system reset. thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. the dbgcnt bits are not cleared by a system reset. thus should a reset occur, the number of valid lines in the trace buffer is indicated by dbgcnt. the internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. generally debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. 22.4.6 tagging a tag follows program information as it advances through the instruction queue. when a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. each comparator control register features a tag bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. if a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. both s12xcpu and xgate opcodes can be tagged with the comparator register tag bits. using begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. if the transition is to the final state, tracing is started. only upon completion of the tracing session can a breakpoint be generated. similarly using mid trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. upon tracing completion the breakpoint is generated. using end trigger, when the tagged instruction is about to be executed and the next transition is to final state then a breakpoint is generated immediately, before the tagged instruction is carried out. r/w monitoring is not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. similarly access size (sz) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the size of access. thus these bits are ignored if tagged triggering is selected. when con?ured for range comparisons and tagging, the ranges are accurate only to word boundaries. s12x tagging is disabled when the bdm becomes active. xgate tagging is possible when the bdm is active. 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 819 22.4.6.1 external tagging using t a ghi and t a glo external tagging using the external t a ghi and t a glo pins can only be used to tag s12xcpu opcodes; tagging of xgate code using these pins is not possible. an external tag triggers the state sequencer into state0 when the tagged opcode reaches the execution stage of the instruction queue. the pins operate independently, thus the state of one pin does not affect the function of the other. external tagging is possible in emulation modes only. the presence of logic level 0 on either pin at the rising edge of the external clock (eclk) performs the function indicated in the table 22-44 . it is possible to tag both bytes of an instruction word. if a taghit occurs, a breakpoint can be generated as de?ed by the dbgbrk and bdm bits in dbgc1. each time t a ghi or t a glo are low on the rising edge of eclk, the old tag is replaced by a new one. 22.4.6.2 unconditional tagging function in emulation modes a low assertion of pe5/ t a glo/moda in the 7th or 8th bus cycle after reset enables the unconditional tagging function, allowing immediate tagging via t a ghi/ t a glo with breakpoint to bdm independent of the arm, bdm and dbgbrk bits. conversely these bits are not affected by unconditional tagging. the unconditional tagging function remains enabled until the next reset. this function allows an immediate entry to bdm in emulation modes before user code execution. the t a glo assertion must be in the 7th or 8th bus cycle following the end of reset, whereby the prior reset pin assertion lasts the full 192 bus cycles. 22.4.7 breakpoints there are several ways to generate breakpoints to the xgate and s12xcpu modules through xgate software breakpoint requests. from comparator channel triggers to ?al state. using software to write to the trig bit in the dbgc1 register. from taghits generated using the external t a ghi and t a glo pins. 22.4.7.1 xgate software breakpoints the xgate software breakpoint instruction brk can request an s12xcpu breakpoint, via the s12xdbg module. in this case, if the xgsbpe bit is set, the s12xdbg module immediately generates a forced breakpoint request to the s12xcpu, the state sequencer is returned to state0 and tracing, if active, is terminated. if con?ured for begin trigger and tracing has not yet been triggered from another source, the trace buffer contains no information. breakpoint requests from the xgate module do not depend upon the state of the dbgbrk or arm bits in dbgc1. they depend solely on the state of the xgsbpe table 22-44. tag pin function t a ghi t a glo tag 1 1 no tag 1 0 low byte 0 1 high byte 0 0 both bytes 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 820 freescale semiconductor and bdm bits. thus it is not necessary to arm the dbg module to use xgate software breakpoints to generate breakpoints in the s12xcpu program ?w, but it is necessary to set xgsbpe. furthermore, if a breakpoint to bdm is required, the bdm bit must also be set. when the xgate requests an s12xcpu breakpoint, the xgate program ?w stops by default, independent of the s12xdbg module. 22.4.7.2 breakpoints from internal comparator channel final state triggers breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. if con?ured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. if a tracing session is selected by the tsource bits, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 22-45 ). if no tracing session is selected, breakpoints are requested immediately. if the brk bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment. 22.4.7.3 breakpoints generated via the trig bit if a trig triggers occur, the final state is entered. tracing trigger alignment is de?ed by the talign bits. if a tracing session is selected by the tsource bits, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 22-45 ). if no tracing session is selected, breakpoints are requested immediately. trig breakpoints are possible even if the s12xdbg module is disarmed. table 22-45. breakpoint setup for both xgate and s12xcpu breakpoints brk talign dbgbrk[n] breakpoint alignment 0 00 0 fill trace buffer until trigger (no breakpoints ?keep running) 0 00 1 fill trace buffer until trigger, then breakpoint request occurs 0 01 0 start trace buffer at trigger (no breakpoints ?keep running) 0 01 1 start trace buffer at trigger a breakpoint request occurs when trace buffer is full 0 10 0 store a further 32 trace buffer line entries after trigger (no breakpoints ?keep running) 0 10 1 store a further 32 trace buffer line entries after trigger request breakpoint after the 32 further trace buffer entries 1 00,01,10 1 terminate tracing and generate breakpoint immediately on trigger 1 00,01,10 0 terminate tracing immediately on trigger x 11 x reserved 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 821 22.4.7.4 breakpoints via taghi or taglo pin taghits tagging using the external t a ghi/ t a glo pins always ends the session immediately at the tag hit. it is always end aligned, independent of internal channel trigger alignment con?uration. 22.4.7.5 s12xdbg breakpoint priorities xgate software breakpoints have the highest priority. active tracing sessions are terminated immediately. if a trig trigger occurs after begin or mid aligned tracing has already been triggered by a comparator instigated transition to final state, then trig no longer has an effect. when the associated tracing session is complete, the breakpoint occurs. similarly if a trig is followed by a subsequent trigger from a comparator channel, it has no effect, since tracing has already started. if a comparator tag hit occurs simultaneously with an external t a ghi/ t a glo hit, the state sequencer enters state0. taghi/taglo triggers are always end aligned, to end tracing immediately, independent of the tracing trigger alignment bits talign[1:0]. if a forced and tagged breakpoint coincide, the forced breakpoint occurs too late to prevent the tagged instruction being loaded into the execution unit. conversely the taghit is too late to prevent the breakpoint request in the dbg module. thus the s12xcpu suppresses the taghit although the tagged instruction is executed. considering the code example below the forced breakpoint is requested when the location counter is accessed. this is signalled to the s12xcpu when the next (tagged) instruction (nop) is already in the execution stage, thus the tagged instruction is carried out but the tagged breakpoint is suppressed. reading the pc with bdm read_pc returns $c008 c000 cf ff 00 start lds #$ff00 c003 a7 nop c004 72 70 08 inc counter ; forced breakpoint location = counter c007 a7 mark nop ; tagged opcode location = mark 00 bgnd [bdm firmware commands] c008 20 01 bra end ; 1st instruction on return from bdm 22.4.7.5.1 s12xdbg breakpoint priorities and bdm interfacing breakpoint operation is dependent on the state of the s12xbdm module. if the s12xbdm module is active, the s12xcpu is executing out of bdm ?mware and s12x breakpoints are disabled. in addition, while executing a bdm trace command, tagging into bdm is disabled. if bdm is not active, the breakpoint will give priority to bdm requests over swi requests if the breakpoint happens to coincide with a swi instruction in the users code. on returning from bdm, the swi from user code gets executed. table 22-46. breakpoint mapping summary dbgbrk[1] (dbgc1[3]) bdm bit (dbgc1[4]) bdm enabled bdm active s12x breakpoint mapping 0 x x x no breakpoint 1 0 x 0 breakpoint to swi 1 0 x 1 no breakpoint 4 .com u datasheet
chapter 22 s12x debug (s12xdbgv3) module MC9S12XHZ512 data sheet, rev. 1.02 822 freescale semiconductor bdm cannot be entered from a breakpoint unless the enable bit is set in the bdm. if entry to bdm via a bgnd instruction is attempted and the enable bit in the bdm is cleared, the s12xcpu actually executes the bdm ?mware code. it checks the enable and returns if enable is not set. if not serviced by the monitor then the breakpoint is re-asserted when the bdm returns to normal s12xcpu ?w. if the comparator register contents coincide with the swi/bdm vector address then an swi in user code and dbg breakpoint could occur simultaneously. the s12xcpu ensures that bdm requests have a higher priority than swi requests. returning from the bdm/swi service routine care must be taken to avoid re triggering a breakpoint. note when program control returns from a tagged breakpoint using an rti or bdm go command without program counter modi?ation it will return to the instruction whose tag generated the breakpoint. to avoid re triggering a breakpoint at the same location recon?ure the s12xdbg module in the swi routine, if con?ured for an swi breakpoint, or over the bdm interface by executing a trace command before the go to increment the program ?w past the tagged instruction. an xgate software breakpoint is forced immediately, the tracing session terminated and the xgate module execution stops. the user can thus determine if an xgate breakpoint has occurred by reading out the xgate program counter over the bdm interface. 1 1 0 x breakpoint to swi 1 1 1 0 breakpoint to bdm 1 1 1 1 no breakpoint table 22-46. breakpoint mapping summary 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 823 chapter 23 external bus interface (s12xebiv3) 23.1 introduction this document describes the functionality of the xebi block controlling the external bus interface. the xebi controls the functionality of a non-multiplexed external bus (a.k.a. ?xpansion bus? in relationship with the chip operation modes. dependent on the mode, the external bus can be used for data exchange with external memory, peripherals or pru, and provide visibility to the internal bus externally in combination with an emulator. 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 824 freescale semiconductor 23.1.1 glossary or terms 23.1.2 features the xebi includes the following features: output of up to 23-bit address bus and control signals to be used with a non-muxed external bus bidirectional 16-bit external data bus with option to disable upper half visibility of internal bus activity 23.1.3 modes of operation single-chip modes the external bus interface is not available in these modes. expanded modes address, data, and control signals are activated on the external bus in normal expanded mode and special test mode. emulation modes the external bus is activated to interface to an external tool for emulation of normal expanded mode or normal single-chip mode applications. bus clock system clock. refer to crg block guide. expanded modes normal expanded mode emulation single-chip mode emulation expanded mode special test mode single-chip modes normal single-chip mode special single-chip mode emulation modes emulation single-chip mode emulation expanded mode normal modes normal single-chip mode normal expanded mode special modes special single-chip mode special test mode ns normal single-chip mode ss special single-chip mode nx normal expanded mode es emulation single-chip mode ex emulation expanded mode st special test mode external resource addresses outside mcu prr port replacement registers pru port replacement unit emulmem external emulation memory access source cpu or bdm or xgate 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 825 refer to the s12x_mmc section for a detailed description of the mcu operating modes. 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 826 freescale semiconductor 23.1.4 block diagram figure 23-1 is a block diagram of the xebi with all related i/o signals. figure 23-1. xebi block diagram 23.2 external signal description the user is advised to refer to the soc section for port configuration and location of external bus signals. note the following external bus related signals are described in other sections: cs2, cs1, cs0 (chip selects) ?s12x_mmc section eclk, eclkx2 (free-running clocks) ?pim section t a ghi, t a glo (tag inputs) ?pim section, s12x_dbg section table 23-1 outlines the pin names and gives a brief description of their function. refer to the soc section and pim section for reset states of these pins and associated pull-ups or pull-downs. xebi addr[22:0] data[15:0] lstrb rw uds lds re we ewait acc[2:0] iqstat[3:0] ivd[15:0] 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 827 table 23-1. external system signals associated with xebi signal i 1 /o 1 all inputs are capable of reducing input threshold level ebi signal multiplex (t)ime 2 (f)unction 3 2 time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated time slot (in modes where applicable). 3 function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin depending on con?uration and reset state. description available in modes ns ss nx es ex st re o read enable, indicates external read access no no yes no no no addr[22:20] o t external address no no yes yes yes yes acc[2:0] o access source no no no yes yes yes addr[19:16] o t external address no no yes yes yes yes iqstat[3:0] o instruction queue status no no no yes yes yes addr[15:1] o t external address no no yes yes yes yes ivd[15:1] o internal visibility read data (ivis = 1) no no no yes yes yes addr0 o t f external address no no no yes yes yes ivd0 o internal visibility read data (ivis = 1) no no no yes yes yes uds o upper data select, indicates external access to the high byte data[15:8] no no yes no no no lstrb o f low strobe, indicates valid data on data[7:0] no no no yes yes yes lds o lower data select, indicates external access to the low byte data[7:0] no no yes no no no r w o f read/write, indicates the direction of internal data transfers no no no yes yes yes we o write enable, indicates external write access no no yes no no no data[15:8] i/o bidirectional data (even address) no no yes yes yes yes data[7:0] i/o bidirectional data (odd address) no no yes yes yes yes ew ait i external control for external bus access stretches (adding wait states) no no yes no yes no 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 828 freescale semiconductor 23.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the xebi . 23.3.1 module memory map the registers associated with the xebi block are shown in figure 23-2 . 23.3.2 register descriptions the following sub-sections provide a detailed description of each register and the individual register bits. all control bits can be written anytime, but this may have no effect on the related function in certain operating modes. this allows specific configurations to be set up before changing into the target operating mode. note depending on the operating mode an available function may be enabled, disabled or depend on the control register bit. reading the register bits will re?ct the status of related function only if the current operating mode allows user control. please refer the individual bit descriptions. register name bit 7 6 5 4 3 2 1 bit 0 0x0e ebictl0 r ithrs 0 hdbe asiz4 asiz3 asiz2 asiz1 asiz0 w 0x0f ebictl1 r ewaite 0000 exstr2 exstr1 exstr0 w = unimplemented or reserved figure 23-2. xebi register summary 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 829 23.3.2.1 external bus interface control register 0 (ebictl0) read: anytime. in emulation modes, read operations will return the data from the external bus, in all other modes, the data is read from this register. write: anytime. in emulation modes, write operations will also be directed to the external bus. this register controls input pin threshold level and determines the external address and data bus sizes in normal expanded mode. if not in use with the external bus interface, the related pins can be used for alternative functions. external bus is available as programmed in normal expanded mode and always full-sized in emulation modes and special test mode; function not available in single-chip modes. module base +0x000e (prr) 76543210 r ithrs 0 hdbe asiz4 asiz3 asiz2 asiz1 asiz0 w reset 0 0 1 11111 = unimplemented or reserved figure 23-3. external bus interface control register 0 (ebictl0) table 23-2. ebictl0 field descriptions field description 7 ithrs reduced input threshold ?this bit selects reduced input threshold on external data bus pins and speci? control input signals which are in use with the external bus interface in order to adapt to external devices with a 3.3 v, 5 v tolerant i/o. the reduced input threshold level takes effect depending on ithrs, the operating mode and the related enable signals of the ebi pin function as summarized in table 23-3 . 0 input threshold is at standard level on all pins 1 reduced input threshold level enabled on pins in use with the external bus interface 5 hdbe high data byte enable this bit enables the higher half of the 16-bit data bus. if disabled, only the lower 8-bit data bus can be used with the external bus interface. in this case the unused data pins and the data select signals ( uds and lds) are free to be used for alternative functions. 0 data[15:8], uds, and lds disabled 1 data[15:8], uds, and lds enabled 4? asiz[4:0] external address bus size these bits allow scalability of the external address bus. the programmed value corresponds to the number of available low-aligned address lines (refer to table 23-4 ). all address lines addr[22:0] start up as outputs after reset in expanded modes. this needs to be taken into consideration when using alternative functions on relevant pins in applications which utilize a reduced external address bus. 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 830 freescale semiconductor table 23-3. input threshold levels on external signals ithrs external signal ns ss nx es ex st 0 data[15:8] t a ghi, t a glo standard standard standard reduced reduced standard data[7:0] ewait standard standard 1 data[15:8] t a ghi, t a glo standard standard reduced if hdbe = 1 reduced reduced reduced data[7:0] reduced ew ait reduced if ewaite = 1 standard reduced if ewaite = 1 standard table 23-4. external address bus size asiz[4:0] available external address lines 00000 none 00001 uds 00010 addr1, uds 00011 addr[2:1], uds :: 10110 addr[21:1], uds 10111 : 11111 addr[22:1], uds 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 831 23.3.2.2 external bus interface control register 1 (ebictl1) read: anytime. in emulation modes, read operations will return the data from the external bus, in all other modes the data is read from this register. write: anytime. in emulation modes, write operations will also be directed to the external bus. this register is used to configure the external access stretch (wait) function. module base +0x000f (prr) 76543210 r ewaite 0000 exstr2 exstr1 exstr0 w reset 0 0 0 00111 = unimplemented or reserved figure 23-4. external bus interface control register 1 (ebictl1) table 23-5. ebictl1 field descriptions field description 7 ewaite external wait enable ?this bit enables the external access stretch function using the external ew ait input pin. enabling this feature may have effect on the minimum number of additional stretch cycles (refer to table 23-6 ). external wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function not available in all other operating modes. 0 external wait is disabled 1 external wait is enabled 2? exstr[2:0] external access stretch bits 2, 1, 0 ?this three bit ?ld determines the amount of additional clock stretch cycles on every access to the external address space as shown in table 23-6 . the minimum number of stretch cycles depends on the ewaite setting. stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function not available in all other operating modes. table 23-6. external access stretch bit de?ition exstr[2:0] number of stretch cycles ewaite = 0 ewaite = 1 000 1 cycle >= 2 cycles 001 2 cycles >= 2 cycles 010 3 cycles >= 3 cycles 011 4 cycles >= 4 cycles 100 5 cycles >= 5 cycles 101 6 cycles >= 6 cycles 110 7 cycles >= 7 cycles 111 8 cycles >= 8 cycles 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 832 freescale semiconductor 23.4 functional description this section describes the functions of the external bus interface. the availability of external signals and functions in relation to the operating mode is initially summarized and described in more detail in separate sub-sections. 23.4.1 operating modes and external bus properties a summary of the external bus interface functions for each operating mode is shown in table 23-7 . table 23-7. summary of functions properties (if enabled) single-chip modes expanded modes normal single-chip special single-chip normal expanded emulation single-chip emulation expanded special test timing properties prr access 1 1 incl. s12x_ebi registers 2 cycles read internal write internal 2 cycles read internal write internal 2 cycles read internal write internal 2 cycles read external write int & ext 2 cycles read external write int & ext 2 cycles read internal write internal internal access visible externally 1 cycle 1 cycle 1 cycle external address access and unimplemented area access 2 max. of 2 to 9 programmed cycles or n cycles of ext. wait 3 1 cycle max. of 2 to 9 programmed cycles or n cycles of ext. wait 3 1 cycle flash area address access 4 1 cycle 1 cycle 1 cycle signal properties bus signals addr[22:1] data[15:0] addr[22:20]/a cc[2:0] addr[19:16]/ iqstat[3:0] addr[15:0]/ ivd[15:0] data[15:0] addr[22:20]/a cc[2:0] addr[19:16]/ iqstat[3:0] addr[15:0]/ ivd[15:0] data[15:0] addr[22:0] data[15:0] data select signals (if 16-bit data bus) uds lds addr0 lstrb addr0 lstrb addr0 lstrb data direction signals re we r wr wr w chip selects cs0 cs1 cs2 cs3 cs0 cs1 cs2 cs3 cs0 cs1 cs2 cs3 external wait feature ew ait ew ait reduced input threshold enabled on refer to table 23-3 data[15:0] ew ait data[15:0] ew ait refer to table 23-3 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 833 23.4.2 internal visibility internal visibility allows the observation of the internal cpu address and data bus as well as the determination of the access source and the cpu pipe (queue) status through the external bus interface. internal visibility is always enabled in emulation single chip mode and emulation expanded mode. internal cpu accesses are made visible on the external bus interface except cpu execution of bdm firmware instructions. internal reads are made visible on addrx/ivdx (address and read data multiplexed, see table 23-10 to table 23-12 ), internal writes on addrx and datax (see table 23-13 to table 23-15 ). r w and lstrb show the type of access. external read data are also visible on ivdx. during ?o access?cycles r w is held in read position while lstrb is undetermined. all accesses which make use of the external bus interface are considered external accesses. 23.4.2.1 access source signals (acc) the access source can be determined from the external bus control signals acc[2:0] as shown in table 23-8 . 23.4.2.2 instruction queue status signals (iqstat) the cpu instruction queue status (execution-start and data-movement information) is brought out as iqstat[3:0] signals. for decoding of the iqstat values, refer to the s12x_cpu section. 23.4.2.3 internal visibility data (ivd) depending on the access size and alignment, either a word of read data is made visible on the address lines or only the related data byte will be presented in the eclk low phase. for details refer to table 23-9 . 2 refer to s12x_mmc section. 3 if ewaite = 1, the minimum number of external bus cycles is 3. 4 available only if con?ured appropriately by romon and eromon (refer to s12x_mmc section). table 23-8. determining access source from control signals acc[2:0] access description 000 repetition of previous access cycle 001 cpu access 010 bdm external access 011 xgate prr access 100 no access 1 1 denotes also cpu accesses to bdm ?mware and bdm registers (iqstatx are ?xxx?and r w = 1 in these cases) 101 cpu access error 110, 111 reserved 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 834 freescale semiconductor invalid ivd are brought out in case of non-cpu read accesses. 23.4.2.4 emulation modes timing a bus access lasts 1 eclk cycle. in case of a stretched external access (emulation expanded mode), up to an infinite amount of eclk cycles may be added. addrx values will only be shown in eclk high phases, while accx, iqstatx, and ivdx values will only be presented in eclk low phases. based on this multiplex timing, accx are only shown in the current (first) access cycle. iqstatx and (for read accesses) ivdx follow in the next cycle. if the access takes more than one bus cycle, accx display null (0x000) in the second and all following cycles of the access. iqstatx display null (0x0000) from the third until one cycle after the access to indicate continuation. the resulting timing pattern of the external bus signals is outlined in the following tables for read, write and interleaved read/write accesses. three examples represent different access lengths of 1, 2, and n? bus cycles. non-shaded bold entries denote all values related to access #0. table 23-9. ivd read data output access ivd[15:8] ivd[7:0] word read of data at an even and even+1 address ivd(even) ivd(even+1) word read of data at an odd and odd+1 internal ram address (misaligned) ivd(odd+1) ivd(odd) byte read of data at an even address ivd(even) addr[7:0] (rep.) byte read of data at an odd address addr[15:8] (rep.) ivd(odd) 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 835 the following terminology is used: ?ddr??value(addrx); small letters denote the logic values at the respective pins ???unde?ed output pin values ???tristate pins ???dependent on previous access (read or write); ivdx: ?vd?or ?? datax: ?ata?or ? 23.4.2.4.1 read access timing table 23-10. read access (1 cycle) access #0 access #1 bus cycle -> ... 123 ... eclk phase ... high low high low high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 1 acc 1 addr 2 acc 2 ... addr[19:16] / iqstat[3:0] ... iqstat -1 iqstat 0 iqstat 1 ... addr[15:0] / ivd[15:0] ... ? ivd 0 ivd 1 ... data[15:0] (internal read) ... ? zz z z z ... data[15:0] (external read) ... ? z data 0 z data 1 z ... r w ...111111... table 23-11. read access (2 cycles) access #0 access #1 bus cycle -> ... 123 ... eclk phase ... high low high low high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 0 000 addr 1 acc 1 ... addr[19:16] / iqstat[3:0] ... iqstat-1 iqstat 0 0000 ... addr[15:0] / ivd[15:0] ... ? x ivd 0 ... data[15:0] (internal read) ... ? zzzz z ... data[15:0] (external read) ... ? z z z data 0 z ... r w ...111111... table 23-12. read access (n? cycles) access #0 access #1 bus cycle -> ... 123 ... n ... eclk phase ... high low high low high low ... high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 0 000 addr 0 000 ... addr 1 acc 1 ... addr[19:16] / iqstat[3:0] ... iqstat-1 iqstat 0 0000 ... 0000 ... addr[15:0] / ivd[15:0] ... ? xx ... ivd 0 ... data[15:0] (internal read) ... ? zzzzz ... z z ... data[15:0] (external read) ... ? zzzzz ... data 0 z ... r w ...111111...11... 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 836 freescale semiconductor 23.4.2.4.2 write access timing table 23-13. write access (1 cycle) access #0 access #1 access #2 bus cycle -> ... 123 ... eclk phase ... high low high low high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 1 acc 1 addr 2 acc 2 ... addr[19:16] / iqstat[3:0] ... iqstat -1 iqstat 0 iqstat 1 ... addr[15:0] / ivd[15:0] ... ? x x ... data[15:0] (write) ... ? data 0 data 1 data 2 ... r w ...001111... table 23-14. write access (2 cycles) access #0 access #1 bus cycle -> ... 123 ... eclk phase ... high low high low high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 0 000 addr 1 acc 1 ... addr[19:16] / iqstat[3:0] ... iqstat-1 iqstat 0 0000 ... addr[15:0] / ivd[15:0] ... ? xx ... data[15:0] (write) ... ? data 0 x ... r w ...000011... table 23-15. write access (n? cycles) access #0 access #1 bus cycle -> ... 123 ... n ... eclk phase ... high low high low high low ... high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 0 000 addr 0 000 ... addr 1 acc 1 ... addr[19:16] / iqstat[3:0] ... iqstat-1 iqstat 0 0000 ... 0000 ... addr[15:0] / ivd[15:0] ... ? x x ... x ... data[15:0] (write) ... ? data 0 x ... r w ...000000...11... 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 837 23.4.2.4.3 read-write-read access timing 23.4.3 accesses to port replacement registers all read and write accesses to prr addresses take two bus clock cycles independent of the operating mode. if writing to these addresses in emulation modes, the access is directed to both, the internal register and the external resource while reads will be treated external. the xebi control registers also belong to this category. 23.4.4 stretched external bus accesses in order to allow fast internal bus cycles to coexist in a system with slower external resources, the xebi supports stretched external bus accesses (wait states). this feature is available in normal expanded mode and emulation expanded mode for accesses to all external addresses except emulation memory and prr. in these cases the fixed access times are 1 or 2 cycles, respectively. table 23-16. interleaved read-write-read accesses (1 cycle) access #0 access #1 access #2 bus cycle -> ... 123 ... eclk phase ... high low high low high low ... addr[22:20] / acc[2:0] ... addr 0 acc 0 addr 1 acc 1 addr 2 acc 2 ... addr[19:16] / iqstat[3:0] ... iqstat -1 iqstat 0 iqstat 1 ... addr[15:0] / ivd[15:0] ... ? ivd 0 x ... data[15:0] (internal read) ... ? zz (write) data 1 z ... data[15:0] (external read) ... ? z data 0 (write) data 1 z ... r w ...110011... 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 838 freescale semiconductor stretched accesses are controlled by: 1. exstr[2:0] bits in the ebictl1 register con?uring ?ed amount of stretch cycles 2. activation of the external wait feature by ewaite in ebictl1 register 3. assertion of the external ew ait signal when ewaite = 1 the exstr[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles. if the external wait feature is enabled, the minimum number of additional stretch cycles is 2. an arbitrary amount of stretch cycles can be added using the ewait input. ewait needs to be asserted at least for a minimal specified time window within an external access cycle for the internal logic to detect it and add a cycle (refer to electrical characteristics). holding it for additional cycles will cause the external bus access to be stretched accordingly. write accesses are stretched by holding the initiator in its current state for additional cycles as programmed and controlled by external wait after the data have been driven out on the external bus. this results in an extension of time the bus signals and the related control signals are valid externally. read data are not captured by the system in normal expanded mode until the specified setup time before the re rising edge. read data are not captured in emulation expanded mode until the specified setup time before the falling edge of eclk. in emulation expanded mode, accesses to the internal flash or the emulation memory (determined by eromon and romon bits; see s12x_mmc section for details) always take 1 cycle and stretching is not supported. in case the internal flash is taken out of the map in user applications, accesses are stretched as programmed and controlled by external wait. 23.4.5 data select and data direction signals the s12x_ebi supports byte and word accesses at any valid external address. the big endian system of the mcu is extended to the external bus; however, word accesses are restricted to even aligned addresses. the only exception is the visibility of misaligned word accesses to addresses in the internal ram as this module exclusively supports these kind of accesses in a single cycle. with the above restriction, a fixed relationship is implied between the address parity and the dedicated bus halves where the data are accessed: data[15:8] is related to even addresses and data[7:0] is related to odd addresses. in expanded modes the data access type is externally determined by a set of control signals, i.e., data select and data direction signals, as described below. the data select signals are not available if using the external bus interface with an 8-bit data bus. 23.4.5.1 normal expanded mode in normal expanded mode, the external signals re, we, uds, lds indicate the access type (read/write), data size and alignment of an external bus access ( table 23-17 ). 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 839 23.4.5.2 emulation modes and special test mode in emulation modes and special test mode, the external signals lstrb, r w, and addr0 indicate the access type (read/write), data size and alignment of an external bus access. misaligned accesses to the internal ram and misaligned xgate prr accesses in emulation modes are the only type of access that are able to produce lstrb = addr0 = 1. this is summarized in table 23-18 . table 23-17. access in normal expanded mode access re we uds lds data[15:8] data[7:0] i/o data(addr) i/o data(addr) word write of data on data[15:0] at an even and even+1 address 1 0 0 0 out data(even) out data(odd) byte write of data on data[7:0] at an odd address 1 0 1 0 in x out data(odd) byte write of data on data[15:8] at an even address 1 0 0 1 out data(even) in x word read of data on data[15:0] at an even and even+1 address 0 1 0 0 in data(even) in data(odd) byte read of data on data[7:0] at an odd address 0 1 1 0 in x in data(odd) byte read of data on data[15:8] at an even address 0 1 0 1 in data(even) in x indicates no access 1 1 1 1 in x in x unimplemented 1 1 1 0 in x in x 11 0 1 in x in x table 23-18. access in emulation modes and special test mode access r w lstrb addr0 data[15:8] data[7:0] i/o data(addr) i/o data(addr) word write of data on data[15:0] at an even and even+1 address 0 0 0 out data(even) out data(odd) byte write of data on data[7:0] at an odd address 0 0 1 in x out data(odd) byte write of data on data[15:8] at an even address 0 1 0 out data(odd) in x word write at an odd and odd+1 internal ram address (misaligned ?only in emulation modes) 0 1 1 out data(odd+1) out data(odd) word read of data on data[15:0] at an even and even+1 address 1 0 0 in data(even) in data(even+1) byte read of data on data[7:0] at an odd address 1 0 1 in x in data(odd) byte read of data on data[15:8] at an even address 1 1 0 in data(even) in x word read at an odd and odd+1 internal ram address (misaligned - only in emulation modes) 1 1 1 in data(odd+1) in data(odd) 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 840 freescale semiconductor 23.4.6 low-power options the xebi does not support any user-controlled options for reducing power consumption. 23.4.6.1 run mode the xebi does not support any options for reducing power in run mode. power consumption is reduced in single-chip modes due to the absence of the external bus interface. operation in expanded modes results in a higher power consumption, however any unnecessary toggling of external bus signals is reduced to the lowest indispensable activity by holding the previous states between external accesses. 23.4.6.2 wait mode the xebi does not support any options for reducing power in wait mode. 23.4.6.3 stop mode the xebi will cease to function in stop mode. 23.5 initialization/application information this section describes the external bus interface usage and timing. typical customer operating modes are normal expanded mode and emulation modes, specifically to be used in emulator applications. taking the availability of the external wait feature into account the use cases are divided into four scenarios: normal expanded mode external wait feature disabled external wait feature enabled emulation modes emulation single-chip mode (without wait states) emulation expanded mode (with optional access stretching) normal single-chip mode and special single-chip mode do not have an external bus. special test mode is used for factory test only. therefore, these modes are omitted here. all timing diagrams referred to throughout this section are available in the electrical characteristics appendix of the soc section. 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 841 23.5.1 normal expanded mode this mode allows interfacing to external memories or peripherals which are available in the commercial market. in these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access. 23.5.1.1 example 1a: external wait feature disabled the first example of bus timing of an external read and write access with the external wait feature disabled is shown in figure ?xample 1a: normal expanded mode ?read followed by write the associated supply voltage dependent timing are numbers given in table ?xample 1a: normal expanded mode timing v dd5 = 5.0 v (ewaite = 0) table ?xample 1a: normal expanded mode timing v dd5 = 3.0 v (ewaite = 0) systems designed this way rely on the internal programmable access stretching. these systems have predictable external memory access times. the additional stretch time can be programmed up to 8 cycles to provide longer access times. 23.5.1.2 example 1b: external wait feature enabled the external wait operation is shown in this example. it can be used to exceed the amount of stretch cycles over the programmed number in exstr[2:0]. the feature must be enabled by writing ewaite = 1. if the ewait signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. if ewait is asserted within the predefined time window during the access it will be strobed active and another stretch cycle is added. if strobed inactive, the next cycle will be the last cycle before the access is finished. ewait can be held asserted as long as desired to stretch the access. an access with 1 cycle stretch by ewait assertion is shown in figure ?xample 1b: normal expanded mode ?stretched read access figure ?xample 1b: normal expanded mode ?stretched write access the associated timing numbers for both operations are given in table ?xample 1b: normal expanded mode timing v dd5 = 5.0 v (ewaite = 1) table ?xample 1b: normal expanded mode timing v dd5 = 3.0 v (ewaite = 1) it is recommended to use the free-running clock (eclk) at the fastest rate (bus clock rate) to synchronize the ewait input signal. 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 842 freescale semiconductor 23.5.2 emulation modes in emulation mode applications, the development systems use a custom pru device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. accesses to a set of registers controlling the related ports in normal modes (refer to soc section) are directed to the external bus in emulation modes which are substituted by prr as part of the pru. accesses to these registers take a constant time of 2 cycles. depending on the setting of romon and eromon (refer to s12x_mmc section), the program code can be executed from internal memory or an optional external emulation memory (emulmem). no wait state operation (stretching) of the external bus access is done in emulation modes when accessing internal memory or emulation memory addresses. in both modes observation of the internal operation is supported through the external bus (internal visibility). 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 843 23.5.2.1 example 2a: emulation single-chip mode this mode is used for emulation systems in which the target application is operating in normal single-chip mode. figure 23-5 shows the pru connection with the available external bus signals in an emulator application. figure 23-5. application in emulation single-chip mode the timing diagram for this operation is shown in: figure ?xample 2a: emulation single-chip mode ?read followed by write the associated timing numbers are given in: table ?xample 2a: emulation single-chip mode timing (ewaite = 0) timing considerations: signals muxed with address lines addrx, i.e., ivdx, iqstatx and accx, have the same timing. lstrb has the same timing as r w. eclkx2 rising edges have the same timing as eclk edges. the timing for accesses to pru registers, which take 2 cycles to complete, is the same as the timing for an external non-prr access with 1 cycle of stretch as shown in example 2b. s12x_ebi addr[22:0]/ivd[15:0] data[15:0] eclk eclkx2 lstrb rw addr[22:20]/acc[2:0] addr[19:16]/ prr ports pru iqstat[3:0] emulmem emulator 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 844 freescale semiconductor 23.5.2.2 example 2b: emulation expanded mode this mode is used for emulation systems in which the target application is operating in normal expanded mode. if the external bus is used with a pru, the external device rebuilds the data select and data direction signals uds, lds, re, and we from the addr0, lstrb, and r w signals. figure 23-6 shows the pru connection with the available external bus signals in an emulator application. figure 23-6. application in emulation expanded mode the timings of accesses with 1 stretch cycle are shown in figure ?xample 2b: emulation expanded mode ?read with 1 stretch cycle figure ?xample 2b: emulation expanded mode ?write with 1 stretch cycle the associated timing numbers are given in table ?xample 2b: emulation expanded mode timing v dd5 = 5.0 v (ewaite = 0)?(this also includes examples for alternative settings of 2 and 3 additional stretch cycles) timing considerations: if no stretch cycle is added, the timing is the same as in emulation single-chip mode. s12x_ebi addr[22:0]/ivd[15:0] data[15:0] eclk eclkx2 lstrb rw uds lds re we addr[22:20]/acc[2:0] addr[19:16]/ cs[2:0] prr ports pru iqstat[3:0] emulmem emulator ewait 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 845 4 .com u datasheet
chapter 23 external bus interface (s12xebiv3) MC9S12XHZ512 data sheet, rev. 1.02 846 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 847 chapter 24 interrupt (s12xintv1) 24.1 introduction the xint module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the cpu or the xgate module. the xint module supports: i bit and x bit maskable interrupt requests a non-maskable unimplemented opcode trap a non-maskable software interrupt (swi) or background debug mode request a spurious interrupt vector request three system reset vector requests each of the i bit maskable interrupt requests can be assigned to one of seven priority levels supporting a ?xible priority scheme. for interrupt requests that are con?ured to be handled by the cpu, the priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed. interrupt requests con?ured to be handled by the xgate module cannot be nested because the xgate module cannot be interrupted while processing. note the hprio register and functionality of the xint module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme. 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 848 freescale semiconductor 24.1.1 glossary the following terms and abbreviations are used in the document. 24.1.2 features interrupt vector base register (ivbr) one spurious interrupt vector (at address vector base 1 + 0x0010). 2?13 i bit maskable interrupt vector requests (at addresses vector base + 0x0012?x00f2). each i bit maskable interrupt request has a con?urable priority level and can be con?ured to be handled by either the cpu or the xgate module 2 . i bit maskable interrupts can be nested, depending on their priority levels. one x bit maskable interrupt vector request (at address vector base + 0x00f4). one non-maskable software interrupt request (swi) or background debug mode vector request (at address vector base + 0x00f6). one non-maskable unimplemented opcode trap (trap) vector (at address vector base + 0x00f8). three system reset vectors (at addresses 0xfffa?xfffe). determines the highest priority dma and interrupt vector requests, drives the vector to the xgate module or to the bus on cpu request, respectively. wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever xirq is asserted, even if x interrupt is masked. xgate can wake up and execute code, even with the cpu remaining in stop or wait mode. 24.1.3 modes of operation run mode this is the basic mode of operation. table 24-1. terminology term meaning ccr condition code register (in the s12x cpu) dma direct memory access int interrupt ipl interrupt processing level isr interrupt service routine mcu micro-controller unit xgate please refer to the "xgate block guide" irq refers to the interrupt request associated with the irq pin xirq refers to the interrupt request associated with the xirq pin 1. the vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (ivbr, used as upper byte) and 0x00 (used as lower byte). 2. the irq interrupt can only be handled by the cpu 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 849 wait mode in wait mode, the xint module is frozen. it is however capable of either waking up the cpu if an interrupt occurs or waking up the xgate if an xgate request occurs. please refer to section 24.5.3, ?ake up from stop or wait mode for details. stop mode in stop mode, the xint module is frozen. it is however capable of either waking up the cpu if an interrupt occurs or waking up the xgate if an xgate request occurs. please refer to section 24.5.3, ?ake up from stop or wait mode for details. freeze mode (bdm active) in freeze mode (bdm active), the interrupt vector base register is overridden internally. please refer to section 24.3.1.1, ?nterrupt vector base register (ivbr) for details. 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 850 freescale semiconductor 24.1.4 block diagram figure 24-1 shows a block diagram of the xint module. figure 24-1. xint block diagram wake up current rqst ivbr one set per channel xgate interrupts xgate requests interrupt requests interrupt requests cpu vector address new ipl ipl (up to 112 channels) rqst dma request route, priolvln priority level = bits from the channel con?uration in the associated con?uration register int_xgprio = xgate interrupt priority ivbr = interrupt vector base ipl = interrupt processing level priolvl0 priolvl1 priolvl2 int_xgprio peripheral vector id to xgate module priority decoder to cpu priority decoder non i bit maskable channels wake up xgate irq channel 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 851 24.2 external signal description the xint module has no external signals. 24.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the xint. 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 852 freescale semiconductor 24.3.1 register descriptions this section describes in address order all the xint registers and their individual bits. offset address register name bit 7 654321 bit 0 0x1 ivbr r ivb_addr[7:0] w 0x6 int_xgprio r 00000 xilvl[2:0] w 0x7 int_cfaddr r int_cfaddr[7:4] 0000 w 0x8 int_cfdata0 r rqst 0000 priolvl[2:0] w 0x9 int_cfdata1 r rqst 0000 priolvl[2:0] w 0xa int_cfdata2 r rqst 0000 priolvl[2:0] w 0xb int_cfdata3 r rqst 0000 priolvl[2:0] w 0xc int_cfdata4 r rqst 0000 priolvl[2:0] w 0xd int_cfdata5 r rqst 0000 priolvl[2:0] w 0xe int_cfdata6 r rqst 0000 priolvl[2:0] w 0xf int_cfdata7 r rqst 0000 priolvl[2:0] w = unimplemented or reserved figure 24-2. xint register summary 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 853 24.3.1.1 interrupt vector base register (ivbr) read: anytime write: anytime offset address: 0x1 76543210 r ivb_addr[7:0] w reset 1 1 1 11111 figure 24-3. interrupt vector base register (ivbr) table 24-2. ivbr field descriptions field description 7? ivb_addr[7:0] interrupt vector base address bits these bits represent the upper byte of all vector addresses. out of reset these bits are set to 0xff (i.e., vectors are located at 0xff10?xfffe) to ensure compatibility to hcs12. note: a system reset will initialize the interrupt vector base register with ?xff before it is used to determine the reset vector address. therefore, changing the ivbr has no effect on the location of the three reset vectors (0xfffa?xfffe). note: if the bdm is active (i.e., the cpu is in the process of executing bdm ?mware code), the contents of ivbr are ignored and the upper byte of the vector address is ?ed as ?xff? 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 854 freescale semiconductor 24.3.1.2 xgate interrupt priority con?uration register (int_xgprio) read: anytime write: anytime offset address: 0x6 76543210 r00000 xilvl[2:0] w reset 0 0 0 00001 = unimplemented or reserved figure 24-4. xgate interrupt priority con?uration register (int_xgprio) table 24-3. int_xgprio field descriptions field description 2? xilvl[2:0] xgate interrupt priority level the xilvl[2:0] bits configure the shared interrupt level of the dma interrupts coming from the xgate module. out of reset the priority is set to the lowest active level (??. table 24-4. xgate interrupt priority levels priority xilvl2 xilvl1 xilvl0 meaning 0 0 0 interrupt request is disabled low 0 0 1 priority level 1 0 1 0 priority level 2 0 1 1 priority level 3 1 0 0 priority level 4 1 0 1 priority level 5 1 1 0 priority level 6 high 1 1 1 priority level 7 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 855 24.3.1.3 interrupt request con?uration address register (int_cfaddr) read: anytime write: anytime offset address: 0x7 76543210 r int_cfaddr[7:4] 0000 w reset 0 0 0 10000 = unimplemented or reserved figure 24-5. interrupt con?uration address register (int_cfaddr) table 24-5. int_cfaddr field descriptions field description 7? int_cfaddr[7:4] interrupt request con?uration data register select bits ?these bits determine which of the 128 con?uration data registers are accessible in the 8 register window at int_cfdata0?. the hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the interrupt vector, i.e., writing 0xe0 to this register selects the con?uration data register block for the 8 interrupt vector requests starting with vector (vector base + 0x00e0) to be accessible as int_cfdata0?. note: writing all 0s selects non-existing con?uration registers. in this case write accesses to int_cfdata0? will be ignored and read accesses will return all 0. 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 856 freescale semiconductor 24.3.1.4 interrupt request con?uration data registers (int_cfdata0?) the eight register window visible at addresses int_cfdata0? contains the con?uration data for the block of eight interrupt requests (out of 128) selected by the interrupt con?uration address register (int_cfaddr) in ascending order. int_cfdata0 represents the interrupt con?uration data register of the vector with the lowest address in this block, while int_cfdata7 represents the interrupt con?uration data register of the vector with the highest address, respectively. offset address: 0x8 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-6. interrupt request con?uration data register 0 (int_cfdata0) offset address: 0x9 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-7. interrupt request con?uration data register 1 (int_cfdata1) offset address: 0xa 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-8. interrupt request con?uration data register 2 (int_cfdata2) offset address: 0xb 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-9. interrupt request con?uration data register 3 (int_cfdata3) 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 857 read: anytime write: anytime offset address: 0xc 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-10. interrupt request con?uration data register 4 (int_cfdata4) offset address: 0xd 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-11. interrupt request con?uration data register 5 (int_cfdata5) offset address: 0xe 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-12. interrupt request con?uration data register 6 (int_cfdata6) offset address: 0xf 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 1 1 please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 24-13. interrupt request con?uration data register 7 (int_cfdata7) 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 858 freescale semiconductor table 24-6. int_cfdata0? field descriptions field description 7 rqst xgate request enable this bit determines if the associated interrupt request is handled by the cpu or by the xgate module. 0 interrupt request is handled by the cpu 1 interrupt request is handled by the xgate module note: the irq interrupt cannot be handled by the xgate module. for this reason, the con?uration register for vector (vector base + 0x00f2) = irq vector address) does not contain a rqst bit. writing a 1 to the location of the rqst bit in this register will be ignored and a read access will return 0. 2? priolvl[2:0] interrupt request priority level bits the priolvl[2:0] bits con?ure the interrupt request priority level of the associated interrupt request. out of reset all interrupt requests are enabled at the lowest active level (?? to provide backwards compatibility with previous hcs12 interrupt controllers. please also refer to table 24-7 for available interrupt request priority levels. note: write accesses to con?uration data registers of unused interrupt channels will be ignored and read accesses will return all 0. for information about what interrupt channels are used in a speci? mcu, please refer to the device user guide of that mcu. note: when vectors (vector base + 0x00f0?x00fe) are selected by writing 0xf0 to int_cfaddr, writes to int_cfdata2? (0x00f4?x00fe) will be ignored and read accesses will return all 0s. the corresponding vectors do not have con?uration data registers associated with them. note: write accesses to the con?uration register for the spurious interrupt vector request (vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the cpu, priolvl = 7). table 24-7. interrupt priority levels priority priolvl2 priolvl1 priolvl0 meaning 0 0 0 interrupt request is disabled low 0 0 1 priority level 1 0 1 0 priority level 2 0 1 1 priority level 3 1 0 0 priority level 4 1 0 1 priority level 5 1 1 0 priority level 6 high 1 1 1 priority level 7 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 859 24.4 functional description the xint module processes all exception requests to be serviced by the cpu module. these exceptions include interrupt vector requests and reset vector requests. each of these exception types and their overall priority level is discussed in the subsections below. 24.4.1 s12x exception requests the cpu handles both reset requests and interrupt requests. the xint contains registers to con?ure the priority level of each i bit maskable interrupt request which can be used to implement an interrupt priority scheme. this also includes the possibility to nest interrupt requests. a priority decoder is used to evaluate the priority of a pending interrupt request. 24.4.2 interrupt prioritization after system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00f2) are enabled, are set up to be handled by the cpu and have a pre-con?ured priority level of 1. the exception to this rule is the spurious interrupt vector request at (vector base + 0x0010) which cannot be disabled, is always handled by the cpu and has a xed priority level of 7. a priority level of 0 effectively disables the associated interrupt request. if more than one interrupt request is con?ured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. the following conditions must be met for an i bit maskable interrupt request to be processed. 1. the local interrupt enabled bit in the peripheral module must be set. 2. the setup in the con?uration register associated with the interrupt request channel must meet the following conditions: a) the xgate request enable bit must be 0 to have the cpu handle the interrupt request. b) the priority level must be set to non zero. c) the priority level must be greater than the current interrupt processing level in the condition code register (ccr) of the cpu (priolvl[2:0] > ipl[2:0]). 3. the i bit in the condition code register (ccr) of the cpu must be cleared. 4. there is no swi, trap, or xirq request pending. note all non i bit maskable interrupt requests always have higher priority than i bit maskable interrupt requests. if an i bit maskable interrupt request is interrupted by a non i bit maskable interrupt request, the currently active interrupt processing level (ipl) remains unaffected. it is possible to nest non i bit maskable interrupt requests, e.g., by nesting swi or trap calls. 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 860 freescale semiconductor 24.4.2.1 interrupt priority stack the current interrupt processing level (ipl) is stored in the condition code register (ccr) of the cpu. this way the current ipl is automatically pushed to the stack by the standard interrupt stacking procedure. the new ipl is copied to the ccr from the priority level of the highest priority active interrupt request channel which is con?ured to be handled by the cpu. the copying takes place when the interrupt vector is fetched. the previous ipl is automatically restored by executing the rti instruction. 24.4.3 xgate requests the xint module processes all exception requests to be serviced by the xgate module. the overall priority level of those exceptions is discussed in the subsections below. 24.4.3.1 xgate request prioritization an interrupt request channel is con?ured to be handled by the xgate module, if the rqst bit of the associated con?uration register is set to 1 (please refer to section 24.3.1.4, ?nterrupt request con?uration data registers (int_cfdata0?) ). the priority level setting (priolvl) for this channel becomes the dma priority which will be used to determine the highest priority dma request to be serviced next by the xgate module. additionally, dma interrupts may be raised by the xgate module by setting one or more of the xgate channel interrupt ?gs (using the sif instruction). this will result in an cpu interrupt with vector address vector base + (2 * channel id number), where the channel id number corresponds to the highest set channel interrupt ?g, if the xgie and channel rqst bits are set. the shared interrupt priority for the dma interrupt requests is taken from the xgate interrupt priority con?uration register (please refer to section 24.3.1.2, ?gate interrupt priority con?uration register (int_xgprio) ). if more than one dma interrupt request channel becomes active at the same time, the channel with the highest vector address wins the prioritization. 24.4.4 priority decoders the xint module contains priority decoders to determine the priority for all interrupt requests pending for the respective target. there are two priority decoders, one for each interrupt request target (cpu, xgate module). the function of both priority decoders is basically the same with one exception: the priority decoder for the xgate module does not take the current interrupt processing level into account because xgate requests cannot be nested. because the vector is not supplied until the cpu requests it, it is possible that a higher priority interrupt request could override the original exception that caused the cpu to request the vector. in this case, the cpu will receive the highest priority vector and the system will process this exception instead of the original request. 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 861 if the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the cpu will default to that of the spurious interrupt vector. note care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)). 24.4.5 reset exception requests the xint supports three system reset exception request types (please refer to crg for details): 1. pin reset, power-on reset, low-voltage reset, or illegal address reset 2. clock monitor reset request 3. cop watchdog reset request 24.4.6 exception priority the priority (from highest to lowest) and address of all exception vectors issued by the xint upon request by the cpu is shown in table 24-8 . table 24-8. exception vector map and priority vector address 1 1 16 bits vector address based source 0xfffe pin reset, power-on reset, low-voltage reset, illegal address reset 0xfffc clock monitor reset 0xfffa cop watchdog reset (vector base + 0x00f8) unimplemented opcode trap (vector base + 0x00f6) software interrupt instruction (swi) or bdm vector request (vector base + 0x00f4) xirq interrupt request (vector base + 0x00f2) irq interrupt request (vector base + 0x00f0?x0012) device speci? i bit maskable interrupt sources (priority determined by the associated con?uration registers, in descending order) (vector base + 0x0010) spurious interrupt 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 862 freescale semiconductor 24.5 initialization/application information 24.5.1 initialization after system reset, software should: initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xff10?xfff9). initialize the interrupt processing level con?uration data registers (int_cfaddr, int_cfdata0?) for all interrupt vector requests with the desired priority levels and the request target (cpu or xgate module). it might be a good idea to disable unused interrupt requests. if the xgate module is used, setup the xgate interrupt priority register (int_xgprio) and con?ure the xgate module (please refer the xgate block guide for details). enable i maskable interrupts by clearing the i bit in the ccr. enable the x maskable interrupt by clearing the x bit in the ccr (if required). 24.5.2 interrupt nesting the interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the i bit maskable interrupt requests handled by the cpu. i bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested i bit maskable interrupt requests at a time (refer to figure 24-14 for an example using up to three nested interrupt requests). i bit maskable interrupt requests cannot be interrupted by other i bit maskable interrupt requests per default. in order to make an interrupt service routine (isr) interruptible, the isr must explicitly clear the i bit in the ccr (cli). after clearing the i bit, i bit maskable interrupt requests with higher priority can interrupt the current isr. an isr of an interruptible i bit maskable interrupt request could basically look like this: service interrupt, e.g., clear interrupt ?gs, copy data, etc. clear i bit in the ccr by executing the instruction cli (thus allowing interrupt requests with higher priority) process data return from interrupt by executing the instruction rti 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 863 figure 24-14. interrupt processing example 24.5.3 wake up from stop or wait mode 24.5.3.1 cpu wake up from stop or wait mode every i bit maskable interrupt request which is con?ured to be handled by the cpu is capable of waking the mcu from stop or wait mode. to determine whether an i bit maskable interrupts is quali?d to wake up the cpu or not, the same settings as in normal run mode are applied during stop or wait mode: if the i bit in the ccr is set, all i bit maskable interrupts are masked from waking up the mcu. an i bit maskable interrupt is ignored if it is con?ured to a priority level below or equal to the current ipl in ccr. i bit maskable interrupt requests which are con?ured to be handled by the xgate are not capable of waking up the cpu. an xirq request can wake up the mcu from stop or wait mode at anytime, even if the x bit in ccr is set. 24.5.3.2 xgate wake up from stop or wait mode interrupt request channels which are con?ured to be handled by the xgate are capable of waking up the xgate. interrupt request channels handled by the xgate do not affect the state of the cpu. 0 reset 4 0 7 6 5 4 3 2 1 0 l4 7 0 4 l1 (pending) l7 l3 (pending) rti 4 0 3 0 rti rti 1 0 0 rti stacked ipl processing levels ipl in ccr 4 .com u datasheet
chapter 24 interrupt (s12xintv1) MC9S12XHZ512 data sheet, rev. 1.02 864 freescale semiconductor 4 .com u datasheet
MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 865 chapter 25 memory mapping control (s12xmmcv3) 25.1 introduction this section describes the functionality of the module mapping control (mmc) sub-block of the s12x platform. the block diagram of the mmc is shown in figure 25-1 . the mmc module controls the multi-master priority accesses, the selection of internal resources and external space. internal buses, including internal memories and peripherals, are controlled in this module. the local address space for each master is translated to a global memory space. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 866 freescale semiconductor 25.1.1 terminology 25.1.2 features the main features of this block are: paging capability to support a global 8 mbytes memory address space bus arbitration between the masters cpu, bdm, flexray and xgate table 25-1. acronyms and abbreviations logic level ? voltage that corresponds to boolean true state logic level ? voltage that corresponds to boolean false state 0x represents hexadecimal number x represents logic level don? care byte 8-bit data word 16-bit data local address based on the 64 kbytes memory space (16-bit address) global address based on the 8 mbytes memory space (23-bit address) aligned address address on even boundary mis-aligned address address on odd boundary bus clock system clock. refer to crg block guide. expanded modes normal expanded mode emulation single-chip mode emulation expanded mode special test mode single-chip modes normal single-chip mode special single-chip mode emulation modes emulation single-chip mode emulation expanded mode normal modes normal single-chip mode normal expanded mode special modes special single-chip mode special test mode ns normal single-chip mode ss special single-chip mode nx normal expanded mode es emulation single-chip mode ex emulation expanded mode st special test mode unimplemented areas areas which are accessible by the pages (rpage,ppage,epage) and not implemented external space area which is accessible in the global address range 14_0000 to 3f_ffff external resource resources (emulator, application) connected to the mcu via the external bus on expanded modes (unimplemented areas and external space) prr port replacement registers pru port replacement unit located on the emulator side mcu microcontroller unit nvm non-volatile memory; flash eeprom or rom flexray flexray ip integration module 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 867 simultaneous accesses to different resources 1 (internal, external, and peripherals) (see figure 25-1 ) resolution of target bus access collision access restriction control from masters to some targets (e.g., ram write access protection for user speci?d areas) mcu operation mode control mcu security control separate memory map schemes for each master cpu, bdm, flexray and xgate rom control bits to enable the on-chip flash or rom selection port replacement registers access control generation of system reset when cpu accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 25.1.3 s12x memory mapping the s12x architecture implements a number of memory mapping schemes including a cpu 8 mbyte global map, de?ed using a global page (gpage) register and dedicated 23-bit address load/store instructions. a bdm 8 mbyte global map, de?ed using a global page (bdmgpr) register and dedicated 23-bit address load/store instructions. flexray 8 mbyte global map. a (cpu or bdm) 64 kbyte local map, de?ed using speci? resource page (rpage, epage and ppage) registers and the default instruction set. the 64 kbytes visible at any instant can be considered as the local map accessed by the 16-bit (cpu or bdm) address. the xgate 64 kbyte local map. the mmc module performs translation of the different memory mapping schemes to the speci? global (physical) memory implementation. 25.1.4 modes of operation this subsection lists and brie? describes all operating modes supported by the mmc. 25.1.4.1 power saving modes run mode mmc is functional during normal run mode. wait mode mmc is functional during wait mode. stop mode mmc is inactive during stop mode. 1. resources are also called targets. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 868 freescale semiconductor 25.1.4.2 functional modes single chip modes in normal and special single chip mode the internal memory is used. external bus is not active. expanded modes address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus. access to internal resources will not cause activity on the external bus. emulation modes external bus is active to emulate, via an external tool, the normal expanded or the normal single chip mode. 25.1.5 block diagram figure 25-1 1 shows a block diagram of the mmc. figure 25-1. mmc block diagram 25.2 external signal description the user is advised to refer to the soc guide for port con?uration and location of external bus signals. some pins may not be bonded out in all implementations. table 25-2 and table 25-3 outline the pin names and functions. it also provides a brief description of their operation. 1. doted blocks and lines are optional. please refer to the device user guide for their availlibilities. peripherals flash xgate cpu bdm target bus controller dbg eeprom ebi mmc address decoder & priority ram flexray 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 869 table 25-2. external input signals associated with the mmc signal i/o description availability modc i mode input latched after reset (active low) modb i mode input latched after reset (active low) moda i mode input latched after reset (active low) eromctl i erom control input latched after reset (active low) romctl i rom control input latched after reset (active low) table 25-3. external output signals associated with the mmc signal i/o description available in modes ns ss nx es ex st cs0 o chip select line 0 (see table 25-4 ) cs1 o chip select line 1 cs2 o chip select line 2 cs3 o chip select line 3 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 870 freescale semiconductor 25.3 memory map and registers 25.3.1 module memory map a summary of the registers associated with the mmc block is shown in figure 25-2 . detailed descriptions of the registers and bits are given in the subsections that follow. address register name bit 7 654321 bit 0 0x000a mmcctl0 r 0000 cs3e cs2e cs1e cs0e w 0x000b mode r modc modb moda 00000 w 0x0010 gpage r 0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r 00000000 w 0x0013 mmcctl1 r 00000 eromon romhm romon w 0x0014 reserved r 00000000 w 0x0015 reserved r 00000000 w 0x0016 rpage r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w 0x0017 epage r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w 0x0018 ramfrl r frl7 frl6 frl5 frl4 frl3 frl2 frl1 frl0 w 0x0019 ramfru r fru7 fru6 fru5 fru4 fru3 fru2 fru1 fru0 w = unimplemented or reserved figure 25-2. mmc register summary 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 871 25.3.2 register descriptions 25.3.2.1 mmc control register (mmcctl0) read: anytime. in emulation modes read operations will return the data from the external bus. in all other modes the data is read from this register. write: anytime. in emulation modes write operations will also be directed to the external bus. 0x0030 ppage r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0031 reserved r 00000000 w 0x011c ramwpc r rpwe 000 frcpu frxg avie avif w 0x011d ramxgu r 1 xgu6 xgu5 xgu4 xgu3 xgu2 xgu1 xgu0 w 0x011e ramshl r 1 shl6 shl5 shl4 shl3 shl2 shl1 shl0 w 0x011f ramshu r 1 shu6 shu5 shu4 shu3 shu2 shu1 shu0 w address: 0x000a prr 76543210 r0000 cs3e cs2e cs1e cs0e w reset 0000000 r omon 1 1. romon is bit[0] of the register mmctl1 (see figure 25-10 ) = unimplemented or reserved figure 25-3. mmc control register (mmcctl0) table 25-4. chip selects function activity register bit chip modes ns ss nx es ex st cs3e, cs2e, cs1e, cs0e disabled 1 disabled enabled 2 disabled enabled enabled address register name bit 7 654321 bit 0 = unimplemented or reserved figure 25-2. mmc register summary 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 872 freescale semiconductor the mmcctl0 register is used to control external bus functions, i.e., availability of chip selects. caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. 1 disabled: feature always inactive. 2 enabled: activity is controlled by the appropriate register bit value. table 25-5. mmcctl0 field descriptions field description 3? cs[3:0]e chip select enables each of these bits enables one of the external chip selects cs3, cs2, cs1, and cs0 outputs which are asserted during accesses to speci? external addresses. the associated global address ranges are shown in table 25-6 and table 25-24 and figure 25-23 . chip selects are only active if enabled in normal expanded mode, emulation expanded mode and special test mode. the function disabled in all other operating modes. 0 chip select is disabled 1 chip select is enabled table 25-6. chip select signals global address range asserted signal 0x00_0800?x0f_ffff cs3 0x10_0000?x1f_ffff cs2 0x20_0000?x3f_ffff cs1 0x40_0000?x7f_ffff cs0 1 1 when the internal nvm is enabled (see romon in section 25.3.2.5, ?mc control register (mmcctl1) ) the cs0 is not asserted in the space occupied by this on-chip memory block. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 873 25.3.2.2 mode register (mode) read: anytime. in emulation modes read operations will return the data read from the external bus. in all other modes the data are read from this register. write: only if a transition is allowed (see figure 25-5 ). in emulation modes write operations will be also directed to the external bus. the mode bits of the mode register are used to establish the mcu operating mode. caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. address: 0x000b prr 76543210 r modc modb moda 00000 w reset modc 1 modb 1 moda 1 00000 1. external signal (see table 25-2 ). = unimplemented or reserved figure 25-4. mode register (mode) table 25-7. mode field descriptions field description 7? modc, modb, moda mode select bits these bits control the current operating mode during reset high (inactive). the external mode pins modc, modb, and moda determine the operating mode during reset low (active). the state of the pins is latched into the respective register bits after the reset signal goes inactive (see figure 25-5 ). write restrictions exist to disallow transitions between certain modes. figure 25-5 illustrates all allowed mode changes. attempting non authorized transitions will not change the mode bits, but it will block further writes to these register bits except in special modes. both transitions from normal single-chip mode to normal expanded mode and from emulation single-chip to emulation expanded mode are only executed by writing a value of 3?101 (write once). writing any other value will not change the mode bits, but will block further writes to these register bits. changes of operating modes are not allowed when the device is secured, but it will block further writes to these register bits except in special modes. in emulation modes reading this address returns data from the external bus which has to be driven by the emulator. it is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value corresponding to normal single chip mode while the device is in emulation single-chip mode or a value corresponding to normal expanded mode while the device is in emulation expanded mode). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 874 freescale semiconductor figure 25-5. mode transition diagram when mcu is unsecured normal single-chip 100 normal expanded 101 emulation expanded 011 emulation single-chip 001 special test 010 special single-chip 000 101 101 011 011 101 000 010 100 001 001 100 101 reset (ss) 110 111 000 reset reset reset reset reset 010 101 011 001 100 (ex) (nx) (ns) (es) (st) reset transition done by external pins (modc, modb, moda) transition done by write access to the mode register 110 111 illegal (modc, modb, moda) pin values. do not use. (reserved for future use). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 875 25.3.2.3 global page index register (gpage) read: anytime write: anytime the global page index register is used to construct a 23 bit address in the global map format. it is only used when the cpu is executing a global instruction (gldaa, gldab, gldd, glds, gldx, gldy,gstaa, gstab, gstd, gsts, gstx, gsty) (see cpu block guide). the generated global address is the result of concatenation of the cpu local address [15:0] with the gpage register [22:16] (see figure 25-7 ). caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. figure 25-7. gpage address mapping example 25-1. this example demonstrates usage of the gpage register ldx #0x5000 ;set gpage offset to the value of 0x5000 movb #0x14, gpage ;initialize gpage register with the value of 0x14 gldaa x ;load accu a from the global address 0x14_5000 address: 0x0010 76543210 r0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w reset 00000000 = unimplemented or reserved figure 25-6. global page index register (gpage) table 25-8. gpage field descriptions field description 6? gp[6:0] global page index bits 6? these page index bits are used to select which of the 128 64-kilobyte pages is to be accessed. bit16 bit 0 bit15 bit22 cpu address [15:0] gpage register [6:0] global address [22:0] 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 876 freescale semiconductor 25.3.2.4 direct page register (direct) read: anytime write: anytime in special modes, one time only in other modes. this register determines the position of the 256 byte direct page within the memory map.it is valid for both global and local mapping scheme. caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. figure 25-9. direct address mapping bits [22:16] of the global address will be formed by the gpage[6:0] bits in case the cpu executes a global instruction in direct addressing mode or by the appropriate local address to the global address expansion (refer to section 25.4.2.1.1, ?xpansion of the local address map ). example 25-2. this example demonstrates usage of the direct addressing mode movb #0x80,direct ;set direct register to 0x80. write once only. ;global data accesses to the range 0xxx_80xx can be direct. ;logical data accesses to the range 0x80xx are direct. ldy <00 ;load the y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are ?irect page aware?and can address: 0x0011 76543210 r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w reset 00000000 figure 25-8. direct register (direct) table 25-9. direct field descriptions field description 7? dp[15:8] direct page index bits 15? ?these bits are used by the cpu when performing accesses using the direct addressing mode. the bits from this register form bits [15:8] of the address (see figure 25-9 ). bit15 bit0 bit7 bit22 cpu address [15:0] global address [22:0] bit8 bit16 dp [15:8] 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 877 ;automatically select direct mode. 25.3.2.5 mmc control register (mmcctl1) read: anytime. in emulation modes read operations will return the data from the external bus. in all other modes the data are read from this register.write: refer to each bit description. in emulation modes write operations will also be directed to the external bus. caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. eromon and romon control the visibility of the flash in the memory map for cpu or bdm (not for xgate). both local and global memory maps are affected. address: 0x0013 prr 76543210 r00000 eromon romhm romon w reset 00000er omctl 0 romctl = unimplemented or reserved figure 25-10. mmc control register (mmcctl1) table 25-10. mmcctl1 field descriptions field description 2 eromon enables emulated flash or rom memory in the memory map write: never this bit is used in some modes to de?e the placement of the emulated flash or rom (refer to table 25-11 ) 0 disables the emulated flash or rom in the memory map. 1 enables the emulated flash or rom in the memory map. 1 romhm flash or rom only in higher half of memory map write: once in normal and emulation modes and anytime in special modes 0 the ?ed page of flash or rom can be accessed in the lower half of the memory map. accesses to 0x4000?x7fff will be mapped to 0x7f_4000-0x7f_7fff in the global memory space. 1 disables access to the flash or rom in the lower half of the memory map.these physical locations of the flash or rom can still be accessed through the program page window. accesses to 0x4000?x7fff will be mapped to 0x14_4000-0x14_7fff in the global memory space (external access). 0 romon enable flash or rom in the memory map write: once in normal and emulation modes and anytime in special modes. this bit is used in some modes to de?e the placement of the rom (refer to table 25-11 ) 0 disables the flash or rom from the memory map. 1 enables the flash or rom in the memory map. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 878 freescale semiconductor 25.3.2.6 ram page index register (rpage) read: anytime write: anytime these eight index bits are used to page 4 kbyte blocks into the ram page window located in the local (cpu or bdm) memory map from address 0x1000 to address 0x1fff (see figure 25-12 ) . this supports accessing up to 1022 kbytes of ram (in the global map) within the 64 kbyte local map. the ram page index register is effectively used to construct paged ram addresses in the local map format . caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. table 25-11. data sources when cpu or bdm is accessing flash area chip modes romon eromon data source 1 1 internal flash means flash resources inside the mcu are read/written. emulation memory means resources inside the emulator are read/written (pru registers, ?sh replacement, ram, eeprom and register space are always considered internal). external application means resources residing outside the mcu are read/written. stretch 2 2 the external access stretch mechanism is part of the ebi module (refer to ebi block guide for details). normal single chip x x internal flash n special single chip emulation single chip x 0 emulation memory n x 1 internal flash normal expanded 0 x external application y 1 x internal flash n emulation expanded 0 x external application y 1 0 emulation memory n 1 1 internal flash special test 0 x external application n 1 x internal flash address: 0x0016 76543210 r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w reset 11111101 figure 25-11. ram page index register (rpage) 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 879 figure 25-12. rpage address mapping note because ram page 0 has the same global address as the register space, it is possible to write to registers through the ram space when rpage = 0x00. the reset value of 0xfd ensures that there is a linear ram space available between addresses 0x1000 and 0x3fff out of reset. the ?ed 4k page from 0x2000?x2fff of ram is equivalent to page 254 (page number 0xfe). the ?ed 4k page from 0x3000?x3fff of ram is equivalent to page 255 (page number 0xff). table 25-12. rpage field descriptions field description 7? rp[7:0] ram page index bits 7? these page index bits are used to select which of the 256 ram array pages is to be accessed in the ram page window. bit18 bit0 bit11 0 address [11:0] rpage register [7:0] global address [22:0] bit12 bit19 0 address: cpu local address or bdm local address 0 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 880 freescale semiconductor 25.3.2.7 eeprom page index register (epage) read: anytime write: anytime these eight index bits are used to page 1 kbyte blocks into the eeprom page window located in the local (cpu or bdm) memory map from address 0x0800 to address 0x0bff (see figure 25-14 ). this supports accessing up to 256 kbytes of eeprom (in the global map) within the 64 kbyte local map. the eeprom page index register is effectively used to construct paged eeprom addresses in the local map format. caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. figure 25-14. epage address mapping the reset value of 0xfe ensures that there is a linear eeprom space available between addresses 0x0800 and 0x0fff out of reset. the ?ed 1k page 0x0c00?x0fff of eeprom is equivalent to page 255 (page number 0xff). address: 0x0017 76543210 r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w reset 11111110 figure 25-13. eeprom page index register (epage) table 25-13. epage field descriptions field description 7? ep[7:0] eeprom page index bits 7? ?these page index bits are used to select which of the 256 eeprom array pages is to be accessed in the eeprom page window. bit16 bit0 bit9 address [9:0] epage register [7:0] global address [22:0] bit10 bit17 0 0 1 00 address: cpu local address or bdm local address 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 881 25.3.2.8 program page index register (ppage) read: anytime write: anytime these eight index bits are used to page 16 kbyte blocks into the flash page window located in the local (cpu or bdm) memory map from address 0x8000 to address 0xbfff (see figure 25-16 ). this supports accessing up to 4 mbytes of flash (in the global map) within the 64 kbyte local map. the ppage age index register is effectively used to construct paged flash addresses in the local map format. the cpu has special access to read and write this register directly during execution of call and rtc instructions. . caution xgate write access to this register during an cpu access which makes use of this register could lead to unexpected results. figure 25-16. ppage address mapping note writes to this register using the special access of the call and rtc instructions will be complete before the end of the instruction execution. address: 0x0030 76543210 r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w reset 11111110 figure 25-15. program page index register (ppage) bit14 bit0 1 address [13:0] ppage register [7:0] global address [22:0] bit13 bit21 address: cpu local address or bdm local address 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 882 freescale semiconductor the ?ed 16k page from 0x4000?x7fff (when romhm = 0) is the page number 0xfd. the reset value of 0xfe ensures that there is linear flash space available between addresses 0x4000 and 0xffff out of reset. the ?ed 16k page from 0xc000-0xffff is the page number 0xff. 25.3.2.9 ram write protection control register (ramwpc) read: anytime write: anytime table 25-14. ppage field descriptions field description 7? pix[7:0] program page index bits 7? ?these page index bits are used to select which of the 256 flash or rom array pages is to be accessed in the program page window. address: 0x011c 76543210 r rwpe 000 frcpu frxg avie avif w reset 00000000 = unimplemented or reserved figure 25-17. ram write protection control register (ramwpc) table 25-15. ramwpc field descriptions field description 0 rwpe ram write protection enable ?this bit enables the ram write protection mechanism. when the rwpe bit is cleared, there is no write protection and any memory location is writable by the cpu module and the xgate module. when the rwpe bit is set the write protection mechanism is enabled and write access of the cpu or to the xgate ram region. write access performed by the xgate module to outside of the xgate ram region or the shared region is suppressed as well in this case. 0 ram write protection check is disabled, region boundary registers can be written. 1 ram write protection check is enabled, region boundary registers cannot be written. 3 frcpu flexray area could be accessible by the cpu write command ?this bit disables the cpu access permission to the flexray area. 0 cpu accesses the flexray protected area. 1 cpu could not access the flexray protected area. 2 frxg flexray area could be accessible by the xgate write command flexray area could be accessible by the xgate write command. 0 xgate accesses the flexray protected area. 1 xgate could not access the flexray protected area. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 883 25.3.2.10 ram flexray lower boundary register (ramfrl) read: anytime write: anytime 1 avie cpu access violation interrupt enable ?this bit enables the access violation interrupt. if avie is set and avif is set, an interrupt is generated. 0 cpu access violation interrupt disabled. 1 cpu access violation interrupt enabled. 0 avif cpu access violation interrupt flag when set, this bit indicates that the cpu has tried to write a memory location inside the xgate ram region or inside the flexray region when frcpu is set. this ?g can be reset by writing ??to the avif bit location. 0 no access violation by the cpu was detected. 1 access violation by the cpu was detected. table 25-16. system ram protection scheme rwpe frcpu frxg system ram access flexray (read,write) cpu (write) xgate (write) 0 0 0 flexray region whole memory whole memory 0 0 1 flexray region whole memory whole memory except flexray region 0 1 0 flexray region whole memory except flexray region whole memory 0 1 1 flexray region whole memory except flexray region whole memory except flexray region 1 0 0 flexray region (cpu, shared) and flexray region (xgate, shared) and flexray region 1 0 1 flexray region (cpu, shared) and flexray region (xgate, shared) except flexray region 1 1 0 flexray region (cpu, shared) except flexray region (xgate, shared) and flexray region 1 1 1 flexray region (cpu, shared) except flexray region (xgate, shared) except flexray region address: 0x0018 76543210 r frl7 frl6 frl5 frl4 frl3 frl2 frl1 frl0 w reset 11111111 = unimplemented or reserved figure 25-18. ram flexray lower boundary register (ramfrl) table 25-15. ramwpc field descriptions (continued) field description 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 884 freescale semiconductor 25.3.2.11 ram flexray upper boundary register (ramfru) read: anytime write: anytime 25.3.2.12 ram xgate upper boundary register (ramxgu) read: anytime write: anytime when rwpe = 0 table 25-17. ramfrl field descriptions field description 7? frl[7:0] flexray region lower boundary ?these bits de?e the lower boundary of the ram region allocated to the flexray module in multiples of 256 bytes. the 256 byte block selected by this register is included in the region. see figure 25-28 for details. address: 0x0019 76543210 r fru7 fru6 fru5 fru4 fru3 fru2 fru1 fru0 w reset 11111111 = unimplemented or reserved figure 25-19. ram flexray upper boundary register (ramfru) table 25-18. ramfru field descriptions field description 7? fru[7:0] flexray region upper boundary ?these bits de?e the upper boundary of the ram region allocated to the flexray module in multiples of 256 bytes. the 256 byte block selected by this register is included in the region. see figure 25-28 for details. address: 0x011d 76543210 r1 xgu6 xgu5 xgu4 xgu3 xgu2 xgu1 xgu0 w reset 11111111 = unimplemented or reserved figure 25-20. ram xgate upper boundary register (ramxgu) table 25-19. ramxgu field descriptions field description 6? xgu[6:0] xgate region upper boundary bits 6-0 these bits de?e the upper boundary of the ram region allocated to the xgate module in multiples of 256 bytes. the 256 byte block selected by this register is included in the region. see figure 25-28 for details. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 885 25.3.2.13 ram shared region lower boundary register (ramshl) read: anytime write: anytime when rwpe = 0 25.3.2.14 ram shared region upper boundary register (ramshu) read: anytime write: anytime when rwpe = 0 address: 0x011e 76543210 r1 shl6 shl5 shl4 shl3 shl2 shl1 shl0 w reset 11111111 = unimplemented or reserved figure 25-21. ram shared region lower boundary register (ramshl) table 25-20. ramshl field descriptions field description 6? shl[6:0] ram shared region lower boundary bits 6? these bits de?e the lower boundary of the shared memory region in multiples of 256 bytes. the block selected by this register is included in the region. see figure 25-28 for details. address: 0x011f 76543210 r1 shu6 shu5 shu4 shu3 shu2 shu1 shu0 w reset 11111111 = unimplemented or reserved figure 25-22. ram shared region upper boundary register (ramshu) table 25-21. ramshu field descriptions field description 6? shu[6:0] ram shared region upper boundary bits 6? ?these bits de?e the upper boundary of the shared memory in multiples of 256 bytes. the block selected by this register is included in the region. see figure 25-28 for details. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 886 freescale semiconductor 25.4 functional description the mmc block performs several basic functions of the s12x sub-system operation: mcu operation modes, priority control, address mapping, select signal generation and access limitations for the system. each aspect is described in the following subsections. 25.4.1 mcu operating mode normal single-chip mode there is no external bus in this mode. the mcu program is executed from the internal memory and no external accesses are allowed. special single-chip mode this mode is generally used for debugging single-chip operation, boot-strapping or security related operations. the active background debug mode is in control of the cpu code execution and the bdm ?mware is waiting for serial commands sent through the bkgd pin. there is no external bus in this mode. emulation single-chip mode tool vendors use this mode for emulation systems in which the users target application is normal single-chip mode. code is executed from external or internal memory depending on the set-up of the eromon bit (see section 25.3.2.5, ?mc control register (mmcctl1) ). the external bus is active in both cases to allow observation of internal operations (internal visibility). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 887 normal expanded mode the external bus interface is con?ured as an up to 23-bit address bus, 8 or 16-bit data bus with dedicated bus control and status signals. this mode allows 8 or 16-bit external memory and peripheral devices to be interfaced to the system. the fastest external bus rate is half of the internal bus rate. an external signal can be used in this mode to cause the external bus to wait as desired by the external logic. emulation expanded mode tool vendors use this mode for emulation systems in which the users target application is normal expanded mode. special test mode this mode is an expanded mode for factory test. 25.4.2 memory map scheme 25.4.2.1 cpu and bdm memory map scheme the bdm ?mware lookup tables and bdm register memory locations share addresses with other modules; however they are not visible in the memory map during users code execution. the bdm memory resources are enabled only during the read_bd and write_bd access cycles to distinguish between accesses to the bdm memory area and accesses to the other modules. (refer to bdm block guide for further details). when the mcu enters active bdm mode, the bdm ?mware lookup tables and the bdm registers become visible in the local memory map in the range 0xff00-0xffff (global address 0x7f_ff00 - 0x7f_ffff) and the cpu begins execution of ?mware commands or the bdm begins execution of hardware commands. the resources which share memory space with the bdm module will not be visible in the memory map during active bdm mode. please note that after the mcu enters active bdm mode the bdm ?mware lookup tables and the bdm registers will also be visible between addresses 0xbf00 and 0xbfff if the ppage register contains value of 0xff. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 888 freescale semiconductor figure 25-23. expansion of the local address map 0x7f_ffff 0x00_0000 0x14_0000 0x10_0000 0x00_0800 epage rpage ppage cpu and bdm local memory map global memory map 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x0c00 0x2000 0x0800 8k ram 4k ram window 1k eeprom 2k registers 1k eeprom window 16k flash unpaged 16k flash 2k registers 2k ram 253*4k paged ram 1k eeprom 255*1k paged eeprom 253 *16k paged flash 16k flash (ppage 0xfd) 8k ram external space 16k flash (ppage 0xfe) 16k flash (ppage 0xff) 0x00_1000 0x0f_e000 0x13_fc00 0x40_0000 0x7f_4000 0x7f_8000 0x7f_c000 1m minus 2 kilobytes 256 kilobytes 4 mbytes 2.75 mbytes 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 889 25.4.2.1.1 expansion of the local address map expansion of the cpu local address map the program page index register in mmc allows accessing up to 4 mbyte of flash or rom in the global memory map by using the eight page index bits to page 256 16 kbyte blocks into the program page window located from address 0x8000 to address 0xbfff in the local cpu memory map. the page value for the program page window is stored in the ppage register. the value of the ppage register can be read or written by normal memory accesses as well as by the call and rtc instructions (see section 25.5.1, ?all and rtc instructions ). control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64-kilobyte local cpu address space. the starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the ppage register will be set to the appropriate value when the service routine is called. however an interrupt service routine can call other routines that are in paged memory. the upper 16-kilobyte block of the local cpu memory space (0xc000?xffff) is unpaged. it is recommended that all reset and interrupt vectors point to locations in this area or to the other unpaged sections of the local cpu memory map. table 25-22 table 25-12 summarizes mapping of the address bus in flash/external space based on the address, the ppage register value and value of the romhm bit in the mmcctl1 register. the ram page index register allows accessing up to 1 mbyte ? kbytes of ram in the global memory map by using the eight rpage index bits to page 4 kbyte blocks into the ram page window located in the local cpu memory space from address 0x1000 to address 0x1fff. the eeprom page index register epage allows accessing up to 256 kbytes of eeprom in the system by using the eight epage index bits to page 1 kbyte blocks into the eeprom page window located in the local cpu memory space from address 0x0800 to address 0x0bff. table 25-22. global flash/rom allocated local cpu address romhm external access global address 0x4000?x7fff 0 no 0x7f_4000 ?x7f_7fff 1 yes 0x14_4000?x14_7fff 0x8000?xbfff n/a no 1 1 the internal or the external bus is accessed based on the size of the memory resources implemented on-chip. please refer to figure 1-23 for further details. 0x40_0000?x7f_ffff n/a yes 1 0xc000?xffff n/a no 0x7f_c000?x7f_ffff 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 890 freescale semiconductor expansion of the bdm local address map ppage, rpage, and epage registers are also used for the expansion of the bdm local address to the global address. these registers can be read and written by the bdm. the bdm expansion scheme is the same as the cpu expansion scheme. 25.4.2.2 global addresses based on the global page cpu global addresses based on the global page the seven global page index bits allow access to the full 8 mbyte address map that can be accessed with 23 address bits. this provides an alternative way to access all of the various pages of flash, ram and eeprom as well as additional external memory. the gpage register is used only when the cpu is executing a global instruction (see section 25.3.2.3, ?lobal page index register (gpage) ). the generated global address is the result of concatenation of the cpu local address [15:0] with the gpage register [22:16] (see figure 25-7 ). bdm global addresses based on the global page the seven bdmgpr global page index bits allow access to the full 8 mbyte address map that can be accessed with 23 address bits. this provides an alternative way to access all of the various pages of flash, ram and eeprom as well as additional external memory. the bdm global page index register (bdmgpr) is used only in the case the cpu is executing a ?mware command which uses a global instruction (like gldd, gstd) or by a bdm hardware command (like write_w, write_byte, read_w, read_byte). see the bdm block guide for further details. the generated global address is a result of concatenation of the bdm local address with the bdmgpr register [22:16] in the case of a hardware command or concatenation of the cpu local address and the bdmgpr register [22:16] in the case of a ?mware command (see figure 25-24 ). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 891 figure 25-24. bdmgpr address mapping bit16 bit0 bit15 bit22 bdm local address bdmgpr register [6:0] global address [22:0] bit16 bit0 bit15 bit22 cpu local address bdmgpr register [6:0] global address [22:0] bdm hardware command bdm firmware command 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 892 freescale semiconductor 25.4.2.3 implemented memory map the global memory spaces reserved for the internal resources (ram, eeprom, and flash) are not determined by the mmc module. size of the individual internal resources are however xed in the design of the device cannot be changed by the user. please refer to the device user guide for further details. figure 25-25 and table 25-23 show the memory spaces occupied by the on-chip resources. please note that the memory spaces have ?ed top addresses. when the device is operating in expanded modes except emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip resources (unimplemented areas or external memory space) result in accesses to the external bus (see figure 25-25 ). in emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip resources (unimplemented areas) result in accesses to the external bus. cpu accesses to global addresses which are occupied by external memory space result in an illegal access reset (system reset). bdm accesses to the external space are performed but the data will be unde?ed. in single-chip modes accesses by the cpu (except for ?mware commands) to any of the unimplemented areas (see figure 25-25 ) will result in an illegal access reset (system reset). bdm accesses to the unimplemented areas are allowed but the data will be unde?ed. no misaligned word access from the bdm module will occur; these accesses are blocked in the bdm module (refer to bdm block guide). misaligned word access to the last location of ram is performed but the data will be unde?ed. misaligned word access to the last location of any global page (64 kbyte) by any global instruction, is performed by accessing the last byte of the page and the ?st byte of the same page, considering the above mentioned misaligned access cases. the non-internal resources (unimplemented areas or external space) are used to generate the chip selects (cs0,cs1,cs2 and cs3) (see figure 25-25 ), which are only active in normal expanded, emulation expanded and special test modes (see section 25.3.2.1, ?mc control register (mmcctl0) ). table 25-23. global implemented memory space internal resource $address ram ram_low = 0x10_0000 minus ramsize 1 1 ramsize is the hexadecimal value of ram size in bytes eeprom eeprom_low = 0x14_0000 minus eepromsize 2 2 eepromsize is the hexadecimal value of eeprom size in bytes flash0 3 3 internal flash size (flashsize) is the sum of flashsize0 and flashsize1. flash0_low = 0x77_ffff plus flashsize0 flash1 flash1_high = 0x80_0000 minus flashsize1 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 893 table 25-24 shows the address boundaries of each chip select and the relationship with the implemented resources (internal) parameters. table 25-24. global chip selects memory space chip selects bottom address top address cs3 0x00_0800 0x0f_ffff minus ramsize 1 1 external rpage accesses in (nx, ex and st) cs2 0x10_0000 0x13_ffff minus eepromsize 2 2 external epage accesses in (nx, ex and st) cs2 3 3 when romhm is set (see romhm in table 25-22 ) the cs2 is asserted in the space occupied by this on-chip memory block. 0x14_0000 0x1f_ffff cs1 0x20_0000 0x3f_ffff cs0 4 4 when the internal nvm is enabled (see romon in section 25.3.2.5, ?mc control register (mmcctl1) ) the cs0 is not asserted in the space occupied by this on-chip memory block. 0x40_0000 0x7f_ffff minus flashsize 5 5 external ppage accesses in (nx, ex and st) 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 894 freescale semiconductor figure 25-25. local to implemented global address mapping (without gpage) 0x7f_ffff 0x00_0000 0x13_ffff 0x0f_ffff eeprom ram 0x00_07ff epage rpage ppage 0x3f_ffff cpu and bdm local memory map global memory map flashsize eepromsize ramsize unimplemented eeprom unimplemented flash cs3 cs2 cs1 cs0 0x1f_ffff cs2 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x0c00 0x2000 0x0800 8k ram 4k ram window 1k eeprom 2k registers 1k eeprom window 16k flash unpaged 16k flash 2k registers unimplemented ram external space ram_low eeprom_low 0x78_0000 flash1 flash0_low flash1_high flash0 unimplemented flash cs0 flashsize0 flashsize1 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 895 25.4.2.4 xgate memory map scheme 25.4.2.4.1 expansion of the xgate local address map the xgate 64 kbyte memory space allows access to internal resources only (registers, ram, and flash). the 2 kilobyte register address range is the same register address range as for the cpu and the bdm module (see table 25-25 ). xgate can access the flash in single chip modes, even when the mcu is secured. in expanded modes, xgate can not access the flash when mcu is secured. the local address of the xgate ram access is translated to the global ram address range. the xgate shares the ram resource with the cpu and the bdm module (see table 25-25 ). xgate ram size (xgramsize) may be lower or equal to the mcu ram size (ramsize). the local address of the xgate flash access is translated to the global address as de?ed by table 25-25 . example 25-3. is a general example of the xgate memory map implementation. example 25-3. the mcu flashsize is 64 kbytes (0x10000) and mcu ramsize is 32 kbytes (0x8000). the xgate ramsize is 16 kbytes (0x4000). the space occupied by the xgate ram in the global address space will be: bottom address: (0x10_0000 minus 0x4000) = 0x0f_c000 top address: 0x0f_ffff xgate accesses to local address range 0x0800?xbfff will result in accesses to the following flash block in the global address space: bottom address: 0x78_0800 top address: (0x78_ffff minus 0x4000) = 0x78_bfff table 25-25. xgate implemented memory space internal resource $address xgate ram xgram_low = 0x0f_0000 plus (0x1_0000 minus xgramsize) 1 1 xgramsize is the hexadecimal value of xgate ram size in bytes. xgate flash xgflash_high = 0x78_0000 plus (0xffff minus xgramsize) 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 896 freescale semiconductor figure 25-26. xgate global address mapping 0x7f_ffff 0x00_0000 0x0f_ffff 0xffff 0x0000 registers flash ram 0x0800 registers 0x00_07ff xgate local memory map global memory map xgflashsize xgramsize ramsize 0x78_0800 flash ram xgram_low xgflash_high 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 897 25.4.2.5 flexray memory map scheme 25.4.2.5.1 flexray local address map the flexray memory space allows access to system ram only (see figure 25-27 ). the flexray local address is translated to the global ram address range. the flexray shares the ram resource with the cpu, bdm and xgate (see table 25-26 ). flexray ram size (xfrramsize) may be lower or equal to the mcu ram size (ramsize). table 25-26. flexray resources internal resource size /kbyte bottom address ram xfrramsize xfrram_low = 0x0f_0000 plus (ramfrl_00) xfrram_high = 0x0f_0000 plus (ramfru_ff) 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 898 freescale semiconductor figure 25-27. flexray local to global address mapping 0x7f_ffff 0x00_0000 0x0f_ffff ram flexray memory map global memory map ramsize ram xfrram_low xfrram_high ramfrl_00 ramfru_ff xfrramsize 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 899 25.4.3 chip access restrictions 25.4.3.1 illegal flexray accesses a possible access error is ?gged by the s12x_mmc and signalled to flexray under the following conditions: flexray performs an access to the outside range of the speci?d area. this area is de?ed by using the two programmable boundary addresses in the registers (ramfrl ( 25.3.2.10 ram flexray lower boundary register (ramfrl) ), ramfru ( 25.3.2.11 ram flexray upper boundary register (ramfru) )) (see figure 25-28 ). the following conditions must be satis?d: value stored in ramfrl must be lower or equal than the value of the corresponding position of flexray effective address. value stored in ramfru must be upper or equal than the value of the corresponding position of flexray effective address. the flexray region could overlap any of the other regions de?ed below in 25.4.3.2 and 25.4.3.3 . the access permission of the cpu or xgate to the flexray area is de?ed by the two bits frcpu and frxg (see table 25-16 ) (see figure 25-28 ). for further details refer to the flexray block guide. 25.4.3.2 illegal xgate accesses a possible access error is ?gged by the mmc and signalled to xgate under the following conditions: xgate performs misaligned word (in case of load-store or opcode or vector fetch accesses). xgate accesses the register space (in case of opcode or vector fetch). xgate performs a write to flash in any modes (in case of load-store access). xgate performs an access to a secured flash in expanded modes (in case of load-store or opcode or vector fetch accesses). xgate performs an access to an unimplemented area (in case of load-store or opcode or vector fetch accesses). xgate performs a write to non-xgate region in ram (ram protection mechanism) (in case of load-store access). for further details refer to the xgate block guide. 25.4.3.3 illegal cpu accesses after programming the protection mechanism registers (see figure 25-17 , figure 25-20 , figure 25-21 , and figure 25-22 ) and setting the rwpe bit (see figure 25-17 ) there are 3 regions recognized by the mmc module: 1. xgate ram region 2. cpu ram region 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 900 freescale semiconductor 3. shared region (xgate and cpu) if the rwpe bit is set the cpu write accesses into the xgate ram region are blocked. if the cpu tries to write the xgate ram region the avif bit is set and an interrupt is generated if enabled. furthermore if the xgate tries to write to outside of the xgate ram or shared regions and the rwpe bit is set, the write access is suppressed and the access error will be ?gged to the xgate module (see section 25.4.3.2, ?llegal xgate accesses and the xgate block guide). the bottom address of the xgate ram region always starts at the lowest implemented ram address. the values stored in the boundary registers de?e the boundary addresses in 256 byte steps. the 256 byte block selected by any of the registers is always included in the respective region. for example setting the shared region lower boundary register (ramshl) to 0xc1 and the shared region upper boundary register (ramshu) to 0xe0 de?es the shared region from address 0x0f_c100 to address 0x0f_e0ff in the global memory space (see figure 25-22 ). the interrupt requests generated by the mmc are listed in table 25-27 . refer to the device user guide for the related interrupt vector address and interrupt priority. the following conditions must be satis?d to ensure correct operation of the ram protection mechanism: value stored in ramxgu must be lower than the value stored in ramshl. value stored ramshl must be lower or equal than the value stored in ramshu. table 25-27. ram write protection interrupt vectors interrupt source ccr mask local enable cpu access violation i bit avie in ramwpc 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 901 figure 25-28. ram write protection scheme and flexray (cpu and/or xgate) 0x0f_ffff 0x0f_ramshu_ff 0x0f_ramshl_00 0x0f_ramxgu_ff xgramsize 0x0f_ramfrl_00 0x0f_ramfru_ff ramsize flexray area can overlap any of other regions. xgate cpu cpu cpu cpu and xgate 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 902 freescale semiconductor 25.4.4 chip bus control the mmc controls the address buses and the data buses that interface the s12x masters (cpu, bdm, flexray and xgate) with the rest of the system (master buses). in addition the mmc handles all cpu read data bus swapping operations. all internal and external resources are connected to speci? target buses (see figure 25-29 1 ). figure 25-29. mmc block diagram 1. doted blocks and lines are optional. please refer to the device user guide for their availlibilities. cpu bdm mmc ?rossbar switch xgate s12x1 s12x0 xgate xbus3 xbus0 xbus1 xram xbus2 dbg flexray s12x2 ipbi flash eetx ebi xsram bdm ftx blkx resources 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 903 25.4.4.1 master bus prioritization regarding access con?cts on target buses the arbitration scheme allows only one master to be connected to a target at any given time. the following rules apply when prioritizing accesses from different masters to the same target bus: high priority 1 flexray access to xsram has priority over cpu, xgate and bdm. cpu always has priority over bdm, flexray and xgate. xgate access to pru registers constitutes a special case. it is always granted and stalls the cpu for its duration.fcg_arbiter xgate has priority over flexray and bdm. bdm has priority over cpu, flexray and xgate when its access is stalled for more than 128 cycles. in the later case the suspect master will be stalled after ?ishing the current operation and the bdm will gain access to the bus. in emulation modes all internal accesses are visible on the external bus as well and the external bus is used during access to the pru registers. 25.4.5 interrupts 25.4.5.1 outgoing interrupt requests the following interrupt requests can be triggered by the mmc module: cpu access violation: the cpu access violation signals to the cpu detection of an error condition in the cpu application code which is resulted in write access to the protected xgate ram area (see section 25.4.3.3, ?llegal cpu accesses ). 25.5 initialization/application information 25.5.1 call and rtc instructions call and rtc instructions are uninterruptable cpu instructions that automate page switching in the program page window. the call instruction is similar to the jsr instruction, but the subroutine that is called can be located anywhere in the local address space or in any flash or rom page visible through the program page window. the call instruction calculates and stacks a return address, stacks the current ppage value and writes a new instruction-supplied value to the ppage register. the ppage value controls which of the 256 possible pages is visible through the 16 kbyte program page window in the 64 kbyte local cpu memory map. execution then begins at the address of the called subroutine. during the execution of the call instruction, the cpu performs the following steps: 1. writes the current ppage value into an internal temporary register and writes the new instruction-supplied ppage value into the ppage register 2. calculates the address of the next instruction after the call instruction (the return address) and pushes this 16-bit value onto the stack 3. pushes the temporarily stored ppage value onto the stack 1. flexray has two priority access types, one called high priority access and the other called normal access. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 904 freescale semiconductor 4. calculates the effective address of the subroutine, re?ls the queue and begins execution at the new address this sequence is uninterruptable. there is no need to inhibit interrupts during the call instruction execution. a call instruction can be performed from any address to any other address in the local cpu memory space. the ppage value supplied by the instruction is part of the effective address of the cpu. for all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction. in indexed-indirect variations of the call instruction a pointer speci?s memory locations where the new page value and the address of the called subroutine are stored. using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the time of assembly. the rtc instruction terminates subroutines invoked by a call instruction. the rtc instruction unstacks the ppage value and the return address and re?ls the queue. execution resumes with the next instruction after the call instruction. during the execution of an rtc instruction the cpu performs the following steps: 1. pulls the previously stored ppage value from the stack 2. pulls the 16-bit return address from the stack and loads it into the pc 3. writes the ppage value into the ppage register 4. re?ls the queue and resumes execution at the return address this sequence is uninterruptable. the rtc can be executed from anywhere in the local cpu memory space. the call and rtc instructions behave like jsr and rts instruction, they however require more execution cycles. usage of jsr/rts instructions is therefore recommended when possible and call/rtc instructions should only be used when needed. the jsr and rts instructions can be used to access subroutines that are already present in the local cpu memory map (i.e. in the same page in the program memory page window for example). however calling a function located in a different page requires usage of the call instruction. the function must be terminated by the rtc instruction. because the rtc instruction restores contents of the ppage register from the stack, functions terminated with the rtc instruction must be called using the call instruction even when the correct page is already present in the memory map. this is to make sure that the correct ppage value will be present on stack at the time of the rtc instruction execution. 25.5.2 port replacement registers (prrs) registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full emulation of single chip mode operation. these registers are called port replacement registers (prrs) (see table 1-25 ). prrs are accessible from cpu, bdm and xgate using different access types (word aligned, word-misaligned and byte). each access to prrs will be extended to 2 bus cycles for write or read accesses independent of the operating mode. in emulation modes all write operations result in simultaneous writing to the internal registers (peripheral access) and to the emulated registers (external access) located in the pru in the 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 905 emulator. all read operations are performed from external registers (external access) in emulation modes. in all other modes the read operations are performed from the internal registers (peripheral access). due to internal visibility of cpu accesses the cpu will be halted during xgate or bdm access to any prr. this rule applies also in normal modes to ensure that operation of the device is the same as in emulation modes. a summary of prr accesses: an aligned word access to a prr will take 2 bus cycles. a misaligned word access to a prrs will take 4 cycles. if one of the two bytes accessed by the misaligned word access is not a prr, the access will take only 3 cycles. a byte access to a prr will take 2 cycles. table 25-28. prr listing prr name prr local address prr location porta 0x0000 pim portb 0x0001 pim ddra 0x0002 pim ddrb 0x0003 pim portc 0x0004 pim portd 0x0005 pim ddrc 0x0006 pim ddrd 0x0007 pim porte 0x0008 pim ddre 0x0009 pim mmcctl0 0x000a mmc mode 0x000b mmc pucr 0x000c pim rdriv 0x000d pim ebictl0 0x000e ebi ebictl1 0x000f ebi reserved 0x0012 mmc mmcctl1 0x0013 mmc eclkctl 0x001c pim reserved 0x001d pim portk 0x0032 pim ddrk 0x0033 pim 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 906 freescale semiconductor 25.5.3 on-chip rom control the mcu offers two modes to support emulation. in the ?st mode (called generator) the emulator provides the data instead of the internal flash and traces the cpu actions. in the other mode (called observer) the internal flash provides the data and all internal actions are made visible to the emulator. 25.5.3.1 rom control in single-chip modes in single-chip modes the mcu has no external bus. all memory accesses and program fetches are internal (see figure 25-30 ). figure 25-30. rom in single chip modes 25.5.3.2 rom control in emulation single-chip mode in emulation single-chip mode the external bus is connected to the emulator. if the eromon bit is set, the internal flash provides the data and the emulator can observe all internal cpu actions on the external bus. if the eromon bit is cleared, the emulator provides the data (generator) and traces the all cpu actions (see figure 25-31 ). figure 25-31. rom in emulation single-chip mode mcu flash no external bus eromon = 1 emulator mcu eromon = 0 emulator flash mcu flash observer generator 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 907 25.5.3.3 rom control in normal expanded mode in normal expanded mode the external bus will be connected to the application. if the romon bit is set, the internal flash provides the data. if the romon bit is cleared, the application memory provides the data (see figure 25-32 ). figure 25-32. rom in normal expanded mode romon = 1 application mcu romon = 0 application mcu flash memory memory 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 908 freescale semiconductor 25.5.3.4 rom control in emulation expanded mode in emulation expanded mode the external bus will be connected to the emulator and to the application. if the romon bit is set, the internal flash provides the data. if the eromon bit is set as well the emulator observes all cpu internal actions, otherwise the emulator provides the data and traces all cpu actions (see figure 25-33 ). when the romon bit is cleared, the application memory provides the data and the emulator will observe the cpu internal actions (see figure 25-34 ). figure 25-33. romon = 1 in emulation expanded mode eromon = 1 application mcu flash memory emulator eromon = 0 application mcu memory emulator flash generator observer 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 909 figure 25-34. romon = 0 in emulation expanded mode 25.5.3.5 rom control in special test mode in special test mode the external bus is connected to the application. if the romon bit is set, the internal flash provides the data, otherwise the application memory provides the data (see figure 25-35 ). figure 25-35. rom in special test mode application mcu memory emulator observer application mcu memory romon = 0 application mcu memory romon = 1 flash 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 910 freescale semiconductor 25.6 internal information 25.6.1 overview the crossbar switch is an s12x block which manages the interconnection between system masters and system targets. each master and target interfaces to the crossbar switch using defined bus protocols. some bus masters are synchronized with the system clock (s12x buses); others are working at double the speed of the system clock (xgate bus). this chapter describes the functionality of the s12x_mmc crossbar switch regarding system behavior, master features, target features and priority scheme. 25.6.2 s12x system behavior 25.6.2.1 s12x platform architecture 25.6.2.1.1 block diagram figure 25-36 shows the block diagram of the s12x_mmc. figure 25-36. s12x_mmc block diagram 25.6.2.1.2 generic platform this section describes the generic parameters of the s12x_mmc s12x_flexray s12x_cpu s12x_bdm s12x_mmc ?rossbar switch xgate s12x1 s12x0 s12x2 xgate xbus3 xbus0 xbus1 xram xbus2 s12x_dbg ipbi flash eetx ebi xsram bdm ftx blkx resources 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 911 mcu_xsramsize the mcu_xsramsize parameter de?es the implemented system ram (xsram) size. xsram size granularity is 4 kilobytes. the maximum size supported is 1022 kilobytes. mcu_xgxsramsize the mcu_xgxsramsize parameter de?es the implemented xsram size which xgate can access. this value should be less or equal to the mcu_xsramsize. the last-byte address of the xgate ram is identical to the last-byte address of the system ram (xsram) which is 0x0f_ffff. the xgate ram size granularity is 256 bytes. the maximum size supported is 62 kilobytes. table 25-29. generic architecture parameters con?uration min./max. description default unit mcu_xsramsize ?3000/?ff800 de?es the implemented xsram size ?4000 byte mcu_xgxsramsize ?0800/min. {mcu_xsramsiz e,?f800} de?es the implemented xsram size which xgate can access. mcu_xsramsize byte mcu_eetxsize ?0800/?40000 de?es the implemented eeprom (eetx) size ?800 byte mcu_ftxsize ?10000/?400000 de?es the implemented flash (ftx) size ?20000 byte mcu_ftxblks ?1/?8 1 1 the maximum size of one hard-macro in tsmc25unvm is 128 kilobytes. in ll18, the maximum size of one hard-macro is 256 kilobytes. the maximum value is not exhaustive and could change in the future due to the availability of some big ?sh hard-macros. de?es the number of flash blocks, to de?e the size of one hard-macro. ?2 block mcu_xgate n.a. de?es if xgate is on board or not 1?1 logic mcu_xgate_ftx_acc 2 2 this parameter is valid only when mcu_xgate = 1?1. n.a. de?es the availability of the flash read bus (xbus1) which xgate can access 1?1 logic mcu_flexray n.a. de?es if s12x_flexray is on board or not 1?0 logic mcu_ebi n.a. de?es the availability of the external bus (xbus3) 1?1 logic mcu_fmts n.a. de?es if xsram supports fast memory transfer. 1?1 logic mcu_ipbi_xfr_wait n.a. de?es the availability of the transfer wait mechanism in ipbi 1?0 logic 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 912 freescale semiconductor mcu_eetxsize the mcu_eetxsize parameter de?es the implemented system eetx (eeprom) size. eetx size granularity is 1 kilobytes. the maximum size supported is 256 kilobytes. mcu_ftxsize the mcu_ftxsize parameter de?es the implemented system flash size. flash size granularity is 16 kilobytes. the maximum size supported is 4 mbytes. mcu_xgate_ftx_acc s12x platform supports xgate read only access to the flash via xbus1. the speci? block connected to xbus1 is called blkx and its start address is always ?ed to the global address 0x78_0000. blkx is available only if ( mcu_xgate_ftx_acc = 1). table 25-30 describes the flash block accesses by using the right ppage value for each device configuration. table 25-30. different possibilities of flash block distribution mcu_ftxsize hard-macro size mcu_xgate_ftx_acc implemented flash address ?10000 (64 kilobytes) 64 kilobytes 0 blk0: (0xfc..0xff) blkx: n.a. ?20000 (128 kilobytes) 64 kilobytes 0 blk[1:0]: (0xf8..0xff) blkx: n.a. 1 blk0: (0xfc..0xff) blkx: (0xe0..0xe3) 128 kilobytes 0 blk0: (0xf8..0xff) blkx: n.a. ?40000 (256 kilobytes) 128 kilobytes 0 blk[1:0]: (0xf0..0xff) blkx: n.a. 1 blk0: (0xf8..0xff) blkx: (0xe0..0xe7) ?60000 (384 kilobytes) 128 kilobytes 0 blk[2:0]: (0xe8..0xff) blkx: n.a. 1 blk[1:0]: (0xf0..0xff) blkx: (0xe0..0xe7) ?80000 (512 kilobytes) 128 kilobytes 0 blk[3:0]: (0xe0..0xff) blkx: n.a. 1 blk[3:0]: (0xe0..0xff) blkx: blk3 ?c0000 (768 kilobytes) 128 kilobytes 0 blk[5:0]: (0xd0..0xff) blkx: n.a. 1 blk[5:0]: (0xd0..0xff) blkx: blk3 ?100000 (1024 kilobytes) 256 kilobytes 0 blk[3:0]: (0xc0..0xff) blkx: n.a. 1 blk[3:0]: (0xc0..0xff) blkx: blk1 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 913 the example done in table 25-30 is not exhaustive and could be extended to more configurations. mcu_xgate_ftx_acc is valid only if ( mcu_xgate = 1). some devices could have xgate on board but doesnt allow xgate access to flash. in this case, s12x_mmc considers that the flash location in the xgate memory map is an illegal space (see section 25.6.2.4.3, ?gate address translation ). mcu_ftxblk the mcu_ftxblk parameter de?es the unique size of an implemented flash hard-macro. the usage of this parameter is to de?e the upper address of blkx (see table 25-30 ) to arbiter the xgate access and other master access to the blkx. mcu_fmts the xsram is designed to support misaligned word access in one cycle. this behavior is called fast memory transfer ( mcu_fmts = 1 ). if the xsram doesnt support this feature (low end memories), the misaligned word access will be split into two byte accesses ( mcu_fmts = 0 ). mcu_xgate some devices do not support a second processor on board (low-end) ( mcu_xgate = 0). this con?uration parameter disables the xgate activities inside the crossbar switch and removes xbus1 (flash read data bus for xgate). mcu_flexray some devices do not support a s12x_flexray master (mcu_flexray = 0). this con?uration parameter disables the s12x_felxray activities inside the crossbar switch. mcu_ebi (external bus interface) low pin count devices dont have external bus (no s12x_ebi). the bus interface between the crossbar and s12x_ebi is removed when ( mcu_ebi = 0). the mode state machine supports two states mode = ?s?(normal single chip mode) ( modc = 1) mode = ?s?(special single chip mode) ( modc = 0) moda and modb input pins are not available in low-pin count and modc input pin determinates the current operating mode. no s12x_cpu visibility ( xbus3_vis_sel = 0) mcu_ipbi_xfr_wait some slow peripherals can not achieve their commands within 0-wait-state (for read or write). it asserts ips_xfr_wait to prevent that this command is not ?ished. the signal derived from ips_xfr_wait and called xbus2_data_wait suspends the concerned s12x master and dont acknowledge its new transaction. 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 914 freescale semiconductor for xgate two protocols are supported: if ( mcu_ipbi_xfr_wait = 0): xbus2_data_wait = 0 xgate write access to registers (xbus2) is acknowledged in t2 cycle. if ( mcu_ipbi_xfr_wait = 1): xgate write access to registers (xbus2) is acknowledged in the second t2 cycle if ( xbus2_data_wait = 0). 25.6.2.2 system reset pim_romctl , pim_eromctl , pim_moda , pim_modb and pim_modc are system input values which de?e the behavior of the system after the system reset is de-asserted ( ipg_hard_async_reset_b = 1). these values have to maintain stability before the input reset ipp_reset_ind is de-asserted ( ipp_reset_ind = 0). ipp_reset_ind and system reset ( ipg_hard_async_reset_b ) must be deasserted at t4. all system clocks are available after the system reset is de-asserted. all masters are in idle mode. all masters transactions are blocked and not executed due to the nvm hold mechanism. this mechanism determines the nvm security state and initializes the nvm state machines. during this time, the nvm wrapper sends signals that all targets are considered busy to prevent any master accesses of targets ( nvm_hold = eetx_hold_t4 || ftx_hold_t4 = 1). 25.6.2.3 system security after the nvm hold signal is deasserted ( nvm_hold = 0), the nvm security status is determined and sent to the crossbar switch ( seqreq_t4 ). this signal will be combined with the security status signal sent by s12x_bdm which is used in the process of unsecuring the chip (verifying the blank_check mechanism in the nvm) ( bdm_unsecure_t4 ) to de?e the system security signal mmc_secure_t2 (delivered on t2). if the system is in secure mode ( mmc_secure_t2 = 1): all s12x_bdm transactions are mapped to the 2k registers address map (0x00_0000 to 0x00_07ff). all nvm blocks are removed from the global address map in expanded modes.any access to these blocks is redirected to the external space. 25.6.2.4 writes to the mode register (mode, 0x000b) do not change the current operating mode, but will block further writes to these register bits except in special modes. local to global address translation 25.6.2.4.1 s12x_cpu & s12x_bdm address translation two types of address translation from local address map (64 kilobytes) to the global address map (8 mbytes) are featured. the ?st called ?egacy translation uses different pages (ppage,rpage,epage) to do the translation (using s12 load and store), and the second, called ?lobal translation?concatenates the global page (gpage or bdmgpr) to the address using global instructions (global load, global store). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 915 table 25-31 shows the address translation type of the s12x_addr_cpu. table 25-32 shows the address translation type of the s12x_addr_bdm. legacy address translation figure 25-37 shows the ?st type of translation ?egacy translation? (s12x_req_cpu = 1 and s12x_addr_cpu[15:0] and cpu_global_t2 = 0), (s12x_req_bdm = 1 and s12x_addr_bdm[15:0] and bdm_gab_t4 = 0), ? cpu_pc[15:0] and cpu_global_t2 = x). table 25-31. cpu address translation s12x_req_cpu cpu_global_t2 bdm_?minmap_t4 bdm_gab_t4 translation type used resources 1 0 x x legacy rpage,epage, ppage, romhm 1 1 0 x global gpage 1 1 1 0 legacy rpage,epage, ppage, romhm 1 1 1 1 global bdmgpr table 25-32. bdm address translation s12x_req_bdm bdm_gab_t4 bdm_hardinmap_t4 translation type used resources 1 0 x legacy rpage,epage, ppage, romhm 1 1 0 global bdmgpr 1 1 1 legacy 1 1 this case does not occur in the actual implementation ?dm did the restriction to force the bdm_gab_t4 to ??if bdm_hardinmap_t4 is asserted ?ubject to be discussed rpage,epage, ppage, romhm 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 916 freescale semiconductor figure 25-37. legacy address translation global address translation figure 25-38 shows the second type of translation ?lobal translation? this global translation is supported for: ? s12x_req_cpu = 1 and s12x_addr_cpu[15:0] and cpu_global_t2 = 1 and bdm_?minmap_t2 = 0), ? s12x_req_cpu = 1 and s12x_addr_cpu[15:0] and bdm_gab_t4 = 1 and bdm_?minmap_t2 =1)in the case of a ?mware command. ? s12x_req_bdm = 1 and s12x_addr_bdm[15:0] and bdm_gab_t4 = 1 and bdm_hardinmap_t2 =1) in the case of a hardware command. 0x0000 0xffff local address rpage epage ppage global address 0x00_0000 0x7f_ffff a trans trans(a) romhm trans (a[15:0],rpage) = {3?000, rpage, a[11:0]} trans (a[15:0],epage) = {5?00100, epage, a[9:0]} trans (a[15:0],ppage) = {1?0, ppage, a[13:0]} trans (a[15:0],romhm = 1) = {?7f, a[15:0]} if a[15:0] {0x4000 - 0x7fff} trans (a[15:0],romhm = 0) = {?14, a[15:0]} if a[15:0] {0x4000 - 0x7fff} 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 917 figure 25-38. global address translation 25.6.2.4.2 s12x_flexray address translation s12x_flexray does not support the above translation schemes. it sends the complete global address. 25.6.2.4.3 xgate address translation xgate supports a third translation scheme without any usage of pages. the translation is done by a simple redirection of the local address to the internal resource location on the global address map. the local address of the xgate is translated to the global address as de?ed by table 25-25 . table 25-33. xgate memory map internal resource local address global address registers 0x0000 - 0x07ff 0x00_0000 - 0x00_07ff flash (blkx) if (mcu_xgate_ftx_acc = 1) 0x0800 - 0xxxxx 1 1 0xxxxx = 0x00_ffff - mcu_xgxsramsize. 0x78_0800 - 0x78_xxxx flash (blkx) if (mcu_xgate_ftx_acc = 0) illegal address illegal address sram 0xyyyy 2 - 0xffff 2 0xyyyy = 0x01_0000 - mcu_xgxsramsize. 0x0f_yyyy - 0x0f_ffff 0x0000 0xffff local address global address 0x00_0000 0x7f_ffff a glob(a) glob (a[15:0],gpage) = {gpage, a[15:0]} glob (a[15:0],bdmgpr) = {bdmgpr, a[15:0]} gpage glob or bdmgpr glob(0xffff) glob(0x0000) misaligned word access to the address 0xffff results into two byte accesses: glob(0xffff) followed by glob(0x0000) 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 918 freescale semiconductor 25.6.2.5 prr accesses registers used for emulation purposes must be rebuilt by the emulator hardware to achieve full emulation of normal mode operation. these registers are called port replacement registers (prrs). for accesses of internal prrs, the xbus2 is reserved for the two bus cycles. read and write accesses are performed in the second cycle. the ?st bus cycle is blocked and no master can access this bus (if ips_xfr_wait = 1, the current access can not be achieved in one bus cycle). in emulation mode, reads and writes to the prrs are performed to the internal registers ( xbus2_sel_ipbi = 1) during the second bus cycle) as to the external bus ( xbus3_sel_long _ebi = 1) during the 2 bus cycles. in this mode, the read data of prrs is selected from external bus ( xbus3_rdata_ebi ). due to internal visibility requirement of s12x_cpu accesses, the s12x_cpu is not acknowledged ( s12x_vaddr_cpu = 0) when another master accesses a prr. this rule applies also in normal modes to ensure that the operation of the device is the same as in emulation modes. a summary of prr accesses is the following: byte accesses and aligned word access of prrs take 2 bus cycles. a misaligned word access to prrs takes 4 bus cycles if both bytes are prrs and 3 bus cycles if one of the two bytes is not a prr. xgate prrs arbitration is performed at the next t2 cycle due to the late timing of the xgate address. the xgate address is registered to be sent to the external bus. 25.6.2.6 s12x_bdm firmware & hardware commands hardware commands are used to read and write target system memory locations by the s12x_bdm ( s12x_bdm_req = 1). two types of hardware commands to access the overlapping resources (bdm or flash) by their global address (0x7f_ff00 - 0x7f_ffff): ? bdm_hardinmap_t2 = 1) when the hardware command accesses bdm resources. ? bdm_hardinmap_t2 = 0) when the hardware command accesses flash area. firmware commands ( bdm_?minmap_t2 = 1) are used to execute ?mware codes by the s12x_cpu ( s12x_cpu_req = 1). when one of the previous signals is set, the global address through the 0x7f_ff00 - 0x7f_ffff window allows accesses to the s12x_bdm target ( xbus0_sel_bdm = 1) instead of the flash target ( xbus0_sel_ftx = 0). 25.6.3 s12x_cpu the crossbar switch supports the following s12x_cpu features: 25.6.3.1 program counter the s12x_cpu program counter is a 16 bit address ( cpu_pc[15:0] ). it is translated to the global address map ( mmc_pc_dbg[22:0] ) by the legacy translation type (see 25.6.2.4). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 919 25.6.3.2 ppage register access the cpu_selppage_t2 signal is set during a call or a rtc instruction. when this signal is asserted, the s12x_cpu accesses the ppage register at address 0x00_0030. this signal is asserted only when the s12x_cpu issues a request ( s12x_req_cpu = 1). 25.6.3.3 global instructions the cpu_global_t2 signal is set when the s12x_cpu executes a global instruction. the generated global address is the result of concatenation of the s12x_cpu local address s12x_addr_cpu[15:0] with the gpage register {gpage,s12x_addr_cpu[15:0]} . 25.6.3.4 internal visibility s12x_cpu transactions (read, write) are made visible to the emulation board to allow emulation of the s12x_cpu activities, except accesses to the s12x_bdm target (firmware, registers) which are not made visible. if (s12x_req_cpu = 1 and bdm_firminmap_t2 = 1 and mode = (emulation or special test)) then xbus3_sel_vis = 0 end if this feature asserts ( xbus3_sel_vis = 1) when: all targets except (s12x_bdm resources) acknowledged by the s12x_cpu transaction. the system is in emulation mode or in special test mode. in case of s12x_cpu misaligned word access, the internal visibility will be applied to the split accesses and not to the whole misaligned access, which allows other higher priority masters to access the external bus between the two byte accesses. 25.6.3.5 misaligned word access misaligned word accesses are split into two target byte accesses, except for a fast memory transfer access ( mcu_fmts = 1) which performs this access into one cycle. misaligned word accesses to the last location 0xffff of any global page gpage (64 kilobyte) by using global instructions, are performed by accessing the last byte of the page (gpage,0xffff) and the ?st byte of the same page (gpage,0x0000). 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 920 freescale semiconductor figure 25-39. cpu misaligned access & internal visibility 25.6.3.6 swap mechanism the s12x_mmc provides the functionality to split 16-bit accesses into two byte-wide operations when needed. the s12x_cpu is halted during the second cycle of the two cycle access. for read operations the s12x_mmc takes care of the swapping and holding the read data bus. the s12x_cpu therefore receives the data in the correct place on its read data bus. the swap mechanism is performed when s12x_cpu executes a read command of a misaligned word, or for a high byte (see table 25-34 ). table 25-34 describes the data format of all masters in case of read or write command. table 25-34. masters data format wdata, rdata 1 srdata 2 command addr[0] sz8 [15:8] [7:0] [15:8] [7:0] description read/write 0 0 data[15:8] data[7:0] data[15:8] data[7:0] word aligned access 1 data[15:8] data[7:0] data[7:0] data[15:8] word misaligned access 3 0 1 data[15:8] data[15:8] high byte access 1 data[7:0] data[7:0] low byte access g(addr_cpu) g(addr_cpu+1) data[15:0] data[15:8] xbus3_sel_long_ebi xbus3_addr_ebi xbus3_sz8_ebi xbus3_sel_vis mmc_ebi_acc 001 001 100 xbus3_rdata_vis s12x0_addr_cpu[0] = 1?1 s12x0_req_cpu s12x0_addr_cpu s12x0_rwb_cpu s12x0_sz8_cpu s12x0_vaddr_cpu s12x0_srdata_cpu addr_cpu data[15:0] 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 921 25.6.3.7 illegal accesses all non implemented pages are called unimplemented areas. external space is the area de?ed by the global address range 0x14_0000 to 0x3f_ffff. in expanded modes except emulation single-chip mode, accesses of global addresses which are not occupied by the on-chip resources (unimplemented areas or external space) result in accesses to the external bus. in emulation single-chip mode, accesses of global addresses which are not occupied by the on-chip resources (unimplemented areas) result in accesses to the external bus. accesses of external space result in an illegal access reset ( mmc_illegal_addr_reset_t2 = 1). in single-chip modes an access of unimplemented areas or external space by the s12x_cpu (except ?mware commands) results in an illegal access reset ( mmc_illegal_addr_reset_t2 = 1). some areas in xsram are considered protected against s12x_cpu write accesses. any write access to this areas results generation of an interrupt (see table 25-35 ). in the case of illegal s12x_cpu access to protected ram areas, the xsram doesnt receive a request ( xram_req = 0). this transaction will be acknowledged ( s12x_vaddr_cpu = 1) but not performed. 25.6.4 s12x_bdm the crossbar switch supports the following s12x_bdm features: 25.6.4.1 bdm steal this feature is enabled when s12x_req_bdm is continuously asserted for 128 bus cycles and ( s12x_vaddr_bdm = 0) during this time. this access raises the s12x_bdm access priority to high. 1 wdata format is common data bus format for all masters. rdata format is common data bus format for s12x_bdm, xgate and s12x_flexray. 2 srdata (swapped rdata) format is dedicated to the read data bus of s12x_cpu. 3 word misaligned access is supported only by s12x_cpu. table 25-35. s12x_cpu & ram protection scheme ramwpc.rwpe ramwpc.frcpu protected area against s12x_cpu write access system reaction 0 0 n.a. n.a. 0 1 flexray region (ramwpc.avif = 1) and ipi_int_cpuav =1 if (ramwpc.avie = 1) 1 0 xgate region 1 1 xgate region and flexray region 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 922 freescale semiconductor 25.6.4.2 global instructions the bdm_gab_t4 signal is set when the hardware command is a global instructions. the crossbar switch will concatenate the s12x_add_bdm[15:0] and the s12x_bdm global page register s12x_add_bdm[22:16] to build the global address (see section 25.6.2.4.1, ?12x_cpu & s12x_bdm address translation ). if the s12x_cpu is performing a ?mware command, the s12x_addr_cpu[15:0] will be concatenated to the s12x_bdm global page s12x_add_bdm[22:16] instead of the gpage register. 25.6.4.3 access type s12x_bdm does not support misaligned accesses. the lsb address s12x_addr_bdm[0] is always 0 in case of word access ( s12x_sz8_bdm = 0). the access types are bytes or aligned word. 25.6.4.4 illegal accesses if ( mmc_secure_t2 = 0), the whole memory map is accessible by the s12x_bdm. transactions to the unimplemented areas or external space in single chip modes (mode = ns, ss, es) are performed and acknowledged. the result of the transactions in normal single chip mode (mode = ns, ss) are considered garbage. 25.6.5 xgate 25.6.5.1 access type xgate does not support misaligned access. the access types are bytes or aligned word. in case of misaligned word access, xgate will be acknowledged ( xgate_ack = 1) and ( xgate_ill_access = 11) (see section 25.6.5.2, ?llegal accesses ) 25.6.5.2 illegal accesses table 25-36 describes the two types of illegal xgate accesses. the signal xgate_ill_access[1] is set when the illegal access is related to load/store instructions. the signal xgate_ill_access[0] is set when the illegal access is related to opcode or vector fetch. some areas in xsram are considered protected against xgate write accesses. any write access to this areas results to a generation of illegal load/store ( xgate_ill_access[1] = 1) (see table 25-37 ) table 25-36. illegal xgate access xgate access xgate_ill_access[1] (for load/store) xgate_ill_access[0] (for opcode or vector fetch) misaligned word 1 1 register space 0 1 write to flash 1 0 secured flash in expanded modes 1 1 flash not available in the xgate memory map ( mcu_xgate_ftx_acc = 0) 11 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 923 in the case of illegal xgate access to protected ram areas, the xsram doesnt receive a request (xram_req = 0). this transaction will be acknowledged (xgate_ack = 1) but not performed. xgate prr misaligned access is aknowledged in t24 when the ?st cycle is taken. no target is selected and the xgate_ill_access[1:0] = 11. 25.6.6 s12x_flexray 25.6.6.1 access type s12x_flexray does not support misaligned access. the lsb address s12x_addr_?xray[0] is always ? . the only access type supported is word aligned ( s12x_sz8_?xray = 0). 25.6.6.2 illegal accesses most areas in global memory map are considered protected against s12x_flexray accesses. which are considered unimplemented area .any access to these areas results to a generation of an illegal access signal ( ?xray_ill_access = 1) (see table 25-38 ) in the case of illegal s12x_flexray access to protected memory areas, no targets receive a request. this transaction will be acknowledged (s12x_vaddr_?xray = 1) but not performed. table 25-37. xgate & ram protection scheme ramwpc.rwpe ramwpc.frxg protected area against xgate write access system reaction 0 0 n.a. n.a. 0 1 flexray region xgate_ill_access[1] = 1 and xgate_ack = 1 and xram_req = 1 and xram_rwb = 1 1 0 s12x_cpu region 1 1 s12x_cpu region and flexray region table 25-38. s12x_flexray & memory map protection scheme s12x_flexray address system reaction s12x_addr_?xray[22:0] < 0x0f_ramfrl_00 ?xray_ill_access = 1 and s12x_vaddr_?xray = 1 s12x_addr_?xray[22:0] > 0x0f_ramfru_ff 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 924 freescale semiconductor 25.6.7 priority scheme table 25-39 describes the target priority scheme starting from higher to lower priority. table 25-40 describes the ram target priority scheme starting from higher to lower priority in case of s12x mastere write accesses. table 25-39. priority scheme applied to each target bus priority level xbus0 (ftx0, eetx, bdm) xbus1 (ftx1) xbus2 (ipbi). xbus3 (s12x_ebi). xram (xsram) target busy available available available available available flexray (high priority) ???? available for read bdm (high priority) available ? available available available for read xgate (prr) ?? available available ? cpu available ? available available available for read xgate ? available available ? available flexray ???? available for read bdm available ? available available available for read table 25-40. priority scheme applied to ram priority level xram (xsram) target busy available flexray (high priority) available for write bdm (high priority) available for write xgate (prr) ? cpu available for write flexray available for write bdm available for write xgate available 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 925 some masters do have access limitation to some targets; all authorized target accesses to a speci? master are noted by ?vailable? all restricted target accesses are noted by ? : not available? the winner of the priority scheme is granted to access the target. this access preforms if no protection error set. in case of protection error, no other master can access this target. 25.6.8 xbus0 the xbus0 is an xbus protocol type short ( default ) connected to the targets (ftx,eetx and s12x_bdm). the access types of the xbus0 are bytes or aligned words. ftx, eetx are accessible only when the device is not secured ?n expanded modes? s12x_bdm resources are accessible only in case of ?mware or hardware accesses. ftx, eetx and s12x_bdm select-lines (xbus0_sel_ftx, xbus0_sel_eetx, xbus0_sel_bdm) are ?utually exclusive? 25.6.9 xbus1 the xbus1 is an xbus protocol type short ( default ) connected to the targets ftx for the blkx (see section , ?cu_xgate_ftx_acc ). the access types of the xbus1 are aligned words. xbus1 is a read only bus. xbus0 access to the blkx flash address range ( xbus0_sel_ftx = 1) has high priority than xbus1 access to the same address range ( xbus1_sel_ftx = 0). 25.6.10 xbus2 the xbus2 is an xbus protocol type short ( default ) connected to the target ipbi. the access types of the xbus2 are bytes or aligned words. xbus2 is busy ( xbus2_sel_ipbi = 0) during the cycle the xbus2_data_wait = 1. 25.6.11 xbus3 the xbus3 is an xbus protocol type long connected to the target s12x_ebi, which has to keep resources in the whole t2 period (due to the external bus timing). this bus supports two types of selects: 1. xbus3_sel_long_ebi : is set when an external access occurs. 2. xbus3_vis_ebi : is set when s12x_cpu is doing a transaction to a speci? target even external (see section 25.6.3.4, ?nternal visibility ). when xbus3_sel_long_ebi = 1, the allowed access types are bytes or aligned words. when xbus3_vis_ebi = 1, the access types are bytes, aligned word, misaligned word (in case of xsram accesses). two signals are sent to s12x_ebi to be used by the ?ystem stretch mechanism logic? 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 926 freescale semiconductor mmc_acc_emul_mem : this signal is set when the external access to the emulated memory needs to be processed always in one cycle (stretch 0 cycle). mmc_acc_prr : this signal is set when the access to prrs is performed in emulation mode. it informs s12x_ebi to do this access for two cycles (stretch 1 cycle). one signal is sent to s12x_ebi to provide the actual master access information to the external bus. 25.6.12 xram the xram is an xgate bus protocol connected to the target xsram. the access types to the xram bus are: bytes, aligned words and misaligned words (in case of ( mcu_fmts = 1)). bytes, aligned words (in case of ( mcu_fmts = 0)). 25.7 generic labeling scheme s12x_mmc_.... labelling scheme for the generic s12x platform. table 25-42 shows the sub-set of parameters to be used for different labelling scheme. the default s12x platform uses the default parameters in the column ?efault?(refer to figure 25-42 ) in the default case, the should be empty which means and the s12x_mmc applies the following label : s12x_mmc.... table 25-41. master access to external bus interface mmc_ebi_acc(2) mmc_ebi_acc(1) mmc_ebi_acc(0) description 00 0 repetition of the previous access only if xbus3_acc_wait = 1 except the ?st cycle. 00 1 cpu address shown to the external bus address only if (xbus3_sel_vis = 1) only during the ?st cycle 01 0 bdm address shown to the external bus address only if (xbus3_sel_long_ebi = 1) only during the ?st cycle 01 1 xgate address shown to the external bus address only if (xbus3_sel_long_ebi = 1) only during the ?st cycle 10 0 noacc (xbus3_sel_long_ebi = 0) and (xbus3_sel_vis = 0) 10 1 cpu access error cpu address shown to the external bus address only if (xbus3_sel_vis = 1) only during the ?st cycle - - - the remaining cases are not implemented 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 927 if these parameters change the default values, the tag will appear on the ?ld like its de?ed in the tag column in table 25-42 example: eagleray will have the following parameter changes: mcu_flexray = 1. s12x_mmc applies the following label: s12x_mmc_?1.... bonito will have the following parameter changes: mcu_xgate_ftx_acc = 0 mcu_ebi = 0 s12x_mmc applies the following label: s12x_mmc_xfa0ebi0.... table 25-42. generic architecture parameters for label con?uration default tag 1 1 tags are used for label scripting to distinguish between different con?urable architectures. mcu_xgate 1?1 xg0 mcu_xgate_ftx_acc 2 2 this parameter is valid only when mcu_xgate = 1?1. 1?1 xfa0 mcu_flexray 1?0 ?1 mcu_ebi 1?1 ebi0 mcu_fmts 1?1 fmt0 mcu_ipbi_xfr_wait 1?0 xfr1 4 .com u datasheet
chapter 25 memory mapping control (s12xmmcv3) MC9S12XHZ512 data sheet, rev. 1.02 928 freescale semiconductor 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 929 appendix a electrical characteristics a.1 general note the electrical characteristics given in this section should be used as a guide only. values cannot be guaranteed by freescale and are subject to change without notice. this supplement contains the most accurate electrical information for the MC9S12XHZ512 microcontroller available at the time of publication. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classi?ation the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classi?ation is used and the parameters are tagged accordingly in the tables where appropriate. note this classi?ation is shown in the column labeled ??in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the MC9S12XHZ512 utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, and pll as well as the digital core. the v dda , v ssa pair supplies the a/d converter and parts of the internal voltage regulator. the v ddx1 /v ssx1 and v ddx2 /v ssx2 pairs supply the i/o pins except pu, pv and pw. v ddr supplies the internal voltage regulator. v ddm1 /v ssm1 , v ddm2 /v ssm2 and v ddm3 /v ssm3 pairs supply the ports pu, pv and pw. 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 930 freescale semiconductor v dd1 ,v ss1 and v ss2 are the supply pins for the digital logic, v ddpll ,v sspll supply the oscillator and the pll. v ss1 and v ss2 are internally connected by metal. v dda , v ddx1 , v ddx2 , v ddm as well as v ssa , v ssx1 , v ssx2 and v ssm are connected by anti-parallel diodes for esd protection. note in the following context v dd5 is used for either v dda , v ddm , v ddr and v ddx1/2 ; v ss5 is used for either v ssa , v ssr and v ssx unless otherwise noted. i dd5 denotes the sum of the currents ?wing into the v dda , v ddx1/2 , v ddm and v ddr pins. v dd is used for v dd1 and v ddpll ,v ss is used for v ss1 ,v ss2 and v sspll . i dd is used for the sum of the currents ?wing into v dd1 and v ddpll . a.1.3 pins there are four groups of functional pins. a.1.3.1 i/o pins those i/o pins have a nominal level of 5 v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins.the internal structure of all those pins is identical; however, some of the functionality may be disabled. for example, for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this group is made up by the v rh and v rl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5 v level. they are supplied by v ddpll . a.1.3.4 test this pin is used for production testing only. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd5 ) is greater than i dd5 , the injection current may ?w out of v dd5 and could result in external power supply going out of regulation. ensure external v dd5 load will shunt current greater than maximum injection current. this will be the 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 931 greatest risk when the mcu is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1. absolute maximum ratings 1 1 beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 ?.3 6.0 v 2 digital logic supply voltage 2 2 the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd ?.3 3.0 v 3 pll supply voltage 2 v ddpll ?.3 3.0 v 4 voltage difference v ddx to v ddr and v dda ? vddx ?.3 0.3 v 5 voltage difference v ssx to v ssr and v ssa ? vssx ?.3 0.3 v 6 digital i/o input voltage v in ?.3 6.0 v 7 analog reference v rh, v rl ?.3 6.0 v 8 xfc, extal, xtal inputs v ilv ?.3 3.0 v 9 test input v test ?.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins except port u, v and w 3 3 all digital i/o pins are internally clamped to v ssx1/2 and v ddx1/2 or v ssa and v dda . i d ?5 +25 ma 10 instantaneous maximum current single pin limit for port u, v and w 4 4 ports u, v and w are internally clamped to v ssm1/2/3 and v ddm1/2/3 . i d ?5 +55 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 5 5 those pins are internally clamped to v sspll and v ddpll . i dl ?5 +25 ma 12 instantaneous maximum current single pin limit for test 6 6 this pin is clamped low to v sspll , but not clamped high. this pin must be tied low in applications. i dt ?.25 0 ma 13 storage temperature range t stg ?5 155 c 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 932 freescale semiconductor a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device quali?ation esd stresses were performed for the human body model (hbm) and the charge device model. a device will be de?ed as a failure if after exposure to esd pulses the device no longer meets the device speci?ation. complete dc parametric and functional testing is performed per the applicable device speci?ation at room temperature followed by hot temperature, unless speci?d otherwise in the device speci?ation. table a-2. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative 3 3 latch-up minimum input voltage limit ?.5 v maximum input voltage limit 7.5 v table a-3. esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 v 2 c charge device model (cdm) v cdm 500 v 3 c latch-up current at t a = 125 c positive negative i lat +100 ?00 ma 4 c latch-up current at t a = 27 c positive negative i lat +200 ?00 ma 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 933 a.1.7 operating conditions this section describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8, ?ower dissipation and thermal characteristics . table a-4. operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 4.5 5 5.5 v digital logic supply voltage 1 1 the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage 2 v ddpll 2.35 2.5 2.75 v voltage difference v ddx to v ddr and v dda ? vddx ?.1 0 0.1 v voltage difference v ssx to v ssr and v ssa ? vssx ?.1 0 0.1 v oscillator f osc 0.5 16 mhz bus frequency f bus 0.5 40 mhz MC9S12XHZ512 c operating junction temperature range operating ambient temperature range 2 2 please refer to section a.1.8, ?ower dissipation and thermal characteristics for more details about the relation between ambient temperature t a and device junction temperature t j . t j t a ?0 ?0 27 100 85 c MC9S12XHZ512 v operating junction temperature range operating ambient temperature range 2 t j t a ?0 ?0 27 120 105 c MC9S12XHZ512 m operating junction temperature range operating ambient temperature range 2 t j t a ?0 ?0 27 140 125 c 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 934 freescale semiconductor a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: the total power dissipation can be calculated from: two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled p io is the sum of all output currents on i/o ports associated with v ddx and v ddr . for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in table a-9 and not the overall current ?wing into v ddr , which additionally contains the current ?wing into the external loads with output high. p io is the sum of all output currents on i/o ports associated with v ddx and v ddr . t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = p int i dd v dd ? i ddpll v ddpll ? i dda +v dda ? + = p io r dson i i io i 2 ? = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd5 v oh i oh ------------------------------------ for outputs driven high ; = p int i ddr v ddr ? i dda v dda ? + = p io r dson i i io i 2 ? = 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 935 a.1.9 i/o characteristics this section describes the characteristics of all i/o pins except extal, xtal,xfc,test and supply pins. table a-5. thermal package characteristics 1 1 the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit lqfp144 1 t thermal resistance lqfp144, single sided pcb 2 ja 41 c/w 2 t thermal resistance lqfp144, double sided pcb with 2 internal planes 3 ja 32 c/w 3 junction to board lqfp 144 jb 22 c/w 4 junction to case lqfp 144 4 jc 7.4 c/w 5 junction to package top lqfp144 5 jt 3 c/w lqfp112 6 t thermal resistance lqfp112, single sided pcb 2 2 junction to ambient thermal resistance, ja was simulated to be equivalent to the jedec speci?ation jesd51-2 in a horizontal con?uration in natural convection. ja 43 c/w 7 t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3 junction to ambient thermal resistance, ja was simulated to be equivalent to the jedec speci?ation jesd51-7 in a horizontal con?uration in natural convection. ja 32 c/w 8 junction to board lqfp112 jb 22 c/w 9 junction to case lqfp112 4 jc 7 c/w 10 junction to package top lqfp112 5 jt 3 c/w 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 936 freescale semiconductor table a-6. i/o characteristics conditions are 4.5 v < v dd5 < 5.5 v temperature from ?0 c to +140 c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 v t v dd5 + 0.3 v 2 p input low voltage v il 0.35*v dd5 v tv ss5 ?0.3 v 3 c input hysteresis v hys 250 mv 4 p input leakage current (input mode) 1 v in = v dd5 or v ss5 all i/o pins except port u, v, w port u , v and w 1 maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temper ature range from 50 c to 125 c. i in ? ?.5 1 2.5 a a 5 c p p output high voltage (output mode) partial drive: i oh = ? ma full drive: i oh = ?0 ma port u, v, w: i oh = ?0 ma v oh v dd5 ?0.8 v dd5 ?0.8 v dd5 0.32 v dd5 ?0.2 v v v 6 c p output low voltage (output mode) partial drive: i ol = +2 ma full drive: i ol = +10 ma port u, v, w: i oh = +20 ma v ol 0.2 0.8 0.8 0.32 v v v 7 c output rise time ( slew enabled) v dd5 =5v, r load =1k ? , 10% to 90% of v oh partial drive full drive port u, v, w t r 50 25 50 75 35 100 100 50 150 ns ns ns 8 c output fall time ( slew enabled) v dd5 =5v, r load =1k ? , 10% to 90% of v oh partial drive full drive port u, v, w t f 50 25 50 75 35 100 100 50 150 ns ns ns 9 p internal pull up device current, tested at v il max i pul ?30 a 10 c internal pull up device current, tested at v ih min i puh ?0 a 11 p internal pull down device current, tested at v ih min i pdh 130 a 12 c internal pull down device current, tested at v il max i pdl 10 a 13 d input capacitance c in ?pf 14 t injection current 2 single pin limit total device limit, sum of all injected currents 2 refer to section a.1.4, ?urrent injection for more details i ics i icp ?.5 ?5 2.5 25 ma 15 p port ad interrupt input pulse ?tered 3 passed 3 3 parameter only applies in stop or pseudo stop mode. t pulse 10 3 s s 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 937 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode and the cpu and xgate code is executed from ram, v dd5 =5.5v, internal voltage regulator is enabled and the bus frequency is 40mhz using a 4-mhz oscillator in loop controlled pierce mode. production testing is performed using a square wave signal at the extal input. table a-7. i/o characteristics for port c, d, pe5, pe6, and pe7 for reduced input voltage thresholds conditions are 4.5 v < v dd5 < 5.5 v temperature from ?0 c to +140 c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 1.75 v 2 p input low voltage v il 0.75 v 3 c input hysteresis v hys 100 mv 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 938 freescale semiconductor table a-8. shows the con?uration of the peripherals for run current measurement. table a-8. peripheral con?urations for run supply current measurements peripheral con?uration mscan con?ured to loop-back mode using a bit rate of 1mbit/s spi con?ured to master mode, continously transmit data (0x55 or 0xaa) at 1mbit/s sci con?ured into loop mode, continously transmit data (0x55) at speed of 57600 baud iic operate in master mode and continously transmit data (0x55 or 0xaa) at the bit rate of 100kbit/s pwm con?ured to toggle its pins at the rate of 40khz ect the peripheral shall be con?ured to output compare mode, pulse accumulator and modulus counter enabled. atd the peripheral is con?ured to operate at its maximum speci?d frequency and to continuously convert voltages on all input channels in sequence. xgate xgate fetches code from ram, xgate runs in an in?ite loop , it reads the status and flag registers of cans, spis, scis in sequence and does some bit manipulation on the data cop cop warchdog rate 2 24 rti enabled, rti control register (rtictl) set to $ff api the module is con?ured to run from the rc oscillator clock source. pit pit is enabled, micro-timer register 0 and 1 loaded with $0f and timer registers 0 to 3 are loaded with $03/07/0f/1f. dbg the module is enabled and the comparators are con?ured to trigger in outside range. the range covers all the code executed by the core. 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 939 a.1.10.2 additional remarks in expanded modes the currents ?wing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be given. a very good estimate is to take single chip currents and add the currents due to the external loads. table a-9. run and wait current characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit run supply current (peripheral con?uration see table a-8.) 1 p peripheral set 1 f osc =4mhz, f bus =40mhz i dd5 110 ma 2 c t t peripheral set 1 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 1 the following peripherals are on: atd/ect/iic0/pwm/spi/sci0-sci1/can0-can1/xgate 90 45 18 3 t t t peripheral set 2 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 2 the following peripherals are on: atd/ect/iic0/pwm/spi/sci0-sci1/can0-can1 70 35 15 4 t t t peripheral set 3 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 3 the following peripherals are on: atd/ect/iic0/pwm/spi/sci0-sci1 60 30 13 5 t t t peripheral set 4 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 4 the following peripherals are on: atd/ect/iic0/pwm/spi 56 28 12 6 t t t peripheral set 5 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 5 the following peripherals are on: atd/ect/iic0/pwm 53 26 11 7 t t t peripheral set 6 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =20mhz f osc =4mhz, f bus =8mhz 6 the following peripherals are on: atd/ect/iic0 50 25 10 wait supply current 8 p peripheral set 1 ,pll on xgate executing code from ram i ddw 95 ma 9 t t peripheral set 2 f osc =4mhz, f bus =40mhz f osc =4mhz, f bus =8mhz 50 10 10 p all modules disabled, rti enabled, pll off 10 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 940 freescale semiconductor table a-10. pseudo stop and full stop current conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit pseudo stop current (api, rti, and cop disabled) pll off 10 c p c c p c p c p ?0 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i ddps 200 300 400 500 600 800 1000 1200 1500 500 2500 3500 7000 a pseudo stop current (api, rti, and cop enabled) pll off 11 c c c c c c c ?0 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps 500 750 850 1000 1200 1500 2000 a stop current 12 c p c c p c p c p ?0 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i dds 20 30 100 200 250 400 500 600 1000 100 2000 3000 7000 a 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 941 a.2 atd this section describes the characteristics of the analog-to-digital converter. a.2.1 atd operating characteristics the table a-11 and table a-13 show conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer ampli?r can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. a.2.2 factors in?encing accuracy three factors ?source resistance, source capacitance and current injection ?have an in?ence on the accuracy of the atd. a.2.2.1 source resistance due to the input pin leakage current as speci?d in table a-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s speci?s results in an error of less than 1/2 lsb (2.5 mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. table a-11. atd operating characteristics conditions are shown in table a-4 unless otherwise noted, supply voltage 4.5 v < v dda < 5.5 v num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2 c differential reference voltage 1 1 full accuracy is not guaranteed when differential voltage is less than 4.50 v v rh -v rl 4.50 5.00 5.5 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4 d atd 10-bit conversion period clock cycles 2 conv, time at 2.0 mhz atd clock f atdclk 2 the minimum time assumes a ?al sample period of 2 atd clocks cycles while the maximum time assumes a ?al sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles s 5 d atd 8-bit conversion period clock cycles 2 conv, time at 2.0 mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles s 6 d recovery time (v dda = 5.0 volts) t rec 20 s 7 p reference supply current i ref 0.375 ma 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 942 freescale semiconductor a.2.2.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external ?ter capacitor, c f 1024 * (c ins ? inn ). a.2.2.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than speci?d as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as: v err = k * r s * i inj with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table a-12. atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s 1k ? 2 t total input capacitance non sampling sampling c inn c ins 10 22 pf 3 c disruptive analog input current i na ?.5 2.5 ma 4 c coupling ratio positive current injection k p 10 -4 a/a 5 c coupling ratio negative current injection k n 10 -2 a/a 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 943 a.2.3 atd accuracy table a-13 speci?s the atd conversion performance excluding any errors due to current injection, input capacitance, and source resistance. a.2.3.1 atd accuracy de?itions for the following de?itions see also figure a-1 . differential non-linearity (dnl) is de?ed as the difference between two adjacent switching steps. the integral non-linearity (inl) is de?ed as the sum of all dnls: table a-13. atd conversion performance conditions are shown in table a-4 unless otherwise noted v ref = v rh ? rl = 5.12 v. resulting to one 8-bit count = 20 mv and one 10-bit count = 5 mv f atdclk = 2.0 mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl ? 1 counts 3 p 10-bit integral nonlinearity inl ?.5 1.5 2.5 counts 4 p 10-bit absolute error (port ad) 1 1 these values include the quantization error which is inherently 1/2 count for any a/d converter. ae ? 2.0 3 counts 5 p 10-bit absolute error (port l) 1 ae ? 3.0 4 counts 6 p 8-bit resolution lsb 20 mv 7 p 8-bit differential nonlinearity dnl ?.5 0.5 counts 8 p 8-bit integral nonlinearity inl ?.0 0.5 1.0 counts 9 p 8-bit absolute error (port ad) 1 ae ?.5 1.0 1.5 counts 9 p 8-bit absolute error (port l) 1 ae ?.0 1.5 2.0 counts dnl i () v i v i1 1lsb -------------------------- - 1 = inl n () dnl i () i1 = n v n v 0 1lsb -------------------- - n == 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 944 freescale semiconductor figure a-1. atd accuracy de?itions note figure a-1 shows only de?itions, for speci?ation values refer to table a-13 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 50 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb vi-1 vi dnl 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 945 a.3 nvm, flash, and eeprom note unless otherwise noted the abbreviation nvm (nonvolatile memory) is used for both flash and eeprom. a.3.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the speci?d minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits speci?d as f nvmop . the minimum program and erase times shown in table a-14 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2 mhz. a.3.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.3.1.2 burst programming this applies only to the flash where up to 64 words in a row can be programmed consecutively using burst programming by keeping the command pipeline ?led. the time to program a consecutive word can be calculated as: the time to program a whole row is: burst programming is more than 2 times faster than single word programming. t swpgm 9 1 f nvmop ------------------------- ? 25 1 f bus ----------- - ? + = t bwpgm 4 1 f nvmop ------------------------- ? 9 1 f bus ----------- - ? + = t brpgm t swpgm 63 t bwpgm ? + = 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 946 freescale semiconductor a.3.1.3 sector erase erasing a 1024-byte flash sector or a 4-byte eeprom sector takes: the setup time can be ignored for this operation. a.3.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.3.1.5 blank check the time it takes to perform a blank check on the flash or eeprom is dependant on the location of the ?st non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. t era 4000 1 f nvmop ------------------------- ? t mass 20000 1 f nvmop ------------------------- ? t check location t cyc 10 t cyc ? + ? 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 947 table a-14. nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 80 1 1 restrictions for oscillator in crystal mode apply. mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2 minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 3 maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections section a.3.1.1, ?ingle word programming section a.3.1.4, ?ass erase for guidance. s 5 d flash burst programming consecutive word 4 4 burst programming operations are not applicable to eeprom t bwpgm 20.4 2 ?1 3 s 6 d flash burst programming time for 64 words 4 t brpgm 1331.2 2 2027.5 3 s 7 p sector erase time t era 20 5 5 minimum erase times are achieved under maximum nvm operating frequency, f nvmop . 26.7 3 ms 8 p mass erase time t mass 100 5 133 3 ms 9 d blank check time flash per block t check 11 6 6 minimum time, if ?st word in the array is not blank 65546 7 7 maximum time to complete check on an erased block t cyc 10 d blank check time eeprom per block t check 11 6 2058 7 t cyc 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 948 freescale semiconductor a.3.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during quali?ation, constant process monitors and burn-in to screen early life failures. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed table a-15. nvm reliability characteristics 1 1 t javg will not exeed 85 c considering a typical temperature pro?e over the lifetime of a consumer, industrial or automotive application. conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit flash reliability characteristics 1 c data retention after 10,000 program/erase cycles at an average junction temperature of t javg 85 c t flret 15 100 2 2 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale de?es typical data retention, please refer to engineering bulletin eb618. years 2 c data retention with <100 program/erase cycles at an average junction temperature t javg 85 c 20 100 2 3 c number of program/erase cycles (?0 c t j 0 c) n fl 10,000 cycles 4 c number of program/erase cycles (0 c t j 140 c) 10,000 100,000 3 3 spec table quotes typical endurance evaluated at 25 c for this product family, typical endurance at various temperature can be estimated using the graph below. for additional information on how freescale de?es typical endurance, please refer to engineering bulletin eb619. eeprom reliability characteristics 5 c data retention after up to 100,000 program/erase cycles at an average junction temperature of t javg 85 c t eepret 15 100 2 years 6 c data retention with <100 program/erase cycles at an average junction temperature t javg 85 c 20 100 2 7 c number of program/erase cycles (?0 c t j 0 c) n eep 10,000 cycles 8 c number of program/erase cycles (0 c < t j 140 c) 100,000 300,000 3 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 949 figure a-2. typical endurance vs temperature typical endurance [10 3 cycles] operating temperature t j [ c] 0 50 100 150 200 250 300 350 400 450 500 -40 -20 0 20 40 60 80 100 120 140 ------ flash ------ eeprom 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 950 freescale semiconductor a.4 voltage regulator table a-16. voltage regulator electrical characteristics num c characteristic symbol min typ max unit 1 p input voltages v vddr,a 4.5 5.5 v 3 p output voltage core full performance mode reduced power mode shutdown mode v dd 2.35 1.4 2.54 2.25 1 1 high impedance output 2.75 2.75 v v v 4 p output voltage pll full performance mode reduced power mode shutdown mode v ddpll 2.35 1.25 2.54 2.25 2 2 high impedance output 2.75 2.75 v v v 7 p low-voltage interrupt 3 assert level deassert level 3 monitors v dda , active only in full performance mode. indicates i/o and adc performance degradation due to low supply voltage. v lvia v lvid 4.0 4.15 4.37 4.52 4.66 4.77 v v 8 p low-voltage reset 4 assert level 4 monitors v dd , active only in full performance mode. mcu is monitored by the por in rpm (see figure a-1 ) v lvra 2.25 v 9 c power-on reset 5 assert level deassert level 5 monitors v dd . active in all modes. v pora v pord 0.97 2.05 v v 12 c trimmed api internal clock 6 ? f / f nominal 6 the api trimming bits must be set that the minimum periode equals to 0.2 ms. f nominal = 1/0.2ms df api ?10% + 10% 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 951 a.5 reset, oscillator, and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (pll). a.5.1 startup table a-17 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block guide. a.5.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.5.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when v dd5 is out of speci?ation limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg ?gs register has not been set. a.5.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. a.5.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. table a-17. startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d reset input pulse width, minimum input time pw rstl 2t osc 2 d startup from reset n rst 192 196 n osc 3 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 4 d wait recovery startup time t wrs 14 t cyc 5 d fast wakeup from stop 1 1 v dd1 ?ter capacitor 220 nf, v dd5 = 5 v, t= 25 c t fws ?0 s 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 952 freescale semiconductor if the mcu is woken-up by an interrupt and the fast wake-up feature is enabled (fstwkp = 1 and scme = 1), the system will resume operation in self-clock mode after t fws . a.5.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. a.5.2 oscillator the device features an internal low-power loop controlled pierce oscillator and a full swing pierce oscillator/external clock mode. the selection of loop controlled pierce oscillator or full swing pierce oscillator/external clock depends on the xclks signal which is sampled during reset. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout speci?s the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa. 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 953 table a-18. oscillator characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (loop controlled pierce) f osc 4.0 16 mhz 1b c crystal oscillator range (full swing pierce) 1, 2 1 depending on the crystal a damping series resistor might be necessary 2 xclks = 0 f osc 0.5 40 mhz 2 p startup current i osc 100 a 3 c oscillator start-up time (loop controlled pierce) t uposc 3 3 f osc = 4 mhz, c = 22 pf. 50 4 4 maximum value is for extreme cases using high q, low frequency crystals ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 khz 6 p external square wave input frequency f ext 0.5 80 mhz 7 d external square wave pulse width low t extl 5ns 8 d external square wave pulse width high t exth 5ns 9 d external square wave rise time t extr 1ns 10 d external square wave fall time t extf 1ns 11 d input capacitance (extal, xtal inputs) c in ?pf 12 p extal pin input high voltage 5 5 if full swing pierce oscillator/external clock circuitry is used. ( xclks = 0) v ih,extal 0.75* v ddpll v t extal pin input high voltage 5 v ih,extal v ddpll + 0.3 v 13 p extal pin input low voltage 5 v il,extal 0.25* v ddpll v t extal pin input low voltage 5 v il,extal v sspll 0.3 v 14 c extal pin input hysteresis 5 v hys,extal 250 mv 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 954 freescale semiconductor a.5.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.5.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good ?ter characteristics. figure a-3. basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table a-19 . the grey boxes show the calculation for f vco = 80 mhz and f ref = 4 mhz. for example, these frequencies are used for f osc = 4-mhz and a 40-mhz bus clock. the vco gain at the desired vco frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. the loop bandwidth f c should be chosen to ful?l the gardners stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. f osc f ref phase detector vco kv 1 synr+1 f vco loop divider kf 1 2 d fcmp c s r c p v ddpll xfc pin 1 refdv+1 k v k 1 e f 1 f vco () k 1 1v ? --------------------------- - ? = 195mhz v ? e 126 80 195 -------------------- - ? = = -154.0mhz/v k i ch k v ? 3.5 a 154mhz v ? () ? 539.1hz ? ? == = 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 955 and ?ally the frequency relationship is de?ed as with the above values the resistance can be calculated. the example is shown for a loop bandwidth f c = 20 khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: a.5.3.2 jitter information the basic functionality of the pll is shown in figure a-3 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-4 . figure a-4. jitter de?itions f c 2 f ref ?? 1 2 + + ?? ?? ? ------------------------------------------ - 1 10 ----- - f c f ref 410 ? ------------- 0.9 = () ; < ? < f c < 100khz n f vco f ref --------------- 2 s y n r 1 + () ? == = 20 r 2 nf c ??? k ----------------------------- 2 20 20khz ?? ? 539.1hz ()? ? ------------------------------------------ 4.7k ? = = = c s 2 2 f c r ?? ---------------------- - 0.516 f c r ? -------------- - 0.9 = () ; == = 5.5nf = ~ 4.7nf c s 20 ------ c p c s 10 ------ ? c p = 470pf 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 956 freescale semiconductor the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). de?ing the jitter as: for n < 1000, the following equation is a good ? for the maximum jitter: figure a-5. maximum bus clock jitter approximation this is very important to notice with respect to timers, serial modules where a prescaler will eliminate the effect of the jitter to a large extent. jn () max 1 t max n () nt nom ? ---------------------- - 1 t min n () nt nom ? ---------------------- - , ?? ?? ?? = jn () j 1 n -------- j 2 + = 1 5 10 20 n j(n) 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 957 a.6 lcd table a-19. pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 80 mhz 3 d lock detector transition from acquisition to tracking mode |? trk |3 4% 1 1 % deviation from target frequency 4 d lock detection |? lock | 0 1.5 % 1 5 d unlock detection |? unl | 0.5 2.5 % 1 6 d lock detector transition from tracking to acquisition mode |? unt |6 8% 1 7 c pllon total stabilization delay (auto mode) 2 2 f osc = 4 mhz, f bus = 40 mhz equivalent f vco = 80 mhz: refdv = #$00, synr = #$09, c s = 4.7 nf, c p = 470 pf, r s = 4.7 k ? t stab 0.24 ms 8 d pllon acquisition mode stabilization delay 2 t acq 0.09 ms 9 d pllon tracking mode stabilization delay 2 t al 0.16 ms 10 d fitting parameter vco loop gain k 1 ?95 mhz/v 11 d fitting parameter vco loop frequency f 1 126 mhz 12 d charge pump current acquisition mode | i ch | 38.5 a 13 d charge pump current tracking mode | i ch | 3.5 a 14 c jitter ? parameter 1 2 j 1 0.9 1.3 % 15 c jitter ? parameter 2 2 j 2 0.02 0.12 % table a-20. lcd driver electrical characteristics characteristic symbol min. typ. max. unit lcd supply voltage vlcd -0.25 - vddx + 0.25 v lcd output impedance(bp[3:0],fp[31:0]) for outputs to charge to higher voltage level or to gnd 1 1 outputs measured one at a time, low impedance voltage source connected to the vlcd pin. z bp/fp - - 5.0 k ? lcd output current (bp[3:0],fp[31:0]) for outputs to discharge to lower voltage level except gnd 2 2 outputs measured one at a time, low impedance voltage source connected to the vlcd pin. i bp/fp 50 - - ua 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 958 freescale semiconductor a.7 mscan a.8 spi timing this section provides electrical parametrics and ratings for the spi. in table a-22 the measurement conditions are listed. a.8.1 master mode in figure a-6 the timing diagram for master mode with transmission format cpha = 0 is depicted. figure a-6. spi master timing (cpha = 0) in figure a-7 the timing diagram for master mode with transmission format cpha=1 is depicted. table a-21. mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wakeup dominant pulse ?tered t wup 2 s 2 p mscan wakeup dominant pulse pass t wup 5 s table a-22. measurement conditions description value unit drive mode full drive mode load capacitance c load 1 , on all outputs 1 timing speci?d for equal load on all spi output pins. avoid asymmetric load. 50 pf thresholds for delay measurement points (20% / 80%) v ddx v sck (output) sck (output) miso (input) mosi (output) ss1 (output) 1 9 5 6 msb in2 bit 6 . . . 1 lsb in msb out2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1. if con?ured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 12 12 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 959 figure a-7. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in2 bit 6 . . . 1 lsb in master msb out2 master lsb out bit 6 . . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss1 (output) 2 12 13 3 1.if con?ured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 960 freescale semiconductor in table a-23 the timing characteristics for master mode are listed. a.8.2 slave mode in figure a-8 the timing diagram for slave mode with transmission format cpha = 0 is depicted. figure a-8. spi slave timing (cpha = 0) table a-23. spi master mode timing characteristics num c characteristic symbol min typ max unit 1 d sck frequency f sck 1/2048 1 / 2f bus 1 d sck period t sck 2 2048 t bus 2 d enable lead time t lead 1/2 t sck 3 d enable lag time t lag 1/2 t sck 4 d clock (sck) high or low time t wsck 1/2 t sck 5 d data setup time (inputs) t su 8ns 6 d data hold time (inputs) t hi 8ns 9 d data valid after sck edge t vsck 29 ns 10 d data valid after ss fall (cpha = 0) t vss 15 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r 8 ns 13 d rise and fall time outputs t rfo 8 ns sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not de?ed 12 12 11 see 13 note 8 10 see note 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 961 in figure a-9 the timing diagram for slave mode with transmission format cpha = 1 is depicted. figure a-9. spi slave timing (cpha = 1) in table a-24 the timing characteristics for slave mode are listed. table a-24. spi slave mode timing characteristics num c characteristic symbol min typ max unit 1 d sck frequency f sck dc 1 / 4f bus 1 d sck period t sck 4 t bus 2 d enable lead time t lead 4 t bus 3 d enable lag time t lag 4 t bus 4 d clock (sck) high or low time t wsck 4 t bus 5 d data setup time (inputs) t su 8 ns 6 d data hold time (inputs) t hi 8 ns 7 d slave access time (time to data active) t a 20 ns 8 d slave miso disable time t dis 22 ns 9 d data valid after sck edge t vsck 29 + 0.5 ? t bus 1 1 0.5 t bus added due to internal synchronization delay ns 10 d data valid after ss fall t vss 29 + 0.5 ? t bus 1 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r 8 ns 13 d rise and fall time outputs t rfo 8 ns sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not de?ed slave 7 8 see note 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 962 freescale semiconductor a.9 external bus timing the following conditions are assumed for all following external bus timing values: crystal input within 45% to 55% duty equal loads of pins pad full drive (reduced drive must be off) a.9.1 normal expanded mode (external wait feature disabled) figure a-10. example 1a: normal expanded mode ?read followed by write csx addrx re datax addr1 addr2 (read) data1 (write) data2 we ew ait uds, lds 1 3 5 6 7 1 9 8 10 11 2 4 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 963 table a-25. example 1a: normal expanded mode timing v dd5 = 5.0 v ( ew aite = 0) no. c characteristic symbol min max unit frequency of internal bus f i d.c. 40.0 mhz internal cycle time t cyc 25 ns frequency of external bus f o d.c. 20.0 mhz 1 external cycle time (selected by exstr) t cyce 50 ns 2 d address 1 valid to re fall 1 includes the following signals: addrx, uds, lds, and csx. t adre 5ns 3 d pulse width, re pw re 35 ns 4 d address 1 valid to we fall t adwe 5ns 5 d pulse width, we pw we 23 ns 6 d read data setup time (if ithrs = 0) t dsr 24 ns d read data setup time (if ithrs = 1) t dsr 28 ns 7 d read data hold time t dhr 0ns 8 d read enable access time t accr 11 ns 9 d write data valid to we fall t wdwe 7ns 10 d write data setup time t dsw 31 ns 11 d write data hold time t dhw 8ns 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 964 freescale semiconductor a.9.2 normal expanded mode (external wait feature enabled) figure a-11. example 1b: normal expanded mode ?stretched read access csx addrx re datax addr1 (read) data1 we ew ait uds, lds 3 6 7 1 8 2 addr2 12 13 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 965 figure a-12. example 1b: normal expanded mode ?stretched write access csx addrx re datax (write) data1 we ew ait uds, lds 5 1 9 10 11 4 addr1 addr2 12 13 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 966 freescale semiconductor table a-26. example 1b: normal expanded mode timing v dd5 = 5.0 v ( ew aite = 1) no. c characteristic symbol 2 stretch cycles 3 stretch cycles unit min max min max frequency of internal bus f i d.c. 40.0 d.c. 40.0 mhz internal cycle time t cyc 25 25 ns frequency of external bus f o d.c. 13.3 d.c. 10.0 mhz external cycle time (selected by exstr) t cyce 75 100 ns 1 external cycle time (exstr+1ewait) t cycew 100 125 ns 2d address 1 valid to re fall 1 includes the following signals: addrx, uds, lds, and csx. t adre 5?ns 3d pulse width, re 2 2 affected by ew ait. pw re 85 110 ns 4d address 1 valid to we fall t adwe 5?ns 5d pulse width, we 2 pw we 73 98 ns 6 d read data setup time (if ithrs = 0) t dsr 24 24 ns d read data setup time (if ithrs = 1) t dsr 28 28 ns 7 d read data hold time t dhr 0?ns 8 d read enable access time t accr 71 86 ns 9 d write data valid to we fall t wdwe 7?ns 10 d write data setup time t dsw 81 106 ns 11 d write data hold time t dhw 8?ns 12 d address to ew ait fall t adwf 0 20 0 45 ns 13 d address to ew ait rise t adwr 37 47 62 72 ns 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 967 a.9.3 emulation single-chip mode (without wait states) figure a-13. example 2a: emulation single-chip mode ?read followed by write eclk r/ w datax addr1 ivd0 addr2 ivd1 (read) data1 (write) data2 addr3 lstrb eclk2x 1 1 2 3 4 5 6 7 8 9 10 11 12 12 addr1 acc1 addr2 acc2 addr3 data0 addr1 addr2 addr3 iqstat0 iqstat1 addr addr [19:16]/ addr [22:20]/ [15:0]/ acc [2:0] iqstat [3:0] ivd [15:0] 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 968 freescale semiconductor table a-27. example 2a: emulation single-chip mode timing v dd5 = 5.0 v ( ew aite = 0) no. c characteristic 1 1 typical supply and silicon, room temperature only symbol min max unit frequency of internal bus f i d.c. 40.0 mhz 1 cycle time t cyc 25 ns 2 d pulse width, e high pw eh 11.5 ns 3 d pulse width, e low pw el 11.5 ns 4 d address delay time t ad ?ns 5 d address hold time t ah 0ns 6 d ivdx delay time 2 2 includes also accx, iqstatx t ivdd 4.5 ns 7 d ivdx hold time 2 t ivdh 0ns 8 d read data setup time (ithrs = 1 only) t dsr 12 ns 9 d read data hold time t dhr 0ns 10 d write data delay time t ddw ?ns 11 d write data hold time t dhw 0ns 12 d read/write data delay time 3 3 includes lstrb t rwd ? 5 ns 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 969 a.9.4 emulation expanded mode (with optional access stretching) figure a-14. example 2b: emulation expanded mode ?read with 1 stretch cycle eclk addr r/ w datax lstrb eclk2x 1 2 3 4 5 6 8 9 12 12 addr [19:16]/ (read) data1 7 data0 addr1 ? addr1 addr2 addr1 iqstat0 addr1 addr2 addr [22:20]/ addr1 acc1 addr1 000 addr2 [15:0]/ iqstat1 acc [2:0] iqstat [3:0] ivd [15:0] ivd1 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 970 freescale semiconductor figure a-15. example 2b: emulation expanded mode ?write with 1 stretch cycle eclk r/ w datax (write) data1 lstrb eclk2x 11 10 1 2 3 4 5 6 7 12 12 addr1 ? addr1 x addr2 addr1 iqstat0 addr1 addr2 addr1 acc1 addr1 000 addr2 iqstat1 addr addr [19:16]/ addr [22:20]/ [15:0]/ acc [2:0] iqstat [3:0] ivd [15:0] 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 971 table a-28. example 2b: emulation expanded mode timing v dd5 = 5.0 v ( ew aite = 0) no. c characteristic 1 1 typical supply and silicon, room temperature only symbol 1 stretch cycle 2 stretch cycles 3 stretch cycles unit min max min max min max internal cycle time t cyc 25 25 25 25 25 25 ns 1 cycle time t cyce 50 75 100 ns 2 d pulse width, e high pw eh 11.5 14 11.5 14 11.5 14 ns 3 d e falling to sampling e rising t efsr 35 39.5 60 64.5 85 89.5 ns 4 d address delay time t ad ???ns 5 d address hold time t ah 0??ns 6 d ivd delay time 2 2 includes also accx, iqstatx t ivdd 4.5 4.5 4.5 ns 7 d ivd hold time 2 t ivdh 0??ns 8 d read data setup time t dsr 12 12 12 ns 9 d read data hold time t dhr 0??ns 10 d write data delay time t ddw ???ns 11 d write data hold time t dhw 0??ns 12 d read/write data delay time 3 3 includes lstrb t rwd ? 5 1 5 ? 5 ns 4 .com u datasheet
appendix a electrical characteristics MC9S12XHZ512 data sheet, rev. 1.02 972 freescale semiconductor a.9.5 external tag trigger timing figure a-16. external trigger timing table a-29. external tag trigger timing v dd5 = 5.0 v no. c characteristic 1 1 typical supply and silicon, room temperature only symbol min max unit 1 d frequency of internal bus f i d.c. 40.0 mhz 2 d cycle time t cyc 25 ns 3d t a ghi/ t a glo setup time t ts 11.5 ns 4d t a ghi/ t a glo hold time t th 0ns eclk r/ w datax t a ghi/ t a glo 2 3 data addr addr 1 4 .com u datasheet
appendix b package information MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 973 appendix b package information this section provides the physical dimensions of the MC9S12XHZ512 packages. 4 .com u datasheet
appendix b package information MC9S12XHZ512 data sheet, rev. 1.02 974 freescale semiconductor b.1 144-pin lqfp figure b-1. 144-pin lqfp mechanical dimensions (case no. 918-03) n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m t l-m dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 0 07 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35. 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 0.25 view ab n 0.20 t l-m m l n 2 t t 144x x 4 .com u datasheet
appendix b package information MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 975 b.2 112-pin lqfp package figure b-2. 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0 4 .com u datasheet
appendix c pcb layout guidelines MC9S12XHZ512 data sheet, rev. 1.02 976 freescale semiconductor appendix c pcb layout guidelines the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible to the corresponding pins (c1?9). central point of the ground star should be the v ss1 pin. use low ohmic low inductance connections between v ss1 , v ss2 , v ssa , v ssx1,2 and v ssm1,2,3 . ? sspll must be directly connected to v ss1 . keep traces of v sspll , extal and xtal as short as possible and occupied board area for c10, c11, c14 and q1 as small as possible. do not place other signals or supplies underneath area occupied by c10, c11, c14 and q1 and the connection area to the mcu. central power input should be fed in at the v dda /v ssa pins. table c-1. recommended components component purpose type value c1 v dd1 ?ter cap ceramic x7r >=400 nf c2 v dda ?ter cap x7r/tantalum >=100 nf c3 v ddx2 ?ter cap x7r/tantalum >=100 nf c4 v ddr ?ter cap x7r/tantalum >=100 nf c5 v ddm3 ?ter cap x7r/tantalum >=100 nf c6 v ddm2 ?ter cap x7r/tantalum >=100 nf c7 v ddm1 ?ter cap x7r/tantalum >=100 nf c8 v ddx1 ?ter cap x7r/tantalum >=100 nf c9 v ddpll ?ter cap ceramic x7r 100 nf .. 220 nf c10 osc load cap see crg block description chapter c11 osc load cap c12 pll loop ?ter cap c13 pll loop ?ter cap c14 dc cutoff cap r1 pll loop ?ter res q1 quartz/resonator 4 .com u datasheet
appendix c pcb layout guidelines MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 977 figure c-1. lqfp144 recommended pcb layout c8 vssx1 vddx1 c6 vddm2 vssm2 c7 vddm1 vssm1 c5 vddm3 vssm3 c9 c4 c10 c11 q1 c13 c12 r1 vddr/ vddpll vsspll c3 vddx2 c2 c1 vdd1 vss1 vdda vssa c14 4 .com u datasheet
appendix c pcb layout guidelines MC9S12XHZ512 data sheet, rev. 1.02 978 freescale semiconductor figure c-2. lqfp112 recommended pcb layout c9 c4 c6 c8 c2 c1 c10 c11 q1 c13 c12 r1 v ssx1 v ddx1 v ddr / v ddm2 v ssm2 v dd1 v ss1 v ddpll v sspll v dda v ssa c3 c7 v ddm1 v ssm1 v ddx2 c5 v ddm3 v ssm3 c14 4 .com u datasheet
appendix d ordering information MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 979 appendix d ordering information the following ?ure provides an ordering number example for the MC9S12XHZ512. figure d-1. order part number example customers who place orders using the generic mc partnumbers which are constructed using the above rules will automatically receive our preferred maskset (ie preferred revision of silicon). if the product is updated in the future and a newer maskset is put into production, then the newer maskset may automatically ship against these generic mc partnumbers. if required, a customer can specify a particular maskset when ordering product. to do this, the customer must order the corresponding "sc" partnumber from the below table. orders placed against these sc partnumbers will only ever receive one speci? maskset. if a new maskset is made available, customers will be noti?d by pcn (process change noti?ation) but will have to order against a different sc part number in order to receive the new maskset. the marking on the device will be as per the left hand column in the below table independently of whether the mc or the sc partnumber is ordered. mc9s12x hz512 c al package option temperature option device title controller family temperature options c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c package options al = 112 lqfp ag = 144 lqfp 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 980 freescale semiconductor appendix e detailed register map the following tables show the detailed register map of the MC9S12XHZ512. 0x0000?x0009 port integration module (pim) map 1 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0000 porta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 w 0x0001 portb r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddrb r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w 0x0004 portc r pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 w 0x0005 portd r pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 w 0x0006 ddrc r ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 w 0x0007 ddrd r ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 w 0x0008 porte r pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 w 0x0009 ddre r ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 00 w 0x000a?x000b module mapping control (s12xmmc) map 1 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000a mmcctl0 r00000 cs2e cs1e cs0e w 0x000b mode r modc modb moda 00000 w 0x000c?x000d port integration module (pim) map 2 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000c pucr r pupke bkgpe 0 pupee pupde pupce pupbe pupae w 0x000d rdriv r rdpk 00 rdpe rdpd rdpc rdpb rdpa w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 981 0x000e?x000f external bus interface (s12xebi) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000e ebictl0 r ithrs 0 hdbe asiz4 asiz3 asiz2 asiz1 asiz0 w 0x000f ebictl1 r ewaite 0000 exstr2 exstr1 exstr0 w 0x0010?x0017 module mapping control (s12xmmc) map 2 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0010 gpage r0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r00000000 w 0x0013 mmcctl1 r00000 eromon romhm romon w 0x0014 reserved r00000000 w 0x0015 reserved r00000000 w 0x0016 rpage r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w 0x0017 epage r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w 0x0018?x001b miscellaneous peripheral address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0018 reserved r00000000 w 0x0019 reserved r00000000 w 0x001a partidh r11100100 w 0x001b partidl r00000000 w 0x001c?x001f port integration module (pim) map 3 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001c eclkctl r neclk nclkx2 0000 ediv1 ediv0 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 982 freescale semiconductor 0x001d reserved r00000000 w 0x001e irqcr r irqe irqen 000000 w 0x001f srcr r srrk 00 srre srrd srrc srrb srra w 0x0020?x0027 debug module (s12xdbg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0020 dbgc1 r arm 0 xgsbpe bdm dbgbrk comrv w trig 0x0021 dbgsr r tbf extf 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r tsource trange trcmod talign w 0x0023 dbgc2 r0 0 0 0 cdcm abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r 0 cnt w 0x0027 dbgscrx r0 0 0 0 sc3 sc2 sc1 sc0 w 0x0028 1 1 this represents the contents if the comparator a or c control register is blended into this address dbgxctl (compa/c) r0 ndb tag brk rw rwe src compe w 0x0028 2 2 this represents the contents if the comparator b or d control register is blended into this address dbgxctl (compb/d) r sze sz tag brk rw rwe src compe w 0x0029 dbgxah r0 bit 22 21 20 19 18 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 54321 bit 0 w 0x002c dbgxdh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgxdl r bit 7 6 54321 bit 0 w 0x002e dbgxdhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgxdlm r bit 7 6 54321 bit 0 w 0x001c?x001f port integration module (pim) map 3 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 983 0x0030?x0031 module mapping control (s12xmmc) map 3 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0030 ppage r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0031 reserved r00000000 w 0x0032?x0033 port integration module (pim) map 4 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0032 portk r pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 w 0x0033 ddrk r ddrk7 ddrk6 ddrk5 ddrk4 ddrk3 ddrk2 ddrk1 ddrk0 w 0x0034?x003f clock and reset generator (crg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0034 synr r0 0 syn5 syn4 syn3 syn2 syn1 syn0 w 0x0035 refdv r 00 refdv5 refdv4 refdv3 refdv2 refdv1 refdv0 w 0x0036 ctflg r00000000 w reserved for factory test 0x0037 crgflg r rtif porf lvrf lockif lock track scmif scm w 0x0038 crgint r rtie ilaf 0 lockie 00 scmie 0 w 0x0039 clksel r pllsel pstp 00 pllwai 0 rtiwai copwai w 0x003a pllctl r cme pllon auto acq fstwkp pre pce scme w 0x003b rtictl r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c copctl r wcop rsbck 000 cr2 cr1 cr0 w 0x003d forbyp r00000000 w reserved for factory test 0x003e ctctl r0000 000 w reserved for factory test 0x003f armcop r00000000 w bit 7 6 54321 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 984 freescale semiconductor 0x0040?x007f enhanced capture timer 16-bit 8-channels (ect) map (sheet 1 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0040 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x0041 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0042 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x0043 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0044 tcnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0045 tcnt (lo) r bit 7 6 54321 bit 0 w 0x0046 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x0047 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0048 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0049 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x004a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x004b tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x004c tie r c7i c6i c5i c4i c3i c2i c1i c0i w 0x004d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x004e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x004f tflg2 r tof 0000000 w 0x0050 tc0 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0051 tc0 (lo) r bit 7 6 54321 bit 0 w 0x0052 tc1 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0053 tc1 (lo) r bit 7 6 54321 bit 0 w 0x0054 tc2 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0055 tc2 (lo) r bit 7 6 54321 bit 0 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 985 0x0056 tc3 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0057 tc3 (lo) r bit 7 6 54321 bit 0 w 0x0058 tc4 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0059 tc4 (lo) r bit 7 6 54321 bit 0 w 0x005a tc5 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x005b tc5 (lo) r bit 7 6 54321 bit 0 w 0x005c tc6 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x005d tc6 (lo) r bit 7 6 54321 bit 0 w 0x005e tc7 (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x005f tc7 (lo) r bit 7 6 54321 bit 0 w 0x0060 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0061 paflg r000000 paovf paif w 0x0062 pacn3 (hi) r bit 7 6 54321 bit 0 w 0x0063 pacn2 (lo) r bit 7 6 54321 bit 0 w 0x0064 pacn1 (hi) r bit 7 6 54321 bit 0 w 0x0065 pacn0 (lo) r bit 7 6 54321 bit 0 w 0x0066 mcctl r mczi modmc rdmcl 00 mcen mcpr1 mcpr0 w iclat flmc 0x0067 mcflg r mczf 0 0 0 polf3 polf2 polf1 polf0 w 0x0068 icpar r0 0 0 0 pa3en pa2en pa1en pa0en w 0x0069 dlyct r dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 w 0x006a icovw r novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 w 0x006b icsys r sh37 sh26 sh15 sh04 tfmod pacmx bufen latq w 0x006c ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x0040?x007f enhanced capture timer 16-bit 8-channels (ect) map (sheet 2 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 986 freescale semiconductor 0x006d timtst r00000000 w reserved for factory test 0x006e ptpsr r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w 0x006f ptmcpsr r ptmps7 ptmps6 ptmps5 ptmps4 ptmps3 ptmps2 ptmps1 ptmps0 w 0x0070 pbctl r0 pben 0000 pbovi 0 w 0x0071 pbflg r000000 pbovf 0 w 0x0072 pa3h r pa3h7 pa3h6 pa3h5 pa3h4 pa3h3 pa3h2 pa3h1 pa3h0 w 0x0073 pa2h r pa2h7 pa2h6 pa2h5 pa2h4 pa2h3 pa2h2 pa2h1 pa2h0 w 0x0074 pa1h r pa1h7 pa1h6 pa1h5 pa1h4 pa1h3 pa1h2 pa1h1 pa1h 0 w 0x0075 pa0h r pa0h7 pa0h6 pa0h5 pa0h4 pa0h3 pa0h2 pa0h1 pa0h0 w 0x0076 mccnt (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0077 mccnt (lo) r bit 7 6 54321 bit 0 w 0x0078 tc0h (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x0079 tc0h (lo) r bit 7 6 54321 bit 0 w 0x007a tc1h (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x007b tc1h (lo) r bit 7 6 54321 bit 0 w 0x007c tc2h (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x007d tc2h (lo) r bit 7 6 54321 bit 0 w 0x007e tc3h (hi) r bit 15 14 13 12 11 10 9 bit 8 w 0x007f tc3h (lo) r bit 7 6 54321 bit 0 w 0x0040?x007f enhanced capture timer 16-bit 8-channels (ect) map (sheet 3 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 987 0x0080?x00af analog-to-digital converter 10-bit 16-channels (atd) map (sheet 1 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0080 atdctl0 r0 0 0 0 wrap3 wrap2 wrap1 wrap0 w 0x0081 atdctl1 r etrig sel 000 etrig ch3 etrig ch2 etrig ch1 etrig ch0 w 0x0082 atdctl2 r adpu affc awai etrigle etrigp etrige ascie ascif w 0x0083 atdctl3 r0 s8c s4c s2c s1c fifo frz1 frz0 w 0x0084 atdctl4 r sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 w 0x0085 atdctl5 r djm dsgn scan mult cd cc cb ca w 0x0086 atdstat0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x0087 reserved r00000000 w 0x0088 atdtest0 ruuuuuuuu w reserved for factory test 0x0089 atdtest1 r00000000 w reserved for factory test 0x008a atdstat2 r ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 w 0x008b atdstat1 r ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 w 0x008c atddien0 r ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 w 0x008d atddien r ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 w 0x008e atdptad0 r ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 w 0x008f atdptad1 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w 0x0090 atddr0h r bit15 14 13 12 11 10 9 bit8 w 0x0091 atddr0l r bit7 bit6 000000 w 0x0092 atddr1h r bit15 14 13 12 11 10 9 bit8 w 0x0093 atddr1l r bit7 bit6 000000 w 0x0094 atddr2h r bit15 14 13 12 11 10 9 bit8 w 0x0095 atddr2l r bit7 bit6 000000 w 0x0096 atddr3h r bit15 14 13 12 11 10 9 bit8 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 988 freescale semiconductor 0x0097 atddr3l r bit7 bit6 000000 w 0x0098 atddr4h r bit15 14 13 12 11 10 9 bit8 w 0x0099 atddr4l r bit7 bit6 000000 w 0x009a atddr5h r bit15 14 13 12 11 10 9 bit8 w 0x009b atddr5l r bit7 bit6 000000 w 0x009c atddr6h r bit15 14 13 12 11 10 9 bit8 w 0x009d atddr6l r bit7 bit6 000000 w 0x009e atddr7h r bit15 14 13 12 11 10 9 bit8 w 0x009f atddr7l r bit7 bit6 000000 w 0x00a0 atddr8h r bit15 14 13 12 11 10 9 bit8 w 0x00a1 atddr8l r bit7 bit6 000000 w 0x00a2 atddr9h r bit15 14 13 12 11 10 9 bit8 w 0x00a3 atddr9l r bit7 bit6 000000 w 0x00a4 atddr10h r bit15 14 13 12 11 10 9 bit8 w 0x00a5 atddr10l r bit7 bit6 000000 w 0x00a6 atddr11h r bit15 14 13 12 11 10 9 bit8 w 0x00a7 atddr11l r bit7 bit6 000000 w 0x00a8 atddr12h r bit15 14 13 12 11 10 9 bit8 w 0x00a9 atddr12l r bit7 bit6 000000 w 0x00aa atddr13h r bit15 14 13 12 11 10 9 bit8 w 0x00ab atddr13l r bit7 bit6 000000 w 0x00ac atddr14h r bit15 14 13 12 11 10 9 bit8 w 0x0080?x00af analog-to-digital converter 10-bit 16-channels (atd) map (sheet 2 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 989 0x00ad atddr14l r bit7 bit6 000000 w 0x00ae atddr15h r bit15 14 13 12 11 10 9 bit8 w 0x00af atddr15l r bit7 bit6 000000 w 0x00b0?x00bf interrupt module (s12xint) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00b0 reserved r00000000 w 0x00b1 ivbr r ivb_addr[7:0] w 0x00b2 reserved r00000000 w 0x00b3 reserved r00000000 w 0x00b4 reserved r00000000 w 0x00b5 reserved r00000000 w 0x00b6 int_xgprio r00000 xilvl[2:0] w 0x00b7 int_cfaddr r int_cfaddr[7:4] 0000 w 0x00b8 int_cfdata0 r rqst 0000 priolvl[2:0] w 0x00b8 int_cfdata1 r rqst 0000 priolvl[2:0] w 0x00b9 int_cfdata2 r rqst 0000 priolvl[2:0] w 0x00ba int_cfdata3 r rqst 0000 priolvl[2:0] w 0x00bb int_cfdata4 r rqst 0000 priolvl[2:0] w 0x00bc int_cfdata5 r rqst 0000 priolvl[2:0] w 0x00be int_cfdata6 r rqst 0000 priolvl[2:0] w 0x00bf int_cfdata7 r rqst 0000 priolvl[2:0] w 0x0080?x00af analog-to-digital converter 10-bit 16-channels (atd) map (sheet 3 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 990 freescale semiconductor 0x00c0?x00c7 inter ic bus (iic0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00c0 ib0ad r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w 0x00c1 ib0fd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w 0x00c2 ib0cr r iben ibie ms/ sl tx/ rx txak 00 ibswai w rsta 0x00c3 ib0sr r tcf iaas ibb ibal 0srw ibif rxak w 0x00c4 ib0dr r d7 d6 d5 d4 d3 d2 d1 d 0 w 0x00c5 ib0cr2 r gcen adtype 0 0 0 adr10 adr9 adr8 w 0x00c6 reserved r00000000 w 0x00c7 reserved r00000000 w 0x00c8?x00cf asynchronous serial interface (sci0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00c8 sci0bdh 1 1 those registers are accessible if the amap bit in the sci0sr2 register is set to zero r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00c9 sci0bdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00ca sci0cr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x00c8 sci0asr1 2 2 those registers are accessible if the amap bit in the sci0sr2 register is set to one r rxedgif 0000 berrv berrif bkdif w 0x00c9 sci0acr1 2 r rxedgie 00000 berrie bkdie w 0x00ca sci0acr2 2 r00000 berrm1 berrm0 bkdfe w 0x00cb sci0cr2 r tie tcie rie ilie te re rwu sbk w 0x00cc sci0sr1 r tdre tc rdrf idle or nf fe pf w 0x00cd sci0sr2 r amap 00 txpol rxpol brk13 txdir raf w 0x00ce sci0drh rr8 t8 000000 w 0x00cf sci0drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 991 0x00d0?x00d7 asynchronous serial interface (sci1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d0 sci1bdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00d1 sci1bdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00d2 sci1cr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x00d0 sci1asr1 2 r rxedgif 0000 berrv berrif bkdif w 0x00d1 sci1acr1 2 r rxedgie 00000 berrie bkdie w 0x00d2 sci1acr2 2 r00000 berrm1 berrm0 bkdfe w 0x00d3 sci1cr2 r tie tcie rie ilie te re rwu sbk w 0x00d4 sci1sr1 r tdre tc rdrf idle or nf fe pf w 0x00d5 sci1sr2 r amap 00 txpol rxpol brk13 txdir raf w 0x00d6 sci1drh rr8 t8 000000 w 0x00d7 sci1drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1 those registers are accessible if the amap bit in the sci1sr2 register is set to zero 2 those registers are accessible if the amap bit in the sci1sr2 register is set to one 0x00d8?x00df serial peripheral interface (spi) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d8 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00d9 spicr2 r0 0 0 modfen bidiroe 0 spiswai spc0 w 0x00da spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00db spisr r spif 0 sptef modf 0 0 0 0 w 0x00dc reserved r00000000 w 0x00dd spidr r bit7 6 54321 bit0 w 0x00de reserved r00000000 w 0x00df reserved r00000000 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 992 freescale semiconductor 0x00e0?x00ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e0 0x00ff reserved r00000000 w 0x0100?x010f flash control register (ftx512k4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0100 fclkdiv r fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0102 ftstmod r0 mrds wrall 0000 w 0x0103 fcnfg r cbeie ccie keyacc 00000 w 0x0104 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0105 fstat r cbeif ccif pviol accerr 0 blank 0 0 w 0x0106 fcmd r0 cmdb[6:0] w 0x0107 fctl r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0108 faddrhi r faddrhi w 0x0109 faddrlo r faddrlo w 0x010a fdatahi r fdatahi w 0x010b fdatalo r fdatalo w 0x010c reserved r00000000 w 0x010d reserved r00000000 w 0x010e reserved r00000000 w 0x010f reserved r00000000 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 993 0x0110?x011b eeprom control register (eetx4k) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0110 eclkdiv r edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 w 0x0111 reserved r00000000 w 0x0112 reserved r00000000 w 0x0113 ecnfg r cbeie ccie 000000 w 0x0114 eprot r epopen rnv6 rnv5 rnv4 epdis eps2 eps1 eps0 w 0x0115 estat r cbeif ccif pviol accerr 0 blank 0 0 w 0x0116 ecmd r0 cmdb[6:0] w 0x0117 reserved r00000000 w 0x0118 eaddrhi r 0 0 0 0 0 eabhi w 0x0119 eaddrlo r eablo w 0x011a edatahi r edhi w 0x011b edatalo r edlo w 0x011c?x011f memory map control (s12xmmc) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x011c ramwpc r rpwe 00000 avie avif w 0x011d ramxgu r1 xgu6 xgu5 xgu4 xgu3 xgu2 xgu1 xgu0 w 0x011e ramshl r1 shl6 shl5 shl4 shl3 shl2 shl1 shl0 w 0x011f ramshu r1 shu6 shu5 shu4 shu3 shu2 shu1 shu0 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 994 freescale semiconductor 0x0120?x0137 liquid crystal display 32x4 (lcd) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0120 lcdcr0 r lcden 0 lclk2 lclk1 lclk0 bias duty1 duty0 w 0x0121 lcdcr1 r000000 lcdswai lcdrpst p w 0x0122 fpenr0 r fpen7 fpen6 fpen5 fpen4 fpen3 fpen2 fpen1 fpen0 w 0x0123 fpenr1 r fpen15 fpen14 fpen13 fpen12 fpen11 fpen10 fpen9 fpen8 w 0x0124 fpenr2 r fpen23 fpen22 fpen21 fpen20 fpen19 fpen18 fpen17 fpen16 w 0x0125 fpenr3 r fpen31 fpen30 fpen29 fpen28 fpen27 fpen26 fpen25 fpen24 w 0x0126 reserved r00000000 w 0x0127 reserved r00000000 w 0x0128 lcdram0 r fp1bp3 fp1bp2 fp1bp1 fp1bp0 fp0bp3 fp0bp2 fp0bp1 fp0bp0 w 0x0129 lcdram1 r fp3bp3 fp3bp2 fp3bp1 fp3bp0 fp2bp3 fp2bp2 fp2bp1 fp2bp0 w 0x012a lcdram2 r fp5bp3 fp5bp2 fp5bp1 fp5bp0 fp4bp3 fp4bp2 fp4bp1 fp4bp0 w 0x012b lcdram3 r fp7bp3 fp7bp2 fp7bp1 fp7bp0 fp6bp3 fp6bp2 fp6bp1 fp6bp0 w 0x012c lcdram4 r fp9bp3 fp9bp2 fp9bp1 fp9bp0 fp8bp3 fp8bp2 fp8bp1 fp8bp0 w 0x012d lcdram5 r fp11bp3 fp11bp2 fp11bp1 fp11bp0 fp10bp3 fp10bp2 fp10bp1 fp10bp0 w 0x012e lcdram6 r fp13bp3 fp13bp2 fp13bp1 fp13bp0 fp12bp3 fp12bp2 fp12bp1 fp12bp0 w 0x012f lcdram7 r fp15bp3 fp15bp2 fp15bp1 fp15bp0 fp14bp3 fp14bp2 fp14bp1 fp14bp0 w 0x0130 lcdram8 r fp17bp3 fp17bp2 fp17bp1 fp17bp0 fp16bp3 fp16bp2 fp16bp1 fp16bp0 w 0x0131 lcdram9 r fp19bp3 fp19bp2 fp19bp1 fp19bp0 fp18bp3 fp18bp2 fp18bp1 fp18bp0 w 0x0132 lcdram10 r fp21bp3 fp21bp2 fp21bp1 fp21bp0 fp20bp3 fp20bp2 fp20bp1 fp20bp0 w 0x0133 lcdram11 r fp23bp3 fp23bp2 fp23bp1 fp23bp0 fp22bp3 fp22bp2 fp22bp1 fp22bp0 w 0x0134 lcdram12 r fp25bp3 fp25bp2 fp25bp1 fp25bp0 fp24bp3 fp24bp2 fp24bp1 fp24bp0 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 995 0x0135 lcdram13 r fp27bp3 fp27bp2 fp27bp1 fp27bp0 fp26bp3 fp26bp2 fp26bp1 fp26bp0 w 0x0136 lcdram14 r fp29bp3 fp29bp2 fp29bp1 fp29bp0 fp28bp3 fp28bp2 fp28bp1 fp28bp0 w 0x0137 lcdram15 r fp31bp3 fp31bp2 fp31bp1 fp31bp0 fp30bp3 fp30bp2 fp30bp1 fp30bp0 w 0x0138?x013f inter ic bus (iic1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0138 ib1ad r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w 0x0139 ib1fd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w 0x013a ib1cr r iben ibie ms/ sl tx/ rx txak 00 ibswai w rsta 0x013b ib1sr r tcf iaas ibb ibal 0srw ibif rxak w 0x013c ib1dr r d7 d6 d5 d4 d3 d2 d1 d 0 w 0x013d ib1cr2 r gcen adtype 0 0 0 adr10 adr9 adr8 w 0x013e reserved r00000000 w 0x013f reserved r00000000 w 0x0140?x017f freescale scalable can ?mscan (can0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0140 can0ctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0141 can0ctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0142 can0btr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0143 can0btr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0144 can0rflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0145 can0rier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0146 can0tflg r00000 txe2 txe1 txe0 w 0x0147 can0tier r00000 txeie2 txeie1 txeie0 w 0x0120?x0137 liquid crystal display 32x4 (lcd) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 996 freescale semiconductor 0x0148 can0tarq r00000 abtrq2 abtrq1 abtrq0 w 0x0149 can0taak r 0 0 0 0 0 abtak2 abtak1 abtak0 w 0x014a can0tbsel r00000 tx2 tx1 tx0 w 0x014b can0idac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x014c reserved r00000000 w 0x014d can0misc r0000000 bohold w 0x014e can0rxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w 0x014f can0txerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0150 0x0153 can0idar0 can0idar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0154 0x0157 can0idmr0 can0idmr3 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0158 0x015b can0idar4 can0idar7 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x015c 0x015f can0idmr4 can0idmr7 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0160 0x016f can0rxfg r foreground receive buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x0170 0x017f can0txfg r foreground transmit buffer (see detailed mscan foreground receive and transmit buffer layout ) w detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xxxx0 extended id r id28 id27 id26 id25 id24 id23 id22 id21 standard id r id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 w 0xxxx1 extended id r id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id r id2 id1 id0 rtr ide=0 canxridr1 w 0xxxx2 extended id r id14 id13 id12 id11 id10 id9 id8 id7 standard id r canxridr2 w 0xxxx3 extended id r id6 id5 id4 id3 id2 id1 id0 rtr standard id r canxridr3 w 0x0140?x017f freescale scalable can ?mscan (can0) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 997 0xxxx4 0xxxxb canxrdsr0 canxrdsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0xxxxc canrxdlr r dlc3 dlc2 dlc1 dlc0 w 0xxxxd reserved r w 0xxxxe canxrtsrh r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w 0xxxxf canxrtsrl r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w 0xxx10 extended id r id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 w standard id r id10 id9 id8 id7 id6 id5 id4 id3 w 0xxx0x xx10 extended id r id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 w standard id r id2 id1 id0 rtr ide=0 w 0xxx12 extended id r id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 w standard id r w 0xxx13 extended id r id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 w standard id r w 0xxx14 0xxx1b canxtdsr0 canxtdsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0xxx1c canxtdlr r dlc3 dlc2 dlc1 dlc0 w 0xxx1d canxttbpr r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w 0xxx1e canxttsrh r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w 0xxx1f canxttsrl r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w detailed mscan foreground receive and transmit buffer layout (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 998 freescale semiconductor 0x0180?x01bf freescale scalable can ?mscan (can1) map (sheet 1 of 2) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0180 can1ctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0181 can1ctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0182 can1btr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0183 can1btr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0184 can1rflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0185 can1rier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0186 can1tflg r00000 txe2 txe1 txe0 w 0x0187 can1tier r00000 txeie2 txeie1 txeie0 w 0x0188 can1tarq r00000 abtrq2 abtrq1 abtrq0 w 0x0189 can1taak r 0 0 0 0 0 abtak2 abtak1 abtak0 w 0x018a can1tbsel r00000 tx2 tx1 tx0 w 0x018b can1idac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x018c reserved r00000000 w 0x018d can1misc r0000000 bohold w 0x018e can1rxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w 0x018f can1txerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0190 can1idar0 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0191 can1idar1 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0192 can1idar2 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0193 can1idar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0194 can1idmr0 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0195 can1idmr1 r am7 am6 am5 am4 am3 am2 am1 am0 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 999 0x0196 can1idmr2 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0197 can1idmr3 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0198 can1idar4 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0199 can1idar5 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x019a can1idar6 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x019b can1idar7 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x019c can1idmr4 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x019d can1idmr5 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x019e can1idmr6 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x019f can1idmr7 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x01a0 0x01af can1rxfg r foreground receive buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x01b0 0x01bf can1txfg r foreground transmit buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x01c0?x01ff motor controller 10-bit 12-channels (mc) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01c0 mcctl0 r0 mcpre1 mcpre0 mcswai fast dith 0 mctoif w 0x01c1 mcctl1 r recirc 000000 mctoie w 0x01c2 mcper (hi) r00000 p10 p9 p8 w 0x01c3 mcper (lo) r p7 p6 p5 p4 p3 p2 p1 p0 w 0x01c4 0x01cf reserved r00000000 w 0x01d0 mccc0 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d1 mccc1 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d2 mccc2 r om1 om0 am1 am0 00 cd1 cd0 w 0x0180?x01bf freescale scalable can ?mscan (can1) map (sheet 2 of 2) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1000 freescale semiconductor 0x01d3 mccc3 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d4 mccc4 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d5 mccc5 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d6 mccc6 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d7 mccc7 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d8 mccc8 r om1 om0 am1 am0 00 cd1 cd0 w 0x01d9 mccc9 r om1 om0 am1 am0 00 cd1 cd0 w 0x01da mccc10 r om1 om0 am1 am0 00 cd1 cd0 w 0x01db mccc11 r om1 om0 am1 am0 00 cd1 cd0 w 0x01dc 0x01df reserved r00000000 w 0x01e0 mcdc0 (hi) r s ssss d10 d9 d8 w 0x01e1 mcdc0 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e2 mcdc1 (hi) r s ssss d10 d9 d8 w 0x01e3 mcdc1 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e4 mcdc2 (hi) r s ssss d10 d9 d8 w 0x01e5 mcdc2 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e6 mcdc3 (hi) r s ssss d10 d9 d8 w 0x01e7 mcdc3 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e8 mcdc4 (hi) r s ssss d10 d9 d8 w 0x01e9 mcdc4 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01ea mcdc5 (hi) r s ssss d10 d9 d8 w 0x01eb mcdc5 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01ec mcdc6 (hi) r s ssss d10 d9 d8 w 0x01c0?x01ff motor controller 10-bit 12-channels (mc) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1001 0x01ed mcdc6 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01ee mcdc7 (hi) r s ssss d10 d9 d8 w 0x01ef mcdc7 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01f0 mcdc8 (hi) r s ssss d10 d9 d8 w 0x01f1 mcdc8 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01f2 mcdc9 (hi) r s ssss d10 d9 d8 w 0x01f3 mcdc9 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01f4 mcdc10 (hi) r s ssss d10 d9 d8 w 0x01f5 mcdc10 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01f6 mcdc11 (hi) r s ssss d10 d9 d8 w 0x01f7 mcdc11 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01f8 0x01ff reserved r00000000 w 0x0200?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0200 ptt r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w 0x0201 ptit r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w 0x0202 ddrt r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w 0x0203 rdrt r rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 w 0x0204 pert r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w 0x0205 ppst r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w 0x0206 womt r womt7 womt6 womt5 womt4 0 modrr2 modrr1 modrr0 w 0x0207 srrt r srrt7 srrt6 srrt5 srrt4 srrt3 srrt2 srrt1 srrt0 w 0x01c0?x01ff motor controller 10-bit 12-channels (mc) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1002 freescale semiconductor 0x0208 pts r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w 0x0209 ptis r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w 0x020a ddrs r ddrs7 ddrs7 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w 0x020b rdrs r rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 w 0x020c pers r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w 0x020d ppss r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w 0x020e woms r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w 0x020f srrs r srrs7 srrs6 srrs5 srrs4 srrs3 srrs2 srrs1 srrs0 w 0x0210 ptm r0 0 ptm5 ptm4 ptm3 ptm2 ptm1 0 w 0x0211 ptim r 0 0 ptim5 ptim4 ptim3 ptim2 ptim1 0 w 0x0212 ddrm r0 0 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 0 w 0x0213 rdrm r0 0 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 0 w 0x0214 perm r0 0 perm5 perm4 perm3 perm2 perm1 0 w 0x0215 ppsm r0 0 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 0 w 0x0216 womm r0 0 womm5 womm4 womm3 womm2 womm1 0 w 0x0217 srrm r0 0 srrm5 srrm4 srrm3 srrm2 srrm1 0 w 0x0218 ptp r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w 0x0219 ptip r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w 0x021a ddrp r ddrp7 ddrp7 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w 0x021b rdrp r rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 w 0x021c perp r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w 0x021d ppsp r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 w 0x021e womp r womp7 womp6 womp5 womp4 0 womp2 0 womp0 w 0x0200?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1003 0x021f srrp r srrp7 srrp6 srrp5 srrp4 srrp3 srrp2 srrp1 srrp0 w 0x0220 0x022f reserved r00000000 w 0x0230 ptl r ptl7 ptl6 ptl5 ptl4 ptl3 ptl2 ptl1 ptl0 w 0x0231 ptil r ptil7 ptil6 ptil5 ptil4 ptil3 ptil2 ptil1 ptil0 w 0x0232 ddrl r ddrl7 ddrl6 ddrl5 ddrl4 ddrl3 ddrl2 ddrl1 ddrl0 w 0x0233 rdrl r rdrl7 rdrl6 rdrl5 rdrl4 rdrl3 rdrl2 rdrl1 rdrl0 w 0x0234 perl r perl7 perl6 perl5 perl4 perl3 perl2 perl1 perl0 w 0x0235 ppsl r ppsl7 ppsl6 ppsl5 ppsl4 ppsl3 ppsl2 ppsl1 ppsl0 w 0x0236 reserved r00000000 w 0x0237 srrl r srrl7 srrl6 srrl5 srrl4 srrl3 srrl2 srrl1 srrl0 w 0x0238 ptu r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w 0x0239 ptiu r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w 0x023a ddru r ddru7 ddru7 ddru ddru4 ddru3 ddru2 ddru1 ddru0 w 0x023b srru r srru7 srru6 srru5 srru4 srru3 srru2 srru1 srru0 w 0x023c peru r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w 0x023d ppsu r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 w 0x023e reserved r00000000 w 0x023f reserved r00000000 w 0x0240 ptv r ptv7 ptv6 ptv5 ptv4 ptv3 ptv2 ptv1 ptv0 w 0x0241 ptiv r ptiv7 ptiv6 ptiv5 ptiv4 ptiv3 ptiv2 ptiv1 ptiv0 w 0x0242 ddrv r ddrv7 ddrv7 ddrv ddrv4 ddrv3 ddrv2 ddrv1 ddrv0 w 0x0243 srrv r srrv7 srrv6 srrv5 srrv4 srrv3 srrv2 srrv1 srrv0 w 0x0244 perv r perv7 perv6 perv5 perv4 perv3 perv2 perv1 perv0 w 0x0200?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1004 freescale semiconductor 0x0245 ppsv r ppsv7 ppsv6 ppsv5 ppsv4 ppsv3 ppsv2 ppsv1 ppsv0 w 0x0246 reserved r00000000 w 0x0247 reserved r00000000 w 0x0248 ptw r ptw7 ptw6 ptw5 ptw4 ptw3 ptw2 ptw1 ptw0 w 0x0249 ptiw r ptiw7 ptiw6 ptiw5 ptiw4 ptiw3 ptiw2 ptiw1 ptiw0 w 0x024a ddrw r ddrw7 ddrw7 ddrw ddrw4 ddrw3 ddrw2 ddrw1 ddrw0 w 0x024b srrw r srrw7 srrw6 srrw5 srrw4 srrw3 srrw2 srrw1 srrw0 w 0x024c perw r perw7 perw6 perw5 perw4 perw3 perw2 perw1 perw0 w 0x024d ppsw r ppsw7 ppsw6 ppsw5 ppsw4 ppsw3 ppsw2 ppsw1 ppsw0 w 0x024e reserved r00000000 w 0x024f reserved r00000000 w 0x0250 reserved r00000000 w 0x0251 ptad r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w 0x0252 reserved r00000000 w 0x0253 ptiad r ptiad7 ptiad6 ptiad5 ptiad4 ptiad3 ptiad2 ptiad1 ptiad0 w 0x0254 reserved r00000000 w 0x0255 ddrad r ddrad7 ddrad6 ddrad5 ddrad4 ddrad3 ddrad2 ddrad1 ddrad0 w 0x0256 reserved r00000000 w 0x0257 rdrad r rd1ad7 rdrad6 rdrad5 rdrad4 rdrad3 rdrad2 rdrad1 rdrad0 w 0x0258 reserved r00000000 w 0x0259 perad r perad7 perad6 perad5 perad4 perad3 perad2 perad1 perad0 w 0x025a reserved r00000000 w 0x025b ppsad r ppsad7 ppsad6 ppsad5 ppsad4 ppsad3 ppsad2 ppsad1 ppsad0 w 0x0200?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1005 0x025c reserved r00000000 w 0x025d piead r piead7 piead6 piead5 piead4 piead3 piead2 piead1 piead0 w 0x025e reserved r00000000 w 0x025f pifad r pifad7 pifad6 pifad5 pifad4 pifad3 pifad2 pifad1 pifad0 w 0x0260 0x027f reserved r00000000 w 0x0280?x0287 stepper stall detector (ssd4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0280 rtz4ctl r itg dcoil rcir pol 00 step w 0x0281 mdc4ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x0282 ssd4ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x0283 ssd4flg r mczif 000000 aovif w 0x0284 mdc4cnt(hi) r mdccnt[15:8] w 0x0285 mdc4cnt(lo) r mdccnt[7:0] w 0x0286 itg4acc(hi) r itgacc[15:8] w 0x0287 itg4acc(lo) r itgacc[7:0] w 0x0288?x028f stepper stall detector (ssd0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0288 rtz0ctl r itg dcoil rcir pol 00 step w 0x0289 mdc0ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x028a ssd0ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x028b ssd0flg r mczif 000000 aovif w 0x028c mdc0cnt(hi) r mdccnt[15:8] w 0x0200?x027f port integration module (pim) map 5 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1006 freescale semiconductor 0x028d mdc0cnt(lo) r mdccnt[7:0] w 0x028e itg0acc(hi) r itgacc[15:8] w 0x028f itg0acc(lo) r itgacc[7:0] w 0x0290?x0297 stepper stall detector (ssd1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0290 rtz1ctl r itg dcoil rcir pol 00 step w 0x0291 mdc1ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x0292 ssd1ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x0293 ssd1flg r mczif 000000 aovif w 0x0294 mdc1cnt(hi) r mdccnt[15:8] w 0x0295 mdc1cnt(lo) r mdccnt[7:0] w 0x0296 itg1acc(hi) r itgacc[15:8] w 0x0297 itg1acc(lo) r itgacc[7:0] w 0x0298?x029f stepper stall detector (ssd2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0298 rtz2ctl r itg dcoil rcir pol 00 step w 0x0299 mdc2ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x029a ssd2ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x029b ssd2flg r mczif 000000 aovif w 0x029c mdc2cnt(hi) r mdccnt[15:8] w 0x029d mdc2cnt(lo) r mdccnt[7:0] w 0x029e itg2acc(hi) r itgacc[15:8] w 0x029f itg2acc(lo) r itgacc[7:0] w 0x0288?x028f stepper stall detector (ssd0) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1007 0x02a0?x02a7 stepper stall detector (ssd3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02a0 rtz3ctl r itg dcoil rcir pol 00 step w 0x02a1 mdc3ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x02a2 ssd3ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x02a3 ssd3flg r mczif 000000 aovif w 0x02a4 mdc3cnt(hi) r mdccnt[15:8] w 0x02a5 mdc3cnt(lo) r mdccnt[7:0] w 0x02a6 itg3acc(hi) r itgacc[15:8] w 0x02a7 itg3acc(lo) r itgacc[7:0] w 0x02a8?x02af stepper stall detector (ssd5) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02a8 rtz5ctl r itg dcoil rcir pol 00 step w 0x02a9 mdc5ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x02aa ssd5ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x02ab ssd5flg r mczif 000000 aovif w 0x02ac mdc5cnt(hi) r mdccnt[15:8] w 0x02ad mdc5cnt(lo) r mdccnt[7:0] w 0x02ae itg5acc(hi) r itgacc[15:8] w 0x02af itg5acc(lo) r itgacc[7:0] w 0x02b0?x02ef reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02b0 0x02ef reserved r00000000 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1008 freescale semiconductor 0x02f0?x02f7 voltage regulator (vreg_3v3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f0 vreghtcl r reserved for factory test w 0x02f1 vregctrl r00000lvds lvie lvif w 0x02f2 vregapicl r apiclk 0000 apife apie apif w 0x02f3 vregapitr r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w 0x02f4 vregapirh r0 0 0 0 apir11 apir10 apir9 apir8 w 0x02f5 vregapirl r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w 0x02f6 reserved r00000000 w 0x02f7 reserved r00000000 w 0x02f8?x02ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f8 0x02ff reserved r00000000 w 0x0300?x0327 pulse width modulator 8-bit 8-channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0300 pwme r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w 0x0301 pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w 0x0302 pwmclk r pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w 0x0303 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x0304 pwmcae r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w 0x0305 pwmctl r con67 con45 con23 con01 pswai pfrz 00 w 0x0306 pwmtst test only r00000000 w 0x0307 pwmprsc r00000000 w 0x0308 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x0309 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1009 0x030a pwmscnta r00000000 w 0x030b pwmscntb r00000000 w 0x030c pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x030d pwmcnt1 r bit 7 6 54321 bit 0 w00000000 0x030e pwmcnt2 r bit 7 6 54321 bit 0 w00000000 0x030f pwmcnt3 r bit 7 6 54321 bit 0 w00000000 0x0310 pwmcnt4 r bit 7 6 54321 bit 0 w00000000 0x0311 pwmcnt5 r bit 7 6 54321 bit 0 w00000000 0x0312 pwmcnt6 r bit 7 6 54321 bit 0 w00000000 0x0313 pwmcnt7 r bit 7 6 54321 bit 0 w00000000 0x0314 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x0315 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x0316 pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w 0x0317 pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0318 pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0319 pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w 0x031a pwmper6 r bit 7 6 5 4 3 2 1 bit 0 w 0x031b pwmper7 r bit 7 6 5 4 3 2 1 bit 0 w 0x031c pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x031d pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w 0x031e pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w 0x031f pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0320 pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0300?x0327 pulse width modulator 8-bit 8-channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1010 freescale semiconductor 0x0321 pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w 0x0322 pwmdty6 r bit 7 6 5 4 3 2 1 bit 0 w 0x0323 pwmdty7 r bit 7 6 5 4 3 2 1 bit 0 w 0x0324 pwmsdn r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7 ena w pwm rstrt 0x0325 reserved r00000000 w 0x0326 reserved r00000000 w 0x0327 reserved r00000000 w 0x0328?x033f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0328 0x033f reserved r00000000 w 0x0340?x0367 periodic interrupt timer (pit) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0340 pitcflmt r pite pitswai pitfrz 00000 w pflmt1 pflmt0 0x0341 pitflt r00000000 w pflt3 pflt2 pflt1 pflt0 0x0342 pitce r0 0 0 0 pce3 pce2 pce1 pce0 w 0x0343 pitmux r0 0 0 0 pmux3 pmux2 pmux1 pmux0 w 0x0344 pitinte r0 0 0 pinte3 pinte2 pinte1 pinte0 w 0x0345 pittf r0 0 0 0 ptf3 ptf2 ptf1 ptf0 w 0x0346 pitmtld0 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w 0x0347 pitmtld1 r pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 w 0x0348 pitld0 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0349 pitld0 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x0300?x0327 pulse width modulator 8-bit 8-channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1011 0x034a pitcnt0 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x034b pitcnt0 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x034c pitld1 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x034d pitld1 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x034e pitcnt1 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x034f pitcnt1 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0350 pitld2 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0351 pitld2 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x0352 pitcnt2 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x0353 pitcnt2 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0354 pitld3 (hi) r pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 w 0x0355 pitld3 (lo) r pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 w 0x0356 pitcnt3 (hi) r pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 w 0x0357 pitcnt3 (lo) r pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 w 0x0358 0x0367 reserved r00000000 w 0x0368?x037f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0368 0x037f reserved r00000000 w 0x0340?x0367 periodic interrupt timer (pit) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1012 freescale semiconductor 0x0380?x03bf xgate map (sheet 1 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0380 xgmctl r0000000 xgiem w xgem xgfrzm xgdbgm xgssm xgfactm xgs weifm 0x0381 xgmctl r xge xgfrz xgdbg xgss xgfact 0 xgsweif xgie w 0x0382 xgchid r 0 xgchid[6:0] w 0x0383 reserved r w 0x0384 reserved r w 0x0385 reserved r w 0x0386 xgvbr r xgvbr[15:8] w 0x0387 xgvbr r xgvbr[7:1] 0 w 0x0388 xgif r0000000 xgif_78 w 0x0389 xgif r xgif_77 xgif_76 xgif_75 xgif_74 xgif_73 xgif_72 xgif_71 xgif_70 w 0x038a xgif r xgif_6f xgif_6e xgif_6d xgif_6c xgif_6b xgif_6a xgif_69 xgif_68 w 0x023b xgif r xgif_67 xgif_66 xgif_65 xgif_64 xgif_63 xgif_62 xgif_61 xgif_60 w 0x023c xgif r xgif_5f xgif_5e xgif_5d xgif_5c xgif_5b xgif_5a xgif_59 xgif_58 w 0x038d xgif r xgif_57 xgif_56 xgif_55 xgif_54 xgif_53 xgif_52 xgif_51 xgif_50 w 0x038e xgif r xgif_4f xgif_4e xgif_4d xgif_4c xgif_4b xgif_4a xgif_49 xgif_48 w 0x038f xgif r xgif_47 xgif_46 xgif_45 xgif_44 xgif_43 xgif_42 xgif_41 xgif_40 w 0x0390 xgif r xgif_3f xgif_3e xgif_3d xgif_3c xgif_3b xgif_3a xgif_39 xgif_38 w 0x0391 xgif r xgif_37 xgif_36 xgif_35 xgif_34 xgif_33 xgif_32 xgif_31 xgif_30 w 0x0392 xgif r xgif_2f xgif_2e xgif_2d xgif_2c xgif_2b xgif_2a xgif_29 xgif_28 w 0x0393 xgif r xgif_27 xgif_26 xgif_25 xgif_24 xgif_23 xgif_22 xgif_21 xgif_20 w 0x0394 xgif r xgif_1f xgif_1e xgif_1d xgif_1c xgif_1b xgif_1a xgif_19 xgif_18 w 0x0395 xgif r xgif_17 xgif_16 xgif_15 xgif_14 xgif_13 xgif_12 xgif_11 xgif_10 w 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 freescale semiconductor 1013 0x0396 xgif r xgif_0f xgif_0e xgif_0d xgif_0c xgif_0b xgif_0a xgif_09 0 w 0x0397 xgif r00000000 w 0x0398 xgswt (hi) r00000000 w xgswtm[7:0] 0x0399 xgswt (lo) r xgswt[7:0] w 0x039a xgsem (hi) r00000000 w xgsemm[7:0] 0x039b xgsem (lo) r xgsem[7:0] w 0x039c reserved r00000000 w 0x039d xgccr r0 0 0 0 xgn xgz xgv xgc w 0x039e xgpc (hi) r xgpc[15:8] w 0x039f xgpc (lo) r xgpc[7:0] w 0x03a0 reserved r00000000 w 0x03a1 reserved r00000000 w 0x03a2 xgr1 (hi) r xgr1[15:8] w 0x03a3 xgr1 (lo) r xgr1[7:0] w 0x03a4 xgr2 (hi) r xgr2[15:8] w 0x03a5 xgr2 (lo) r xgr2[7:0] w 0x03a6 xgr3 (hi) r xgr3[15:8] w 0x03a7 xgr3 (lo) r xgr3[7:0] w 0x03a8 xgr4 (hi) r xgr4[15:8] w 0x03a9 xgr4 (lo) r xgr4[7:0] w 0x03aa xgr5 (hi) r xgr5[15:8] w 0x03ab xgr5(lo) r xgr5[7:0] w 0x03ac xgr6 (hi) r xgr6[15:8] w 0x0380?x03bf xgate map (sheet 2 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
appendix e detailed register map MC9S12XHZ512 data sheet, rev. 1.02 1014 freescale semiconductor 0x03ad xgr6 (lo) r xgr6[7:0] w 0x03ae xgr7 (hi) r xgr7[15:8] w 0x03af xgr7 (lo) r xgr7[7:0] w 0x03b0 0x03bf reserved r00000000 w 0x03c0?x07ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x03c0 ?x07ff reserved r00000000 w 0x0380?x03bf xgate map (sheet 3 of 3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4 .com u datasheet
4 .com u datasheet
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